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5329 Commits

Author SHA1 Message Date
Stan Lee 04faedd131 syntax err 2026-01-28 17:40:57 -08:00
Stan Lee dfef18010d shorter lines 2026-01-28 17:20:19 -08:00
Stan Lee 932c4452b5 better working implementation 2026-01-28 17:00:46 -08:00
Akash Levy 5a6dffeecd Silimate mods to upstream opt_balance_tree pass 2026-01-21 23:34:34 -08:00
Stan Lee a52689a1fa
Merge branch 'main' into main 2026-01-21 15:46:06 -08:00
Stan Lee 99cf75531f merge 2026-01-21 15:43:25 -08:00
Stan Lee f026cebaf6 address comments 2026-01-21 15:16:45 -08:00
Akash Levy 947139aca1 Remove opt_balance_tree from silimate (now in opt) 2026-01-21 15:15:21 -08:00
Akash Levy b11037e6c6 Merge remote-tracking branch 'upstream/main' 2026-01-21 15:13:57 -08:00
Stan Lee f14eb4a7bb only check reg cells 2026-01-21 15:13:55 -08:00
Stan Lee 269b70c0f9 compiles 2026-01-21 12:32:38 -08:00
Stan Lee 0018037c16 minor changes 2026-01-21 12:25:28 -08:00
Stan Lee e824c8e0d6 ready for review 2026-01-21 09:00:46 -08:00
Stan Lee 31e32af4a8 greptile 2026-01-21 08:54:43 -08:00
Emil J 317a4d77c7
Merge pull request #5610 from nataliakokoromyti/upstream-debugon 
Add debugon pass for persistent debug logging
 2026-01-21 17:34:30 +01:00
Emil J 5e36503676
Merge pull request #5605 from nataliakokoromyti/opt_balance_tree 
Add opt_balance_tree pass
 2026-01-21 17:34:08 +01:00
Stan Lee d2e8f9b8a8 first round fixes 2026-01-20 21:45:13 -08:00
Stan Lee 29061d3051 leave no room for err 2026-01-20 15:55:05 -08:00
Stan Lee 45bd3f4515 change splitcells pass to remove some bracket from register names in blast mode 2026-01-20 15:50:43 -08:00
Stan Lee 60a81a2676 reg rename pass reads from vcd for original widths 2026-01-20 15:35:13 -08:00
Stan Lee a5106da733 line reduction 2026-01-20 11:56:57 -08:00
Stan Lee 0ea4bb8a2d comment 2026-01-20 11:55:54 -08:00
Stan Lee 80364c608e significantly cleaner 2026-01-20 11:29:56 -08:00
Stan Lee c471014878 slightly cleaner 2026-01-19 12:58:36 -08:00
Stan Lee 6303eed1b4 works hierarchy 2026-01-19 12:22:22 -08:00
Stan Lee 186fc15f8f passes simple test 2026-01-19 12:10:48 -08:00
Stan Lee e678e2a0c3 every step except wire connecting 2026-01-19 11:20:11 -08:00
Stan Lee 15026033a3 annotate original register width 2026-01-19 11:19:41 -08:00
Emil J. Tywoniak c3f36afe7f opt_balance_tree: mark experimental 2026-01-19 12:01:25 +01:00
Robert O'Callahan 28c199fbbd Fix warning about unused variable in `dffunmap`. 2026-01-19 03:25:09 +00:00
Akash Levy 7792f0644a
Merge branch 'YosysHQ:main' into main 2026-01-18 17:17:45 -08:00
KrystalDelusion 8da8d681d0
Merge pull request #5544 from YosysHQ/krys/sim_check_eval_err 
Improve error handling in sim
 2026-01-19 09:51:12 +13:00
Stan Lee 4a1af73ec0 activity pass and a vcd writer bug fix 2026-01-16 16:32:04 -08:00
Natalia ed64df737b Add -on/-off modes to debug pass 2026-01-15 12:07:26 -08:00
Akash Levy 33ddae41c3 Remove lut2bmux from silimate after upstreaming 2026-01-14 20:24:26 -08:00
Natalia 305b6c81d7 Refine width check to allow Y_WIDTH >= natural width 
Change from equality check to >= to allow cells where output
is wider than natural width (zero-extended). Only reject cells
with Y_WIDTH < natural width (truncated).

This fixes test failures while still preventing the truncation
issue identified in widlarizer's feedback.
 2026-01-14 14:58:53 -08:00
Natalia 60ac3670cb Fix truncation issue in opt_balance_tree pass 
Only allow rebalancing of cells with "natural" output widths (no truncation).
This prevents equivalence failures when moving operands between adders
with different intermediate truncation points.

For each operation type, the natural width is:
- Addition: max(A_WIDTH, B_WIDTH) + 1 (for carry bit)
- Multiplication: A_WIDTH + B_WIDTH
- Logic ops: max(A_WIDTH, B_WIDTH)

Fixes widlarizer's counterexample in YosysHQ/yosys#5605 where an 8-bit
intermediate wire was intentionally truncating adder results, and
rebalancing would change where that truncation occurred.
 2026-01-14 13:14:56 -08:00
Natalia Kokoromyti 6aef8ea8ab Add missing <deque> include for MSVC compatibility 2026-01-13 15:31:46 -08:00
Natalia Kokoromyti 8b6925c5b0 Add opt_balance_tree pass for timing optimization 
This pass converts cascaded chains of arithmetic and logic cells ($add,
$mul, $and, $or, $xor) into balanced binary trees to improve timing
performance in hardware synthesis.

The optimization uses a breadth-first search approach to identify chains
of compatible cells, then recursively constructs balanced trees that
reduce the critical path depth.

Features:
- Supports arithmetic cells: $add, $mul
- Supports logic cells: $and, $or, $xor
- Command-line options: -arith (arithmetic only), -logic (logic only)
- Preserves signed/unsigned semantics
- Comprehensive test suite with 30 test cases

Original implementation by Akash Levy <akash@silimate.com> for Silimate.
Upstreamed from https://github.com/Silimate/yosys
 2026-01-13 14:20:11 -08:00
Akash Levy a121255f47
Merge branch 'YosysHQ:main' into main 2026-01-13 11:28:34 -08:00
Emil J. Tywoniak 8e2038c419 Use digit separators for large decimal integers 2026-01-13 16:38:12 +01:00
Akash Levy 58192ad8a6
Merge branch 'YosysHQ:main' into main 2026-01-12 22:52:03 -08:00
Miodrag Milanović 51b210c93c
Merge pull request #5600 from YosysHQ/fix_musllinux 
musllinux fix so wheels build can work
 2026-01-13 07:08:04 +01:00
Emil J cc25ccfcd7
Merge pull request #5559 from nataliakokoromyti/upstream-lut2bmux 
add lut2bmux
 2026-01-12 16:09:13 +01:00
Miodrag Milanovic b3b71df07c musllinux fix so wheels build can work 2026-01-12 15:38:45 +01:00
Miodrag Milanović 72690062a1
Merge pull request #5599 from YosysHQ/musllinux_fix 
musllinux fix so wheels build can work
 2026-01-12 14:00:00 +01:00
Emil J f193dd0a28
Merge pull request #5594 from rocallahan/sdc-workaround 
Check for missing port in SDC code to work around compiler bug
 2026-01-12 11:22:25 +01:00
Miodrag Milanovic 2b12b74121 musllinux fix so wheels build can work 2026-01-11 15:23:38 +01:00
Robert O'Callahan 37347aacb2 Check for missing port in SDC code 
I am getting weird crashes on `main` in `tests/sdc/alu_sub.ys` which I traced to a null `Wire*`
in `SdcObjects::constrained_ports`. The null `Wire*` is being set in the `SdcObjects`
constructor. I don't understand what's going on here, so I added this check to detect the
missing wire early ... and that made the crash go away. Compiler bug maybe? I have
`Debian clang version 19.1.7 (3+build5)`, default build configuration.

Anyway this code seems fine to have.
 2026-01-10 04:00:17 +00:00
KrystalDelusion cc3d569ade
Merge pull request #5591 from YosysHQ/krys/clean_empty_switch 
Improve handling of empty switches
 2026-01-09 11:52:27 +13:00