Stefan Frederik b7b9d666a9 fix: avoid doing any erc checking/highlights if a schematic is explicitly loaded without linking components to symbols. This is done for instances with (spice|verilog)_stop=true attributes set to prevent unwanted symbol expansion		2020-12-23 18:16:53 +01:00
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binto7seg	populating xschem git repo	2020-08-08 15:47:34 +02:00
devices	svg_draw(): do not print unused layer stylesheets, error check when opening file for printing	2020-12-22 18:31:08 +01:00
examples	svg_draw(): do not print unused layer stylesheets, error check when opening file for printing	2020-12-22 18:31:08 +01:00
gschem_import	populating xschem git repo	2020-08-08 15:47:34 +02:00
logic	fix: avoid doing any erc checking/highlights if a schematic is explicitly loaded without linking components to symbols. This is done for instances with (spice|verilog)_stop=true attributes set to prevent unwanted symbol expansion	2020-12-23 18:16:53 +01:00
ngspice	remove "m=1" in xyce spice netlists as xyce does not handle m param. Translate spice_probe ".save" to xyce ".print tran", handle different hierarchical expansion of voltage/current nodes in xyce for hierarchical ammeter/spice_probe probes	2020-12-17 18:26:46 +01:00
pcb	allow ! in net names, it got deleted after the parselabel rework.	2020-12-13 20:26:39 +01:00
rom8k	remove "m=1" in xyce spice netlists as xyce does not handle m param. Translate spice_probe ".save" to xyce ".print tran", handle different hierarchical expansion of voltage/current nodes in xyce for hierarchical ammeter/spice_probe probes	2020-12-17 18:26:46 +01:00
rulz-r8c33	"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols	2020-09-30 00:30:48 +02:00
symgen	removed unused files	2020-08-24 10:01:41 +02:00
xTAG	populating xschem git repo	2020-08-08 15:47:34 +02:00
Makefile	populating xschem git repo	2020-08-08 15:47:34 +02:00