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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
420 Commits 3 Branches 10 Tags 88 MiB
C 71.5%
Tcl 15.7%
Awk 8.2%
Roff 2%
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Stefan Frederik fe42f65ec0 some adjustments to make xschem work without warnings if compiled with 18 years old tcl-tk 8.4, check for unconfigured simulators/viewers (example: running a simulation on tedax netlist), various fixes for the drill_hilight() function 2020-12-24 05:18:50 +01:00
XSchemWin windows install updates 2020-12-16 10:51:41 +01:00
doc removed obsolete --a3page command option 2020-12-20 20:42:07 +01:00
scconfig -a -m check for unbound instances (Joanne fix) 2020-12-23 15:57:28 +01:00
src some adjustments to make xschem work without warnings if compiled with 18 years old tcl-tk 8.4, check for unconfigured simulators/viewers (example: running a simulation on tedax netlist), various fixes for the drill_hilight() function 2020-12-24 05:18:50 +01:00
tests better wire connecting bubble zoom scaling at different snap levels 2020-10-07 19:45:40 +02:00
xschem_library fix: avoid doing any erc checking/highlights if a schematic is explicitly loaded without linking components to symbols. This is done for instances with (spice|verilog)_stop=true attributes set to prevent unwanted symbol expansion 2020-12-23 18:16:53 +01:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
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Changelog fix regression due to r1395, updated Changelog, fix set initial window size when doing ps/pdf export from cli 2020-12-17 03:48:34 +01:00
INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
LICENSE Update LICENSE 2020-10-10 11:44:58 +02:00
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config.h.in better comments in config.h.in 2020-10-28 00:23:26 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions