A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

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stefan schippers 2e7eb9e38b instance based schematic selection: place get_additional_symbols(1) after every load_schematic() to consistently add new virtual symbols for every instance based "schematic" attribute across the whole hierarchy. This is done for all netlisting code and hier_psprint()		2023-04-27 01:14:10 +02:00
XSchemWin	Correct menu accelerator shown for "merge" function (b key)	2023-04-11 09:33:25 +02:00
doc	update documentation (symbol generators), add missing images	2023-04-23 11:06:08 +02:00
scconfig	change preprocessor defined(HAS_CAIRO) to HAS_CAIRO==1	2023-04-09 15:36:06 +02:00
src	instance based schematic selection: place get_additional_symbols(1) after every load_schematic() to consistently add new virtual symbols for every instance based "schematic" attribute across the whole hierarchy. This is done for all netlisting code and hier_psprint()	2023-04-27 01:14:10 +02:00
tests	Doc updates (sim_pinnumber), example circuits update	2022-10-17 12:45:48 +02:00
xschem_library	allow tcl procedures to generate generator script and parameters, update vhdl and verilog netlisters to handle generator schematic/symbol references	2023-04-26 09:54:35 +02:00
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CMakeLists.txt	Added png and embedded graphs to ps and pdf export	2023-01-15 21:34:43 -07:00
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Makefile.conf.in	added libjpeg detection code, so postscript image embedding will be disabled if libjpeg not present	2023-01-18 03:33:28 +01:00
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README_MacOS.md	added notes for MacOS 'Big Sur' builds.	2021-09-26 13:24:51 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions