Doc updates (sim_pinnumber), example circuits update

doc/xschem_man/symbol_property_syntax.html

@@ -338,33 +338,35 @@ m5 net1 b net2 VSSPIN nlv w=wn l=ln geomod=0 m=1
    Defines the direction of a symbol pin. Allowed values are <kbd>in</kbd>, <kbd>out</kbd>, <kbd>inout</kbd>.
   </p>
    <img src="symbol_property_syntax2.png">
-
+  <a id="pinnumber">
   <li><kbd>pinnumber</kbd></li>
+  </a>
   <p> 
    For packaged devices (tEDAx netlists) : indicate the position of the pin on the package.
    This can be overriden at instance level by attributes <kbd>pinnumber(name)</kbd> set in the instance
    for tEDAx netlists.
    <br><br>
+  <li><kbd>sim_pinnumber</kbd></li>
    For VHDL, SPICE, Verilog netlists: define the ordering of symbol ports in netlist.
-   If all symbol pins have a pinnumber attribute this symbol will be netlisted 
-   (in all netlist formats) with pins sorted in ascending order according to pinnumber value.
-   Start value of pinnumber does not matter (may start at 1 or 0) , it is used as the sort key.
-   You can assign the pinnumber attribute directly in the symbol...
+   If all symbol pins have a sim_pinnumber attribute this symbol will be netlisted 
+   (in all netlist formats) with pins sorted in ascending order according to sim_pinnumber value.
+   Start value of sim_pinnumber does not matter (may start at 1 or 0) , it is used as the sort key.
+   You can assign the sim_pinnumber attribute directly in the symbol...
   </p>
   <img src="pinnumber1.png">
   <p>
   ... Or you can assign these in the schematic pins, if you use the "Make symbol from schematic"
   function ('a' key) these attributes will be transferred to the symbol.<br>
-  The pinnumber attributes that determine the netlist port ordering are those defined in the symbol.
+  The sim_pinnumber attributes that determine the netlist port ordering are those defined in the symbol.
   </p>
   <img src="pinnumber2.png">
   <p>
-  For sorting to happen all symbol pins must have a pinnumber attribute.
+  For sorting to happen all symbol pins must have a sim_pinnumber attribute.
   If some pins miss this attribute no sorting is done and pin ordering will be unchanged,
   the stored order of symbol pins will be used (first created pin netlisted first).<br>
-  If there are duplicate pinnumber attributes (but all pins have this attribute) sorting
-  will happen but relative ordering or pins with identical pinnumber is undefined.<br>
-  As an example you may give pinnumber=9999 on a symbol output and pinnumber=1 on all other
+  If there are duplicate sim_pinnumber attributes (but all pins have this attribute) sorting
+  will happen but relative ordering or pins with identical sim_pinnumber is undefined.<br>
+  As an example you may give sim_pinnumber=9999 on a symbol output and sim_pinnumber=1 on all other
   pins if you only require the output pin to be netlisted at the end, and don't care about
   the other pin ordering.
   </p>

tests/xschemtest.tcl

@@ -194,7 +194,7 @@ proc netlist_test {} {
     greycnt.sch             verilog    2415454714
     autozero_comp.sch       spice      1181616733
     loading.sch             vhdl       3300682141
-    mos_power_ampli.sch     spice      1004049459
+    mos_power_ampli.sch     spice      1986885043
     hierarchical_tedax.sch  tedax       998070173
     LCC_instances.sch       spice       268038818
     pcb_test1.sch           tedax      1925087189

xschem_library/logic/ram.sch

@@ -133,21 +133,21 @@ T {data0} 310 -365 0 0 0.3 0.3 {}
 T {prech} 215 -550 0 0 0.18 0.3 {}
 T {sense} 260 -550 0 0 0.18 0.3 {}
 C {opin.sym} 340 -220 0 0 {name=p10 lab=DOUT[width-1:0] verilog_type=wire
-pinnumber=8}
+sim_pinnumber=8}
 C {ipin.sym} 200 -220 0 0 {name=p8 lab=DIN[width-1:0]
-pinnumber=5}
+sim_pinnumber=5}
 C {ipin.sym} 200 -110 0 0 {name=p12 lab=CK
-pinnumber=1}
+sim_pinnumber=1}
 C {ipin.sym} 200 -140 0 0 {name=p1 lab=OEN
-pinnumber=2}
+sim_pinnumber=2}
 C {ipin.sym} 200 -260 0 0 {name=p3 lab=ADD[dim-1:0]
-pinnumber=7}
+sim_pinnumber=7}
 C {ipin.sym} 200 -190 0 0 {name=p2 lab=WEN
-pinnumber=4}
+sim_pinnumber=4}
 C {ipin.sym} 200 -170 0 0 {name=p4 lab=CEN
-pinnumber=3}
+sim_pinnumber=3}
 C {ipin.sym} 200 -240 0 0 {name=p5 lab=M[width-1:0]
-pinnumber=6}
+sim_pinnumber=6}
 C {verilog_timescale.sym} 710 -197.5 0 0 {name=s1 timestep="1ps" precision="1ps" }
 C {title.sym} 160 -30 0 0 {name=l2}
 C {use.sym} 360 -130 0 0 {------------------------------------------------

xschem_library/logic/ram.sym

@@ -24,15 +24,14 @@ L 4 -150 0 -130 0 {}
 L 4 -150 20 -130 20 {}
 L 4 -150 40 -130 40 {}
 L 4 -150 60 -130 60 {}
-B 5 -152.5 -62.5 -147.5 -57.5 {name=ADD[dim-1:0] dir=in pinnumber=7}
-B 5 -152.5 -42.5 -147.5 -37.5 {name=M[width-1:0] dir=in pinnumber=6}
-B 5 147.5 -62.5 152.5 -57.5 {name=DOUT[width-1:0] verilog_type=wire dir=out
-pinnumber=8 }
-B 5 -152.5 -22.5 -147.5 -17.5 {name=DIN[width-1:0] dir=in pinnumber=5}
-B 5 -152.5 -2.5 -147.5 2.5 {name=WEN dir=in pinnumber=4}
-B 5 -152.5 17.5 -147.5 22.5 {name=CEN dir=in pinnumber=3}
-B 5 -152.5 37.5 -147.5 42.5 {name=OEN dir=in pinnumber=2}
-B 5 -152.5 57.5 -147.5 62.5 {name=CK dir=in pinnumber=1}
+B 5 -152.5 57.5 -147.5 62.5 {name=CK dir=in sim_pinnumber=1}
+B 5 -152.5 37.5 -147.5 42.5 {name=OEN dir=in sim_pinnumber=2}
+B 5 -152.5 17.5 -147.5 22.5 {name=CEN dir=in sim_pinnumber=3}
+B 5 -152.5 -2.5 -147.5 2.5 {name=WEN dir=in sim_pinnumber=4}
+B 5 -152.5 -22.5 -147.5 -17.5 {name=DIN[width-1:0] dir=in sim_pinnumber=5}
+B 5 -152.5 -42.5 -147.5 -37.5 {name=M[width-1:0] dir=in sim_pinnumber=6}
+B 5 -152.5 -62.5 -147.5 -57.5 {name=ADD[dim-1:0] dir=in sim_pinnumber=7}
+B 5 147.5 -62.5 152.5 -57.5 {name=DOUT[width-1:0] verilog_type=wire dir=out sim_pinnumber=8 }
 T {@symname} -31.5 -6 0 0 0.3 0.3 {}
 T {@name} 135 -82 0 0 0.2 0.2 {}
 T {ADD[dim-1:0]} -125 -64 0 0 0.2 0.2 {}