instance based schematic selection: place get_additional_symbols(1) after every load_schematic() to consistently add new virtual symbols for every instance based "schematic" attribute across the whole hierarchy. This is done for all netlisting code and hier_psprint()
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@ -93,6 +93,7 @@ void hier_psprint(char **res, int what) /* netlister driver */
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/* for printing we go down to bottom regardless of spice_stop attribute */
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dbg(1, "hier_psprint(): loading file: |%s|\n", filename);
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load_schematic(1,filename, 0, 1);
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get_additional_symbols(1);
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zoom_full(0, 0, 1, 0.97);
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if(what & 1) ps_draw(2); /* page */
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if(what & 2) { /* print cellname */
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@ -577,6 +578,7 @@ int spice_block_netlist(FILE *fd, int i)
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fprintf(fd, "\n");
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spice_stop ? load_schematic(0,filename, 0, 1) : load_schematic(1,filename, 0, 1);
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get_additional_symbols(1);
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err |= spice_netlist(fd, spice_stop); /* 20111113 added spice_stop */
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if(xctx->schprop && xctx->schprop[0]) {
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@ -108,6 +108,7 @@ static int tedax_block_netlist(FILE *fd, int i)
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my_free(_ALLOC_ID_, &extra);
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fprintf(fd, "\n");
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load_schematic(1,filename, 0, 1);
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get_additional_symbols(1);
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err |= tedax_netlist(fd, tedax_stop);
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xctx->netlist_count++;
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@ -467,6 +467,7 @@ int verilog_block_netlist(FILE *fd, int i)
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my_strdup(_ALLOC_ID_, &extra2, get_tok_value(xctx->sym[i].prop_ptr, "verilog_extra", 0));
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fprintf(fd, "// sch_path: %s\n", sanitized_abs_sym_path(filename, ""));
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verilog_stop? load_schematic(0,filename, 0, 1) : load_schematic(1,filename, 0, 1);
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get_additional_symbols(1);
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/* print verilog timescale and preprocessor directives 10102004 */
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fmt_attr = xctx->format ? xctx->format : "verilog_format";
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for(j=0;j<xctx->instances; ++j)
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@ -560,6 +560,7 @@ int vhdl_block_netlist(FILE *fd, int i)
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Int_hashtable table = {NULL, 0};
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fprintf(fd, "-- sch_path: %s\n", sanitized_abs_sym_path(filename, ""));
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load_schematic(1,filename, 0, 1);
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get_additional_symbols(1);
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dbg(1, "vhdl_block_netlist(): packages\n");
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for(l=0;l<xctx->instances; ++l)
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{
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