Version bump

git-svn-id: file://localhost/svn/verilator/trunk/verilator@1053 77ca24e4-aefa-0310-84f0-b9a241c72d87
Add DESTDIR to Makefiles to assist RPM construction. [Gunter Dannoritzer]
2026-10-02 16:13:34 +02:00 · 2008-05-07 18:27:23 +00:00 · 2008-05-07 17:46:33 +00:00 · 2008-05-06 15:45:41 +00:00 · 2008-05-06 14:52:53 +00:00 · 2008-05-06 14:18:04 +00:00
253 changed files with 2676 additions and 704 deletions
@@ -3,6 +3,96 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!

+* Verilator 3.663 2008/05/07
+
+**** Add DESTDIR to Makefiles to assist RPM construction. [Gunter Dannoritzer]
+
+**** Fix compiler warnings under GCC 4.2.1.
+
+**** Fix preprocessor `else after series of `elsif.  [Mark Nodine]
+
+**** Fix parametrized defines calling define with comma.  [Joshua Wise]
+
+**** Fix comma separated list of primitives.  [by Bryan Brady]
+
+* Verilator 3.662 2008/04/25
+
+***  Add Verilog 2005 $clog2() function.
+     This is useful in calculating bus-widths from parameters.
+
+***  Support /**/ comments in -f option files. [Stefan Thiede]
+
+**** Add error message when modules have duplicate names. [Stefan Thiede]
+
+**** Support defines terminated in EOF, though against spec. [Stefan Thiede]
+
+**** Support optional argument to $finish and $stop.  [by Stefan Thiede]
+
+**** Support ranges on gate primitive instantiations. [Stefan Thiede]
+
+**** Ignore old standard(ish) Verilog-XL defines.  [by Stefan Thiede]
+
+**** Fix "always @ ((a) or (b))" syntax error. [by Niranjan Prabhu]
+
+**** Fix "output reg name=expr;" syntax error. [Martin Scharrer]
+
+**** Fix multiple .v files being read in random order. [Stefan Thiede]
+
+**** Fix internal error when params get non-constants. [Johan Wouters]
+
+**** Fix bug introduced in 3.661 with parametrized defines.
+
+* Verilator 3.661 2008/04/04
+
+***  The --enable-defenv configure option added in 3.660 is now the default.
+     This hard-codes a default for VERILATOR_ROOT etc in the executables.
+
+***  Add --language option for supporting older code. [Stefan Thiede]
+
+***  Add --top-module option to select between multiple tops. [Stefan Thiede]
+
+***  Unsized concatenates now give WIDTHCONCAT warnings. [Jonathan Kimmitt]
+     Previously they threw fatal errors, which in most cases is correct
+     according to spec, but can be incorrect in presence of parameter values.
+
+**** Support functions with "input integer".  [Johan Wouters]
+
+**** Ignore delays attached to gate UDPs.  [Stefan Thiede]
+
+**** Fix SystemVerilog parameterized defines with `` expansion,
+     and fix extra whitespace inserted on substitution.  [Vladimir Matveyenko]
+
+**** Fix no-module include files on command line.  [Stefan Thiede]
+
+**** Fix dropping of backslash quoted-quote at end of $display.
+
+**** Fix task output pin connected to non-variables. [Jonathan Kimmitt]
+
+**** Fix missing test_v in install datadir. [Holger Waechtler]
+
+**** Fix internal error after MSB < LSB error reported to user. [Stefan Thiede]
+
+* Verilator 3.660 2008/03/23
+
+***  Add support for hard-coding VERILATOR_ROOT etc in the executables,
+     to enable easier use of Verilator RPMs.  [Gunter Dannoritzer]
+
+***  Allow multiple .v files on command line.  [Stefan Thiede]
+
+***  Convert re-defining macro error to warning.  [Stefan Thiede]
+
+***  Add --error-limit option.  [Stefan Thiede]
+
+***  Allow __ in cell names by quoting them in C.  [Stefan Thiede]
+
+**** Fix genvar to be signed, so "< 0" works properly.  [Niranjan Prabhu]
+
+**** Fix assignments to inputs inside functions/tasks.  [Patricio Kaplan]
+
+**** Fix definitions in main file.v, referenced in library.  [Stefan Thiede]
+
+**** Fix undefined assigns to be implicit warnings. [Stefan Thiede]
+
 * Verilator 3.658 2008/02/25

 **** Fix unistd compile error in 3.657.  [Patricio Kaplan, Jonathan Kimmitt]
@@ -6,7 +6,7 @@
 # 
 # Author: Wilson Snyder <[email protected]>
 # 
-# Code available from: http://www.veripool.com/verilator
+# Code available from: http://www.veripool.org/verilator
 # 
 #*****************************************************************************
 # 
@@ -61,6 +61,9 @@ MAKEINFO = makeinfo
 TEXI2DVI = texi2dvi
 PERL = @PERL@

+# Destination prefix for RPMs
+DESTDIR = 
+
 #### Don't edit: You're much better using configure switches to set these
 prefix = @prefix@
 exec_prefix = @exec_prefix@
@@ -78,8 +81,12 @@ datadir = @datadir@
 infodir = @infodir@

 # Directory in which to install package specific files
+# Generally ${prefix}/share/verilator
 pkgdatadir = @pkgdatadir@

+# Directory in which to install data across multiple architectures
+datarootdir = @datarootdir@
+
 #### End of system configuration section. ####
 ######################################################################

@@ -140,6 +147,7 @@ msg_test:
 	@echo "Type 'make test' to test."
 	@echo

+.PHONY:test
 ifeq ($(VERILATOR_AUTHOR_SITE),1)	# Local... Else don't burden users
 test: test_vcs test_c test_sc test_sp test_verilated test_regress
 else
@@ -184,9 +192,11 @@ verilator.html: bin/verilator
 verilator.pdf: bin/verilator $(DISTCONFIG)
 	pod2latex --full --out verilator.tex bin/verilator
 	cat < verilator.tex \
+	   | sed 's/\\begin{document}/\\usepackage[left=1.7in,right=1.7in,top=1.3in,bottom=1.3in]{geometry}\n\\begin{document}/' \
+	   | sed 's/\\begin{document}/\\usepackage[pdftex,bookmarks=true,bookmarksnumbered=true,hypertexnames=false,breaklinks=true,linkbordercolor={0 0 1}]{hyperref}\n\\begin{document}/' \
 	   | sed 's/\\begin{document}/\\usepackage{fancyhdr} \\pagestyle{fancy}\n\\begin{document}/' \
 	   | sed 's/\\begin{document}/\\setlength{\\parindent}{0pt} \\setlength{\\parskip}{\\baselineskip}\n\\begin{document}/' \
-	   | sed 's/\\begin{document}/\\title{$(DISTTITLE)} \\date{${DISTDATE}} \\author{Wilson Snyder\\\\ http:\/\/www.veripool.com}\n\\begin{document}/' \
+	   | sed 's/\\begin{document}/\\title{$(DISTTITLE)} \\date{${DISTDATE}} \\author{Wilson Snyder\\\\ http:\/\/www.veripool.org}\n\\begin{document}/' \
 	   | sed 's/\\begin{document}/\\lhead[$(DISTTITLE)]{$(DISTTITLE)}\n\\begin{document}/' \
 	   | sed 's/\\tableofcontents/\\begin{titlepage} \\maketitle \\end{titlepage}\n\\tableofcontents/' \
 	   > verilator2.tex
@@ -203,21 +213,32 @@ README: readme.texi
 	$(MAKEINFO) -I$(srcdir) $(srcdir)/readme.texi --output=$@ \
 	--no-headers --no-validate

-installdirs:
-	$(SHELL) ${srcdir}/mkinstalldirs $(bindir) $(infodir)
-
 # See uninstall also
-VL_INST_BIN_FILES = verilator
+VL_INST_BIN_FILES = verilator verilator_bin verilator_bin_dbg
 installbin:
-	( cd bin ; $(INSTALL_PROGRAM) verilator $(bindir)/verilator )
+	$(SHELL) ${srcdir}/mkinstalldirs $(DESTDIR)$(bindir)
+	( cd bin ; $(INSTALL_PROGRAM) verilator $(DESTDIR)$(bindir)/verilator )
+	( $(INSTALL_PROGRAM) verilator_bin $(DESTDIR)$(bindir)/verilator_bin )
+	( $(INSTALL_PROGRAM) verilator_bin_dbg $(DESTDIR)$(bindir)/verilator_bin_dbg )

 VL_INST_MAN_FILES = verilator.1
 installman:
+	$(SHELL) ${srcdir}/mkinstalldirs $(DESTDIR)$(mandir)/man1
 	for p in $(VL_INST_MAN_FILES) ; do \
-	  $(INSTALL_PROGRAM) $$p $(mandir)/man1/$$p; \
+	  $(INSTALL_PROGRAM) $$p $(DESTDIR)$(mandir)/man1/$$p; \
 	done

-install: all_nomsg installdirs installbin installman install-msg
+installdata:
+	$(SHELL) ${srcdir}/mkinstalldirs $(DESTDIR)$(pkgdatadir)/examples
+	cp -r include $(DESTDIR)$(pkgdatadir)
+	cp -r src     $(DESTDIR)$(pkgdatadir)
+	cp -r test_c  $(DESTDIR)$(pkgdatadir)/examples
+	cp -r test_sc $(DESTDIR)$(pkgdatadir)/examples
+	cp -r test_sp $(DESTDIR)$(pkgdatadir)/examples
+	cp -r test_v  $(DESTDIR)$(pkgdatadir)/examples
+
+VL_INST_DATA_FILES = verilator.1
+install: all_nomsg installbin installman installdata install-msg

 install-here: installman ftp

@@ -246,9 +267,6 @@ install-project-quick:
 endif

 ftp: info
-	echo "http://www.veripool.com/verilator3.html"
-	cp verilator.html verilator_man.html
-	ftp_tree --password $(VERIPOOL_PW) --user $(VERIPOOL_USER) verilator_man.html webftp.veripool.com:/web

 install-msg:
 	@echo "Installed!"
@@ -261,8 +279,9 @@ install-msg:
 	@echo

 uninstall:
-	-cd $(mandir)/man1 && rm -f $(VL_INST_MAN_FILES)
-	-cd $(bindir) && rm -f $(VL_INST_BIN_FILES)
+	-cd $(DESTDIR)$(mandir)/man1 && rm -f $(VL_INST_MAN_FILES)
+	-cd $(DESTDIR)$(bindir) && rm -f $(VL_INST_BIN_FILES)
+	-rm -f $(DESTDIR)$(pkgdatadir)

 # autoheader might not change config_build.h.in, so touch a stamp file.
 IN_WILD := ${srcdir}/*.in ${srcdir}/*/*.in ${srcdir}/*/*/*.in \
@@ -287,7 +306,7 @@ configure: configure.ac
 maintainer-clean::
 	@echo "This command is intended for maintainers to use;"
 	@echo "rebuilding the deleted files requires makeinfo."
-	rm -f *.info* $(INFOS) faq.html verilator.html configure bin/*
+	rm -f *.info* $(INFOS) faq.html verilator.html configure

 clean mostlyclean distclean maintainer-clean maintainer-copy::
 	for dir in $(SUBDIRS); do \
@@ -320,7 +339,7 @@ DISTCONFIG = src/config_build.h.in

 DISTTITLE := $(shell sed -e '/DTVERSION/!d' -e 's/[^0-9]*\([0-9.a-z]*\).*/verilator-\1/' -e 's/v/V/' -e q $(DISTCONFIG))
 DISTNAME := $(shell sed -e '/DTVERSION/!d' -e 's/[^0-9]*\([0-9.a-z]*\).*/verilator-\1/' -e q $(DISTCONFIG))
-DISTDATEPRE := $(shell sed -e '/DTVERSION/!d' -e 's/.*\([0-3]\?[0-9].[0-3]\?[0-9].[1-2][0-9][0-9][0-9]\).*/\1/' -e q $(DISTCONFIG))
+DISTDATEPRE := $(shell sed -e '/DTVERSION/!d' -e 's/.*\([1-2][0-9][0-9][0-9].[0-9]*[0-9].[0-9]*[0-9]\).*/\1/' -e q $(DISTCONFIG))

 DISTTAGNAME := $(subst .,_,$(subst -,_,$(DISTNAME)))
 DISTDATE := $(subst /,-,$(DISTDATEPRE))
@@ -34,27 +34,7 @@ use Config;
 use Cwd qw(abs_path getcwd);

 use strict;
-use vars qw ($Debug %Vars $Opt $Opt_Make_Dir $Opt_Sp @Opt_Verilator_Sw
-	     $Opt_Trace
-	     %Modules
-	     );
-
-#######################################################################
-# Global constants -- Configuration info
-
-# Where to find real executables
-# We could find it by using $RealBin, but we require this path
-# so that when the user runs make, they will have it and not get strange error.
-$ENV{VERILATOR_ROOT} or die "%Error: verilator: VERILATOR_ROOT needs to be in environment\n";
-print "export VERILATOR_ROOT=$ENV{VERILATOR_ROOT}\n" if $Debug;
-
-# Read by verilator for populating makefile
-if (!defined $ENV{SYSTEMC_ARCH}) {
-    $ENV{SYSTEMC_ARCH} ||= (($Config{osname} =~ /solaris/i && "gccsparcOS5")
-			    || ($Config{osname} =~ /cygwin/i && "cygwin")
-			    || "linux");
-    print "export SYSTEMC_ARCH=$ENV{SYSTEMC_ARCH}\n" if $Debug;
-}
+use vars qw ($Debug @Opt_Verilator_Sw);

 #######################################################################
 #######################################################################
@@ -65,7 +45,6 @@ autoflush STDERR 1;

 $Debug = 0;
 my $opt_gdb;
-$Opt_Sp = undef;

 # No arguments can't do anything useful.  Give help
 if ($#ARGV < 0) {
@@ -84,34 +63,15 @@ if (! GetOptions (
 		  # Major operating modes
 		  "help"	=> \&usage,
 		  "debug:s"	=> \&debug,
-		  "version!"	=> \&version,
+		  # "version!"	=> \&version,	# Also passthru'ed
 		  # Switches
 		  "gdb=s"	=> \$opt_gdb,	# Undocumented debugging
-		  "trace!"	=> \$Opt_Trace,
-		  "sp!"		=> sub {$Opt_Sp = 'sp';},
-		  "sc!"		=> sub {$Opt_Sp = 'sc';},
-		  "cc!"		=> sub {$Opt_Sp = 0;},
-		  "lint-only!"	=> sub {$Opt_Sp = 0;},
-		  #"ignc!"	=> ...,		# Undocumented debugging, disable $c but don't complain
 		  # Additional parameters
 		  "<>"		=> sub {},	# Ignored
 		  )) {
    pod2usage(-exitstatus=>2, -verbose=>0);
 }

-# Check configuration
-if ($Opt_Sp) {
-    (defined $ENV{SYSTEMC}) or die "%Error: verilator: Need \$SYSTEMC in environment\nProbably System-C isn't installed, see http://www.systemc.org\n";
-}
-if ($Opt_Sp eq 'sp' || $Opt_Trace) {
-    if (!defined $ENV{SYSTEMPERL}) {
-	my $try = "$ENV{W}/hw/utils/perltools/SystemC";
-	$ENV{SYSTEMPERL} = $try if -d $try;
-    }
-    (defined $ENV{SYSTEMPERL}) or die "%Error: verilator: Need \$SYSTEMPERL in environment for --sp or --trace\nProbably System-Perl isn't installed, see http://www.veripool.com/systemperl.html\n";
-    (-d "$ENV{SYSTEMPERL}/src") or die "%Error: verilator: \$SYSTEMPERL environment var doesn't seem to point to System-Perl kit\n";
-}
-
 # Determine runtime flags
 my $vcmd =(($opt_gdb?"$opt_gdb ":"")
 	   .verilator_bin()
@@ -124,7 +84,6 @@ run ($vcmd);
 #----------------------------------------------------------------------

 sub usage {
-    bin_version();
    print '$Revision$$Date$ ', "\n";
    pod2usage(-exitstatus=>2, -verbose=>2);
 }
@@ -135,23 +94,16 @@ sub debug {
    $Debug = $level||3;
 }

-sub version {
-    bin_version();
-    exit (0);
-}
-
-sub bin_version {
-    ($ENV{VERILATOR_ROOT}) or print "%Warning: Unknown rev: VERILATOR_ROOT undefined\n";
-    run (verilator_bin()." --version");
-}
-
 #######################################################################
 #######################################################################
 # Builds

 sub verilator_bin {
-    my $bin = "$ENV{VERILATOR_ROOT}/".($ENV{VERILATOR_BIN}||"verilator_bin");
-    if ($Debug && -x "${bin}_dbg") { $bin = "${bin}_dbg"; }
+    my $bin = "";
+    # Use VERILATOR_ROOT if defined, else assume verilator_bin is in the search path
+    $bin .= $ENV{VERILATOR_ROOT}."/" if defined($ENV{VERILATOR_ROOT});
+    $bin .= ($ENV{VERILATOR_BIN}||"verilator_bin");
+    if ($Debug) { $bin = "${bin}_dbg"; }
    return $bin;
 }

@@ -166,8 +118,11 @@ sub run {
    system($command);
    my $status = $?;
    if ($status) {
+	if ($! =~ /no such file or directory/i) {
+	    warn "%Error: verilator: Misinstalled, or VERILATOR_ROOT might need to be in environment\n";
+	}
 	if ($Debug) {  # For easy rerunning
-	    warn "%Error: export VERILATOR_ROOT=$ENV{VERILATOR_ROOT}\n";
+	    warn "%Error: export VERILATOR_ROOT=".($ENV{VERILATOR_ROOT}||"")."\n";
 	    warn "%Error: $command\n";
 	}
 	die "%Error: Command Failed $command\n";
@@ -206,7 +161,7 @@ code, lints it, and optionally adds coverage and waveform tracing code.
 For C++ and SystemC formats, it outputs .cpp and .h files.  For SystemPerl
 format, it outputs .sp files for the SystemPerl preprocessor, which greatly
 simplifies writing SystemC code and is available at
-L<http://www.veripool.com>.
+L<http://www.veripool.org>.

 The files created by Verilator are then compiled with C++.  The user writes
 a little C++ wrapper file, which instantiates the top level module, and
@@ -235,12 +190,14 @@ descriptions in the next sections for more information.
    --debug-check               Enable debugging assertions
    --dump-tree                 Enable dumping .tree files
    -E                          Preprocess, but do not compile
+    --error-limit <value>	Abort after this number of errors
    --exe                       Link to create executable
    -f <file>                   Parse options from a file
    --help                      Display this help.
    -I<dir>                     Directory to search for includes
    --inhibit-sim               Create function to turn off sim
    --inline-mult <value>       Tune module inlining
+    --language <lang>           Language standard to parse
    --lint-only                 Lint, but do not make output
    --MMD                       Create .d dependency files
    --MP                        Create phony dependency targets
@@ -261,6 +218,7 @@ descriptions in the next sections for more information.
    --sc                        Create SystemC output
    --sp                        Create SystemPerl output
    --stats                     Create statistics file
+    --top-module <topname>      Name of top level input module
    --trace                     Enable waveform creation
    --trace-depth <levels>      Depth of tracing
    -U<var>                     Undefine preprocessor define
@@ -393,6 +351,11 @@ Preprocess the source code, but do not compile, as with 'gcc -E'.  Output
 is written to standard out.  Beware of enabling debugging messages, as they
 will also go to standard out.

+=item --error-limit <value>
+
+After this number of errors or warnings are encountered, exit.  Defaults to
+50.
+
 =item --exe

 Generate a executable.  You will also need to pass additional .cpp files on
@@ -418,6 +381,14 @@ values, or a value <= 1 will inline everything, will lead to longer compile
 times, but potentially faster runtimes.  This setting is ignored for very
 small modules; they will always be inlined, if allowed.

+=item --language I<value>
+
+Select the language to be used when first processing each Verilog file.
+The language value must be "1364-1995", "1364-2001", "1364-2001",
+"1364-2005", or "1800-2005".  This should only be used for legacy code, as
+the preferable option is to edit the code to repair new keywords, or add
+appropriate `begin_keywords.
+
 =item --lint-only

 Check the files for lint violations only, do not create any other output.
@@ -490,8 +461,9 @@ the backward-compatible default of sc_bv's.

 =item --prefix I<topname>

-Specifies the name of the top level class.  Defaults to the name of the top
-level Verilog module.
+Specifies the name of the top level class and makefile.  Defaults to V
+prepended to the name of the --top-module switch, or V prepended to the
+first Verilog filename passed on the command line.

 =item --profile-cfuncs

@@ -537,6 +509,13 @@ Specifies SystemPerl output mode; see also --cc and -sc.

 Creates a dump file with statistics on the design in {prefix}__stats.txt.

+=item --top-module I<topname>
+
+When the input Verilog contains more than one top level module, specifies
+the name of the top level Verilog module to become the top, and sets the
+default for if --prefix is not used.  This is not needed with standard
+designs with only one top.
+
 =item --trace

 Adds waveform tracing code to the model, this will create additional
@@ -872,14 +851,16 @@ After running Make, the C++ compiler should produce the following:

 Required for SystemC output mode.  If set, specifies the directory
 containing the SystemC distribution.  This is used to find the SystemC
-include files.
+include files.  If not specified, it will come from a default optionally
+specified at configure time (before Verilator was compiled).

 =item SYSTEMC_ARCH

 Specifies the architecture name used by the SystemC kit.  This is the part
 after the dash in the lib-{...} directory name created by a 'make' in the
 SystemC distribution.  If not set, Verilator will try to intuit the proper
-setting.
+setting, or use the default optionally specified at configure time (before
+Verilator was compiled).  .

 =item SYSTEMC_CXX_FLAGS

@@ -889,7 +870,9 @@ building the SystemC model.
 =item SYSTEMPERL

 Specifies the directory containing the Verilog-Perl distribution kit.  This
-is used to find the Verilog-Perl library and include files.
+is used to find the Verilog-Perl library and include files.  If not
+specified, it will come from a default optionally specified at configure
+time (before Verilator was compiled).

 =item VCS_HOME

@@ -905,7 +888,9 @@ for debugging and selecting between multiple operating system builds.
 =item VERILATOR_ROOT

 Specifies the directory containing the distribution kit.  This is used to
-find the executable, Perl library, and include files.
+find the executable, Perl library, and include files.  If not specified, it
+will come from a default optionally specified at configure time (before
+Verilator was compiled).

 =back

@@ -1018,6 +1003,8 @@ declarations inside port lists.
 Verilator supports the `begin_keywords and `end_keywords compiler
 directives.

+Verilator supports $clog2.
+
 Verilator partially supports the uwire keyword.

 =head1 SYSTEMVERILOG (IEEE 1800-2005) SUPPORT
@@ -1561,6 +1548,10 @@ argument (as with C's printf), you cannot simply list variables standalone.
 The sized display functions are rarely used and so not supported.  Replace
 them with a $write with the appropriate format specifier.

+=item $finish, $stop
+
+The rarely used optional parameter to $finish and $stop is ignored.
+
 =item $fopen, $fclose, $fdisplay, $fwrite

 File descriptors passed to the file PLI calls must be file descriptors, not
@@ -1700,7 +1691,7 @@ output from a sub-module.)  While legal in Verilog, implicit declarations
 only work for single bit wide signals (not buses), do not allow using a
 signal before it is implicitly declared by a cell, and can lead to dangling
 nets.  A better option is the /*AUTOWIRE*/ feature of Verilog-Mode for
-Emacs, available from L<http://www.veripool.com/>
+Emacs, available from L<http://www.veripool.org/>

 Ignoring this warning will only suppress the lint check, it will simulate
 correctly.
@@ -1734,6 +1725,23 @@ not really needed.  The best solution is to insure that each module is in a
 unique file by the same name.  Otherwise, make sure all library files are
 read in as libraries with -v, instead of automatically with -y.

+=item REDEFMACRO
+
+Warns that you have redefined the same macro with a different value, for
+example:
+
+    `define MACRO def1
+    //...
+    `define MACRO otherdef
+
+The best solution is to use a different name for the second macro.  If this
+is not possible, add a undef to indicate the code is overriding the value:
+
+    `define MACRO def1
+    //...
+    `undef MACRO
+    `define MACRO otherdef
+
 =item STMTDLY

 Warns that you have a statement with a delayed time in front of it, for
@@ -1891,6 +1899,24 @@ The best fix, which clarifies intent and will also make all tools happy is:
 Ignoring this warning will only suppress the lint check, it will simulate
 correctly.

+=item WIDTHCONCAT
+
+Warns that based on width rules of Verilog, a concatenate or replication
+has a undeterminate width.  In most cases this violates the Verilog rule
+that widths inside concatenates and replicates must be sized, and should be
+fixed in the code.
+
+    wire [63:0] concat = {1,2};
+
+An example where this is technically legal (though still bad form) is:
+
+    parameter PAR = 1;
+    wire [63:0] concat = {PAR,PAR};
+
+The correct fix is to either size the 1 ("32'h1"), or add the width to the
+parameter definition ("parameter [31:0]"), or add the width to the
+parameter usage ("{PAR[31:0],PAR[31:0]}".
+
 =back

 The following describes the less obvious errors:
@@ -1944,11 +1970,14 @@ Visual C++ Version 7 or newer, but this is not tested by the author.

 =item Can you provide binaries?

-At this time I'd prefer to get patches out quickly than have to generate
-myriad binaries for many different OS flavors.  People have generally
-requested binaries when they are having problems with their C++
-compiler. Alas, binaries won't help this, as in the end a fully working C++
-compiler is required to compile the output of Verilator.
+Verilator is available as a RPM for SuSE and perhaps other systems; this is
+done by porters and may slightly lag the primary distribution.  If there
+isn't a binary build for your distribution, how about you set one up?
+Please contact the authors for assistance.
+
+Note people sometimes request binaries when they are having problems with
+their C++ compiler. Alas, binaries won't help this, as in the end a fully
+working C++ compiler is required to compile the output of Verilator.

 =item How can it be faster than (name-the-simulator)?

@@ -2031,15 +2060,24 @@ the "verilator" define for you, so just wrap the code in a ifndef region:

 =item Why do I get "unexpected `do'" or "unexpected `bit'" errors?

-Do, bit, ref, and other words are now SystemVerilog keywords.  You should
-change your code to not use them to insure it works with newer tools.
-Alternatively, surround them by the Verilog 2005/SystemVerilog
+Do, bit, ref, return, and other words are now SystemVerilog keywords.  You
+should change your code to not use them to insure it works with newer
+tools.  Alternatively, surround them by the Verilog 2005/SystemVerilog
 begin_keywords pragma to indicate Verilog 2001 code.

   `begin_keywords "1364-2001"
      integer bit; initial bit = 1;
   `end_keywords

+If you want the whole file to be parsed as Verilog 2001, just create a
+file with
+
+   `begin_keywords "1364-2001"
+
+and add it before other Verilog files on the command line.  (Note this will
+also change the default for --prefix, so if you're not using --prefix, you
+will now need to.)
+
 =item How do I prevent my assertions from firing during reset?

 Call Verilated::assertOn(false) before you first call the model, then turn
@@ -2079,7 +2117,7 @@ use GCC 2.95, or GCC 3.4 you'll have faster builds.  Two ways to cheat are
 to compile on parallel machines and avoid compilations altogether.  See the
 --output-split option, and the web for the ccache, distcc and icecream
 packages, and the Make::Cache package available from
-L<http://www.veripool.com/>. Make::Cache will skip GCC runs between
+L<http://www.veripool.org/>. Make::Cache will skip GCC runs between
 identical source builds, even across different users.

 =item Why do so many files need to recompile when I add a signal?
@@ -2217,7 +2255,7 @@ Eugene Weber, Leon Wildman, and Mat Zeno.

 =head1 DISTRIBUTION

-The latest version is available from L<http://www.veripool.com/>.
+The latest version is available from L<http://www.veripool.org/>.

 Copyright 2003-2008 by Wilson Snyder.  Verilator is free software; you can
 redistribute it and/or modify it under the terms of either the GNU Lesser
@@ -178,7 +178,7 @@ Displays this message and program version and exits.

 =head1 DISTRIBUTION

-The latest version is available from L<http://www.veripool.com/>.
+The latest version is available from L<http://www.veripool.org/verilator>.

 Copyright 2005-2008 by Wilson Snyder.  This package is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
@@ -189,7 +189,7 @@ Displays this message and program version and exits.

 =head1 DISTRIBUTION

-The latest version is available from L<http://www.veripool.com/>.
+The latest version is available from L<http://www.veripool.org/>.

 Copyright 2007-2008 by Wilson Snyder.  This package is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
@@ -9,6 +9,11 @@ AC_INIT(src/Verilator.cpp)
 AC_CONFIG_HEADER(src/config_build.h)

 dnl Special Substitutions
+AC_ARG_ENABLE(defenv,
+   [AS_HELP_STRING([--disable-defenv], [disable hardcoded default environment variables])],
+   CFG_WITH_DEFENV=$enableval,
+   CFG_WITH_DEFENV=yes)
+AC_SUBST(CFG_WITH_DEFENV)

 dnl Checks for programs.
 CXX=g++
@@ -18,7 +18,7 @@
 ///	This file must be compiled and linked against all objects
 ///	created from Verilator.
 ///
-/// Code available from: http://www.veripool.com/verilator
+/// Code available from: http://www.veripool.org/verilator
 ///
 //=========================================================================

@@ -19,7 +19,7 @@
 ///	all C++ files it generates.  It contains standard macros and
 ///	classes required by the Verilated code.
 ///
-/// Code available from: http://www.veripool.com/verilator
+/// Code available from: http://www.veripool.org/verilator
 ///
 //*************************************************************************

@@ -460,43 +460,92 @@ static inline IData VL_REDOR_W(int words, WDataInP lwp) {
 }

 // EMIT_RULE: VL_REDXOR:  oclean=dirty; obits=1;
-static inline IData VL_REDXOR_W(int words, WDataInP lwp) {
-    IData r = lwp[0];
-    for (int i=1; i < words; i++) r ^= lwp[i];
-    r=(r^(r>>1));
-    r=(r^(r>>2));
-    r=(r^(r>>4));
-    r=(r^(r>>8));
-    r=(r^(r>>16));
-    return r;
-}
 static inline IData VL_REDXOR_2(IData r) {
+    // Experiments show VL_REDXOR_2 is faster than __builtin_parityl
    r=(r^(r>>1));
    return r;
 }
 static inline IData VL_REDXOR_4(IData r) {
+#if defined(__GNUC__) && (__GNUC__ >= 4) && !defined(VL_NO_BUILTINS)
+    return __builtin_parityl(r);
+#else
    r=(r^(r>>1)); r=(r^(r>>2));
    return r;
+#endif
 }
 static inline IData VL_REDXOR_8(IData r) {
+#if defined(__GNUC__) && (__GNUC__ >= 4) && !defined(VL_NO_BUILTINS)
+    return __builtin_parityl(r);
+#else
    r=(r^(r>>1)); r=(r^(r>>2)); r=(r^(r>>4));
    return r;
+#endif
 }
 static inline IData VL_REDXOR_16(IData r) {
+#if defined(__GNUC__) && (__GNUC__ >= 4) && !defined(VL_NO_BUILTINS)
+    return __builtin_parityl(r);
+#else
    r=(r^(r>>1)); r=(r^(r>>2)); r=(r^(r>>4)); r=(r^(r>>8));
    return r;
+#endif
 }
 static inline IData VL_REDXOR_32(IData r) {
+#if defined(__GNUC__) && (__GNUC__ >= 4) && !defined(VL_NO_BUILTINS)
+    return __builtin_parityl(r);
+#else
    r=(r^(r>>1)); r=(r^(r>>2)); r=(r^(r>>4)); r=(r^(r>>8)); r=(r^(r>>16));
    return r;
+#endif
 }
 static inline IData VL_REDXOR_64(QData r) {
+#if defined(__GNUC__) && (__GNUC__ >= 4) && !defined(VL_NO_BUILTINS)
+    return __builtin_parityll(r);
+#else
    r=(r^(r>>1)); r=(r^(r>>2)); r=(r^(r>>4)); r=(r^(r>>8)); r=(r^(r>>16)); r=(r^(r>>32));
    return r;
+#endif
+}
+static inline IData VL_REDXOR_W(int words, WDataInP lwp) {
+    IData r = lwp[0];
+    for (int i=1; i < words; i++) r ^= lwp[i];
+    return VL_REDXOR_32(r);
+}
+
+static inline IData VL_CLOG2_I(IData lhs) {
+    // Perhaps can do better using fls GCC4 builtins
+    int n=1;
+    IData chk;
+    if (!lhs) return 0;
+    chk = lhs >> VL_UL(16); if (chk) { n += 16; lhs = chk; }
+    chk = lhs >> VL_UL(8);  if (chk) { n += 8; lhs = chk; }
+    chk = lhs >> VL_UL(4);  if (chk) { n += 4; lhs = chk; }
+    chk = lhs >> VL_UL(2);  if (chk) { n += 2; lhs = chk; }
+    chk = lhs >> VL_UL(1);  if (chk) { n += 1; lhs = chk; }
+    return n;
+}
+static inline IData VL_CLOG2_Q(QData lhs) {
+    // Perhaps can do better using fls GCC4 builtins
+    int n=1;
+    QData chk;
+    if (!lhs) return 0;
+    chk = lhs >> VL_ULL(32); if (chk) { n += 32; lhs = chk; }
+    chk = lhs >> VL_ULL(16); if (chk) { n += 16; lhs = chk; }
+    chk = lhs >> VL_ULL(8);  if (chk) { n += 8; lhs = chk; }
+    chk = lhs >> VL_ULL(4);  if (chk) { n += 4; lhs = chk; }
+    chk = lhs >> VL_ULL(2);  if (chk) { n += 2; lhs = chk; }
+    chk = lhs >> VL_ULL(1);  if (chk) { n += 1; lhs = chk; }
+    return n;
+}
+static inline IData VL_CLOG2_W(int words, WDataInP lwp) {
+    for (int i=words-1; i>=0; i--) {
+	if (lwp[i]) return VL_CLOG2_I(lwp[i])+i*VL_WORDSIZE;
+    }
+    return 0;
 }

 // EMIT_RULE: VL_COUNTONES_II:  oclean = false; lhs clean
 static inline IData VL_COUNTONES_I(IData lhs) {
+    // This is faster than __builtin_popcountl
    IData r = lhs - ((lhs >> 1) & 033333333333) - ((lhs >> 2) & 011111111111);
    r = (r + (r>>3)) & 030707070707;
    r = (r + (r>>6));
@@ -1,7 +1,7 @@
 // $Id$ -*- C++ -*-
 //*************************************************************************
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 //*************************************************************************
 //
@@ -21,7 +21,7 @@
 ///	config_build.h.in, code needed by Verilated code only goes into
 ///	verilated.h, and code needed by both goes here (verilatedos.h).
 ///
-/// Code available from: http://www.veripool.com/verilator
+/// Code available from: http://www.veripool.org/verilator
 ///
 //*************************************************************************

@@ -45,7 +45,7 @@ Verilator is invoked with parameters similar to GCC or Synopsys's VCS.  It
 reads the specified Verilog code, lints it, and optionally adds coverage
 code.  For C++ format, it outputs .cpp and .h files.  For SystemC format,
 it outputs .sp files for the SystemPerl preprocessor available at
-http://veripool.com.
+http://www.veripool.org.

 The resulting files are then compiled with C++.  The user writes a little
 C++ wrapper file, which instantiates the top level module.  This is
@@ -57,7 +57,7 @@ The resulting executable will perform the actual simulation.
@section Obtaining Distribution

 The latest version is available at 
-@uref{http://veripool.com/verilator.htm}
+@uref{http://www.veripool.org/verilator}

 Download the latest package from that site, and decompress.
@samp{gunzip verilator_version.tar.gz ; tar xvf verilator_version.tar}
@@ -126,6 +126,12 @@ do a @code{make sc_patch}.
@item
 Type @samp{./configure} to configure Verilator for your system.

+If you are configuring Verilator to be part of a RPM or other
+distribution package system, you may want to use the --enable-defenv
+configure flag.  This will take the current value of VERILATOR_ROOT,
+SYSTEMC, SYSTEMC_ARCH, and SYSTEMPERL and build them as defaults into
+the executable.
+
@item
 Type @samp{make} to compile Verilator.

@@ -3,7 +3,7 @@
 #
 # DESCRIPTION: Verilator: Makefile for verilog source
 #
-# Code available from: http://www.veripool.com/verilator
+# Code available from: http://www.veripool.org/verilator
 #
 #*****************************************************************************
 #
@@ -3,7 +3,7 @@
 #
 # DESCRIPTION: Verilator: Makefile for verilog source
 #
-# Code available from: http://www.veripool.com/verilator
+# Code available from: http://www.veripool.org/verilator
 #
 #*****************************************************************************
 #
@@ -30,6 +30,17 @@ LINK = @CXX@

 LDFLAGS += @LDFLAGS@

+CFG_WITH_DEFENV = @CFG_WITH_DEFENV@
+
+prefix = @prefix@
+
+# Directory in which to install data across multiple architectures
+datarootdir = @datarootdir@
+
+# Directory in which to install package specific files
+# Generally ${prefix}/share/verilator
+pkgdatadir = @pkgdatadir@
+
 #### End of system configuration section. ####

 VPATH += . $(srcdir)
@@ -70,6 +81,19 @@ CPPFLAGS += -W -Wall -Wno-unused-parameter -Wno-char-subscripts -Werror
 #CPPFLAGS += -pedantic-errors
 endif

+# Allow RPM builds to specify hardcoded data directories
+# To do this:
+ifeq ($(CFG_WITH_DEFENV),yes)
+ CPPFLAGS += -DDEFENV_SYSTEMC=\"$(SYSTEMC)\"
+ CPPFLAGS += -DDEFENV_SYSTEMC_ARCH=\"$(SYSTEMC_ARCH)\"
+ CPPFLAGS += -DDEFENV_SYSTEMPERL=\"$(SYSTEMPERL)\"
+ ifeq ($(VERILATOR_ROOT),)	# Use what we're given, or intuit
+  CPPFLAGS += -DDEFENV_VERILATOR_ROOT=\"$(pkgdatadir)\"
+ else
+  CPPFLAGS += -DDEFENV_VERILATOR_ROOT=\"$(VERILATOR_ROOT)\"
+ endif
+endif
+
 HEADERS = $(wildcard V*.h v*.h)

 ASTGEN = $(srcdir)/astgen
@@ -221,14 +245,19 @@ V3PreProc.o:	V3PreProc.cpp V3PreLex.yy.cpp
 #### Generated files

 # Target rule called before parallel build to make generated files
-serial:: V3Ast__gen_classes.h
+serial:: V3Ast__gen_classes.h y.tab.c

 V3Ast__gen_classes.h : $(ASTGEN) V3Ast.h V3AstNodes.h
 	$(PERL) $(ASTGEN) -I$(srcdir)  --classes

-y.tab.c y.tab.h:	verilog.y $(HEADERS)
+y.tab.h: y.tab.c
+
+# Have only one output file in this rule to prevent parallel make issues
+y.tab.c: verilog.y $(HEADERS)
 	@echo "If you get errors from verilog.y below, try upgrading bison to version 1.875 or newer."
 	${YACC} ${YFLAGS} $<
+	mv y.tab.c y_pregen.tab.c && $(PERL) $(srcdir)/bisonfix < y_pregen.tab.c > y.tab.c
+	mv y.tab.h y_pregen.tab.h && $(PERL) $(srcdir)/bisonfix < y_pregen.tab.h > y.tab.h

 V3Lexer_pregen.yy.cpp:	verilog.l y.tab.h $(HEADERS)
 	${LEX} ${LFLAGS} -o$@ $<
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Break always into sensitivity active domains
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Break always into sensitivity block domains
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Break always into sensitivity active domains
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Break always into sensitivity block domains
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Collect and print statistics
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Assertion expansion
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Collect and print statistics
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Assertion pre-expansion
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Ast node structures
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -83,6 +83,20 @@ void AstNode::init() {
    m_user5Cnt = 0;
 }

+string AstNode::encodeName(const string& namein) {
+    string name2 = namein;
+    string out;
+    for (string::iterator pos = name2.begin(); pos != name2.end(); pos++) {
+	if (pos[0]=='_' && pos[1]=='_') {
+	    out += "__ULUL_";
+	    pos++;
+	} else {
+	    out += pos[0];
+	}
+    }
+    return out;
+}
+
 string AstNode::shortName() const {
    string pretty = name();
    string::size_type pos;
@@ -114,6 +128,9 @@ string AstNode::prettyName(const string& namein) {
    while ((pos=pretty.find("__PVT__")) != string::npos) {
 	pretty.replace(pos, 7, "");
    }
+    while ((pos=pretty.find("__ULUL_")) != string::npos) {
+	pretty.replace(pos, 7, "");
+    }
    return AstNode::dedotName(pretty);
 }

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Ast node structure
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -558,6 +558,7 @@ public:
    string 	shortName() const;	// Name with __PVT__ removed for concatenating scopes
    static string dedotName(const string& namein);	// Name with dots removed
    static string prettyName(const string& namein);	// Name for printing out to the user
+    static string encodeName(const string& namein);	// Encode user name into internal C representation
    string	prettyName() const { return prettyName(name()); }
    FileLine*	fileline() const { return m_fileline; }
    int		width() const { return m_width; }
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Ast node structures
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -304,6 +304,10 @@ void AstCellInline::dump(ostream& str) {
    this->AstNode::dump(str);
    str<<" -> "<<origModName();
 }
+void AstDisplay::dump(ostream& str) {
+    this->AstNode::dump(str);
+    //str<<" "<<displayType().ascii();
+}
 void AstPin::dump(ostream& str) {
    this->AstNode::dump(str);
    if (modVarp()) { str<<" -> "; modVarp()->dump(str); }
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Ast node structure
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -1254,6 +1254,7 @@ public:
    virtual AstType type() const { return AstType::DISPLAY;}
    virtual AstNode* clone() { return new AstDisplay(*this); }
    virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
+    virtual void dump(ostream& str);
    virtual string verilogKwd() const { return (filep() ? (string)"$f"+(string)displayType().ascii()
 						: (string)"$"+(string)displayType().ascii()); }
    virtual bool isGateOptimizable() const { return false; }
@@ -1970,6 +1971,20 @@ struct AstUnsigned : public AstNodeUniop {
    virtual bool sizeMattersLhs() {return true;}  // Eliminated before matters
    virtual int instrCount()	const { return 0; }
 };
+struct AstCLog2 : public AstNodeUniop {
+    AstCLog2(FileLine* fl, AstNode* lhsp) : AstNodeUniop(fl, lhsp) {}
+    virtual ~AstCLog2() {}
+    virtual AstType type() const { return AstType::CLOG2;}
+    virtual AstNode* clone() { return new AstCLog2(*this); }
+    virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
+    virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.opCLog2(lhs); }
+    virtual string emitVerilog() { return "%k$clog2(%l)"; }
+    virtual bool emitWordForm() { return true; }
+    virtual string emitOperator() { return "VL_CLOG2"; }
+    virtual bool cleanOut() {return false;} virtual bool cleanLhs() {return true;}
+    virtual bool sizeMattersLhs() {return false;}
+    virtual int instrCount()	const { return widthInstrs()*16; }
+};
 struct AstCountOnes : public AstNodeUniop {
    // Number of bits set in vector
    AstCountOnes(FileLine* fl, AstNode* lhsp) : AstNodeUniop(fl, lhsp) {}
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Removal of named begin blocks
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Removal of named begin blocks
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Branch prediction
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Branch prediction
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Find broken links in tree
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Find broken links in tree
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Break case statements up and add Unknown assigns
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Break case statements up and add Unknown assigns
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Add C++ casts across expression size changes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Add C++ casts across expression size changes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Add temporaries, such as for changed nodes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Pre C-Emit stage changes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Add temporaries, such as for clean nodes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Pre C-Emit stage changes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Clocking POS/NEGEDGE insertion
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Clocking POS/NEGEDGE insertion
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Combine common code into functions
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Combine common code into functions
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Constant folding
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Propagate constants across AST
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Netlist (top level) functions
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Coverage modules/signals together
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Dead code elimination
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Dead branch elimination
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Add temporaries, such as for delayed nodes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Pre C-Emit stage changes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Prevent very deep expressions
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Prevent very deep expressions
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Prevent very deep expressions
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Prevent very deep expressions
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Rename scope references to module-local references
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Rename scope references to module-local references
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit C++ for tree
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -1027,10 +1027,8 @@ void EmitCStmts::visit(AstDisplay* nodep, AstNUser*) {
    emitDispState.clear();
    string fmt = "";
    string::iterator pos = vformat.begin();
-    if (*pos == '"') pos++;
    bool inPct = false;
    for (; pos != vformat.end(); ++pos) {
-	if (pos[0]=='"' && (pos+1)==vformat.end()) break;
 	if (inPct && pos[0]=='%') {
 	    emitDispState.pushFormat("%%");  // We're printf'ing it, so need to quote the %
 	    inPct = false;
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit C++ code for module tree
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit C++ for tree
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit C++ for tree
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit C++ for tree
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit Makefile
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -79,16 +79,16 @@ public:
 	    of.puts("default: "+v3Global.opt.prefix()+"__ALL.a\n");
 	}
 	of.puts("\n# Constants...\n");
-	of.puts("PERL = "+V3Options::getenvStr("PERL","perl")+"\n");
-	of.puts("VERILATOR_ROOT = "+V3Options::getenvStr("VERILATOR_ROOT","")+"\n");
-	of.puts("SYSTEMPERL = "+V3Options::getenvStr("SYSTEMPERL","")+"\n");
+	of.puts("PERL = "+V3Options::getenvPERL()+"\n");
+	of.puts("VERILATOR_ROOT = "+V3Options::getenvVERILATOR_ROOT()+"\n");
+	of.puts("SYSTEMPERL = "+V3Options::getenvSYSTEMPERL()+"\n");

 	of.puts("\n# Switches...\n");
 	of.puts(string("VM_SP = ")+(v3Global.opt.systemPerl()?"1":"0")+"\n");
 	of.puts(string("VM_SC = ")+((v3Global.opt.systemC()&&!v3Global.opt.systemPerl())?"1":"0")+"\n");
 	of.puts(string("VM_SP_OR_SC = ")+(v3Global.opt.systemC()?"1":"0")+"\n");
 	of.puts(string("VM_PCLI = ")+(v3Global.opt.systemC()?"0":"1")+"\n");
-	of.puts(string("VM_SC_TARGET_ARCH = ")+V3Options::getenvStr("SYSTEMC_ARCH","")+"\n");
+	of.puts(string("VM_SC_TARGET_ARCH = ")+V3Options::getenvSYSTEMC_ARCH()+"\n");

 	of.puts("\n# Vars...\n");
 	of.puts(string("VM_PREFIX = ")+v3Global.opt.prefix()+"\n");
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit Makefile
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit Verilog from tree
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit Verilog code for module tree
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Error handling
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -243,8 +243,8 @@ void V3Error::incWarnings() {

 void V3Error::incErrors() {
    s_errCount++;
-    if (errorCount() == MAX_ERRORS) {  // Not >= as would otherwise recurse
-	v3fatal ("Exiting due to too many errors encountered\n");
+    if (errorCount() == v3Global.opt.errorLimit()) {  // Not >= as would otherwise recurse
+	v3fatal ("Exiting due to too many errors encountered; --error-limit="<<errorCount()<<endl);
    }
 }

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Error handling
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -53,6 +53,7 @@ public:
 	IMPLICIT,	// Implicit wire
 	IMPURE,		// Impure function not being inlined
 	MULTIDRIVEN,	// Driven from multiple blocks
+	REDEFMACRO,	// Redefining existing define macro
 	UNDRIVEN,	// No drivers
 	UNOPT,		// Unoptimizable block
 	UNOPTFLAT,	// Unoptimizable block after flattening
@@ -60,6 +61,7 @@ public:
 	UNUSED,		// No receivers
 	VARHIDDEN,	// Hiding variable
 	WIDTH,		// Width mismatch
+	WIDTHCONCAT,	// Unsized numbers/parameters in concatenations
 	MAX
 	// ***Add new elements below also***
    };
@@ -78,9 +80,9 @@ public:
 	    "BLKANDNBLK",
 	    "CASEINCOMPLETE", "CASEOVERLAP", "CASEX", "CMPCONST",
 	    "COMBDLY", "STMTDLY", "GENCLK", "IMPLICIT", "IMPURE",
-	    "MULTIDRIVEN",
+	    "MULTIDRIVEN", "REDEFMACRO",
 	    "UNDRIVEN", "UNOPT", "UNOPTFLAT", "UNSIGNED", "UNUSED",
-	    "VARHIDDEN", "WIDTH",
+	    "VARHIDDEN", "WIDTH", "WIDTHCONCAT",
 	    " MAX"
 	};
 	return names[m_e];
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Add temporaries, such as for expand nodes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Expansion of wide operator macros to C operators
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: File stream wrapper that understands indentation
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: File stream wrapper that understands indentation
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Gate optimizations, such as wire elimination
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Break always into sensitivity block domains
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Generated Clock repairs
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Generated Clock Repairs
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Common headers
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Graph optimizations
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Graph optimizations
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Graph acyclic algorithm
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Graph optimizations
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Graph algorithm base class
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Graph optimizations
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -480,3 +480,97 @@ public:
 void DfaGraph::dfaReduce() {
    DfaGraphReduce (this, &V3GraphEdge::followAlwaysTrue);
 }
+
+//######################################################################
+//######################################################################
+// Algorithms - complement a DFA
+//
+// The traditional algorithm is to make a rejecting state, add edges to
+// reject from all missing values, then swap accept and reject.  Rather
+// than swap at the end, it's faster if we swap up front, then do the edge
+// changes.
+//
+// 1. Since we didn't log rejecting states, make a temp state (this will be
+// the old accept, and new reject).
+//
+// 2. All vertexes except start/accept get edges to NEW accept for any
+// non-existing case.  Weedely we don't have a nice way of representing
+// this so we just create a edge for each case and mark it "complemented."
+// 
+// 3. Delete temp vertex (old accept/new reject) and related edges.
+// The user's old accept is now the new accept.  This is imporant as
+// we want the virtual type of it to be intact.
+
+class DfaGraphComplement : GraphAlg {
+private:
+    // MEMBERS
+    DfaVertex* m_tempNewerReject;
+
+    // METHODS
+    int debug() { return 9; }
+    DfaGraph* graphp() { return static_cast<DfaGraph*>(m_graphp); }
+
+    void add_complement_edges() {
+	// Find accepting vertex
+	DfaVertex* acceptp = NULL;
+ 	for (V3GraphVertex* vertexp = m_graphp->verticesBeginp(); vertexp; vertexp=vertexp->verticesNextp()) {
+	    if (DfaVertex* vvertexp = dynamic_cast<DfaVertex*>(vertexp)) {
+		if (vvertexp->accepting()) {
+		    acceptp = vvertexp;
+		    break;
+		}
+	    }
+	}
+ 	if (!acceptp) v3fatalSrc("No accepting vertex in DFA\n");
+
+	// Remap edges
+	for (V3GraphVertex* vertexp = m_graphp->verticesBeginp(); vertexp; vertexp=vertexp->verticesNextp()) {
+	    if (DfaVertex* vvertexp = dynamic_cast<DfaVertex*>(vertexp)) {
+		//UINFO(9, "   on vertex "<<vvertexp->name()<<endl);
+		if (!vvertexp->accepting() && vvertexp != m_tempNewerReject) {
+		    for (V3GraphEdge* nextp, *edgep = vertexp->outBeginp(); edgep; edgep=nextp) {
+			nextp = edgep->outNextp();
+			if (!edgep->user()) { // Not processed
+			    // Old edges to accept now go to new reject
+			    DfaEdge* vedgep = static_cast<DfaEdge*>(edgep);
+			    DfaVertex* tovertexp = static_cast<DfaVertex*>(edgep->top());
+			    if (tovertexp->accepting()) {
+				new DfaEdge(graphp(), vvertexp, m_tempNewerReject, vedgep);
+				edgep->unlinkDelete(); edgep=NULL;
+			    }
+
+			    // NOT of all values goes to accept
+			    // We make a edge for each value to OR, IE
+			    // edge(complemented,a) edge(complemented,b) means !(a | b)
+			    if (!tovertexp->accepting()) {  // Note we must include edges moved above to reject
+				DfaEdge* newp = new DfaEdge (graphp(), vvertexp, acceptp, vedgep);
+				newp->complement(!newp->complement());
+				newp->user(1);
+			    }
+			}
+		    }
+		}
+	    }
+	}
+    }
+public:
+    DfaGraphComplement(V3Graph* dfagraphp, V3EdgeFuncP edgeFuncp)
+	: GraphAlg(dfagraphp, edgeFuncp) {
+	if (debug()>=6) m_graphp->dumpDotFilePrefixed("comp_in");
+
+	// Vertex::m_user begin: 1 indicates new edge, no more processing
+	m_graphp->userClearEdges();
+
+	m_tempNewerReject = new DfaVertex(graphp());
+	add_complement_edges();
+	if (debug()>=6) m_graphp->dumpDotFilePrefixed("comp_preswap");
+
+	m_tempNewerReject->unlinkDelete(graphp()); m_tempNewerReject=NULL;
+	if (debug()>=6) m_graphp->dumpDotFilePrefixed("comp_out");
+    }
+    ~DfaGraphComplement() {}
+};
+
+void DfaGraph::dfaComplement() {
+    DfaGraphComplement (this, &V3GraphEdge::followAlwaysTrue);
+}
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Graph automata base class
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -43,7 +43,9 @@ class DfaEdge;
 /// or epsilon, represented as a empty list of inputs.
 ///
 /// We're only looking for matches, so the only accepting states are
-/// at the end of the transformations.
+/// at the end of the transformations.  (If we want the complement, we
+/// call complement and the algorithm makes a REJECT state, then flips
+/// accept and reject for you.)
 ///	
 /// Common transforms:
 ///
@@ -51,8 +53,8 @@ class DfaEdge;
 ///
 ///	"L":	...->[ON_L]-->DfaVtx-->[epsilon]-->DfaVtx(ACCEPT)
 ///
-///	"LR":	...->[ON_L]-->DfaVtx-->[epsilon]-->DfaVtx()
-///		   ->[ON_R]-->DfaVtx-->[epsilon]-->DfaVtx(ACCEPT)
+///	"LR":	...->[ON_L]-->DfaVtx-->[epsilon]-->DfaVtx(ACCEPT)
+///		   ->[ON_R]-->DfaVtx-->[epsilon]-/
 ///
 ///	"L|R":	...->DfaVtx-->[epsilon]-->DfaVtx-->[ON_L]-->DfaVtx()->[epsilon]-->DfaVtx(ACCEPT)
 ///			   \->[epsilon]-->DfaVtx-->[ON_R]-->DfaVtx()->[epsilon]-/
@@ -76,6 +78,9 @@ public:

    /// Simplify a DFA automata
    void dfaReduce();
+
+    /// Complement result (must already be dfa)
+    void dfaComplement();
 };

 //=============================================================================
@@ -113,20 +118,33 @@ typedef AstNUser* DfaInput;

 class DfaEdge : public V3GraphEdge {
    DfaInput	m_input;
+    bool	m_complement;	// Invert value when doing compare
 public:
    static DfaInput EPSILON() { return NULL; }
    static DfaInput NA() { return AstNUser::fromInt(1); }	// as in not-applicable
    // CONSTRUCTORS
    DfaEdge(DfaGraph* graphp, DfaVertex* fromp, DfaVertex* top, DfaInput input)
 	: V3GraphEdge(graphp, fromp, top, 1)
-	, m_input(input) {}
+	, m_input(input), m_complement(false) {}
+    DfaEdge(DfaGraph* graphp, DfaVertex* fromp, DfaVertex* top, const DfaEdge* copyfrom)
+	: V3GraphEdge(graphp, fromp, top, copyfrom->weight())
+	, m_input(copyfrom->input()), m_complement(copyfrom->complement()) {}
    virtual ~DfaEdge() {}
    // METHODS
-    virtual string dotColor() const { return na()?"yellow":epsilon()?"green":"black"; }
-    virtual string dotLabel() const { return na()?"":epsilon()?"e":cvtToStr((void*)(input())); }
+    virtual string dotColor() const {
+	return (na() ? "yellow"
+		: epsilon() ? "green"
+		: "black"); }
+    virtual string dotLabel() const {
+	return (na() ? ""
+		: epsilon() ? "e"
+		: complement() ? ("not "+cvtToStr((void*)(input())))
+		: cvtToStr((void*)(input()))); }
    virtual string dotStyle() const { return (na()||cutable())?"dashed":""; }
    bool epsilon() const { return input()==EPSILON(); }
    bool na() const { return input()==NA(); }
+    bool complement() const { return m_complement; }
+    void complement(bool value) { m_complement=value; }
    DfaInput	input() const { return m_input; }
 };

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Graph tests
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -309,6 +309,12 @@ public:
 	gp->nfaToDfa();
 	dump();
 	gp->dfaReduce();
+	dump();
+
+	gp->dfaComplement();
+	dump();
+	gp->dfaReduce();
+	dump();
    }
 };

@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Hashed common code into functions
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Hash AST trees to find duplicates
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Add temporaries, such as for inline nodes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Inlining of modules
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Add temporaries, such as for inst nodes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Break always into sensitivity inst domains
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Language rules
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Lifelicate variable assignment elimination
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Variable life analysis
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: AssignPost Variable assignment elimination
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Lifepost variable analysis
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Resolve module/signal name references
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -381,10 +381,10 @@ private:

    virtual void visit(AstAssignW* nodep, AstNUser*) {
 	// Deal with implicit definitions
-	if (nodep->allowImplicit()) {
-	    if (AstVarRef* forrefp = nodep->lhsp()->castVarRef()) {
-		createImplicitVar(forrefp, false);
-	    }
+	// We used to nodep->allowImplicit() here, but it turns out
+	// normal "assigns" can also make implicit wires.  Yuk.
+	if (AstVarRef* forrefp = nodep->lhsp()->castVarRef()) {
+	    createImplicitVar(forrefp, false);
 	}
 	nodep->iterateChildren(*this);
    }
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Link modules/signals together
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Resolve module/signal name references
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -127,9 +127,6 @@ private:
 	// Module: Pick up modnames, so we can resolve cells later
 	m_modp = nodep;
 	UINFO(2,"Link Module: "<<nodep<<endl);
-	if (nodep->name().find("__") != string::npos) {
-	    nodep->v3error("Unsupported: Double underscores (__) in module names reserved for internal use: "<<nodep->prettyName());
-	}
 	if (nodep->inLibrary()) {
 	    if (!m_libVertexp) m_libVertexp = new LibraryVertex(&m_graph);
 	    new V3GraphEdge(&m_graph, m_libVertexp, vertex(nodep), 1, false);
@@ -213,7 +210,11 @@ private:
    void readModNames() {
 	// Look at all modules, and store pointers to all module names
 	for (AstModule* nodep = v3Global.rootp()->modulesp(); nodep; nodep=nodep->nextp()->castModule()) {
-	    if (!m_mods.findIdName(nodep->name())) {
+	    AstNode* foundp = m_mods.findIdName(nodep->name());
+	    if (foundp && foundp != nodep) {
+		nodep->v3error("Duplicate declaration of module: "<<nodep->prettyName());
+		foundp->v3error("... Location of original declaration");
+	    } else if (!foundp) {
 		m_mods.insert(nodep->name(), nodep);
 	    }
 	}
@@ -2,7 +2,7 @@
 //*************************************************************************
 // DESCRIPTION: Verilator: Link modules/signals together
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Wilson Snyder	0cbab84143	Version bump git-svn-id: file://localhost/svn/verilator/trunk/verilator@1053 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-05-07 18:27:23 +00:00
Wilson Snyder	a4e2a770f6	Add DESTDIR to Makefiles to assist RPM construction. [Gunter Dannoritzer] git-svn-id: file://localhost/svn/verilator/trunk/verilator@1052 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-05-07 17:46:33 +00:00
Wilson Snyder	36e84973ec	Fix parallel make running bison twice git-svn-id: file://localhost/svn/verilator/trunk/verilator@1051 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-05-06 15:45:41 +00:00
Wilson Snyder	f6c8888ee2	Fix comma separated list of primitives. [by Bryan Brady] git-svn-id: file://localhost/svn/verilator/trunk/verilator@1050 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-05-06 14:52:53 +00:00
Wilson Snyder	f2bf6a037b	Fix test broken with last commit. Part of last commit. git-svn-id: file://localhost/svn/verilator/trunk/verilator@1049 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-05-06 14:18:04 +00:00
Wilson Snyder	9dade8fbd9	Fix parametrized defines calling define with comma. [Joshua Wise] git-svn-id: file://localhost/svn/verilator/trunk/verilator@1048 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-05-06 01:11:21 +00:00
Wilson Snyder	d2d38edf06	Fix preprocessor `else after series of` elsif. [Mark Nodine] git-svn-id: file://localhost/svn/verilator/trunk/verilator@1047 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-05-06 00:50:47 +00:00
Wilson Snyder	e0abd238e3	Fix compiler warnings under GCC 4.2.1/ SuSE 10.3 git-svn-id: file://localhost/svn/verilator/trunk/verilator@1046 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-04-29 14:14:20 +00:00
Wilson Snyder	7edcc08886	Really enable DEFENV by default; didn't truely default it earlier git-svn-id: file://localhost/svn/verilator/trunk/verilator@1045 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-04-28 21:14:17 +00:00
Wilson Snyder	0c73b547f1	Fix bug introduced in 3.661 with parametrized defines. git-svn-id: file://localhost/svn/verilator/trunk/verilator@1042 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-04-25 14:01:50 +00:00
Wilson Snyder	73c3d4bb50	Version bump git-svn-id: file://localhost/svn/verilator/trunk/verilator@1041 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-04-25 12:17:12 +00:00
Wilson Snyder	77f063367a	Change website references to veripool.org git-svn-id: file://localhost/svn/verilator/trunk/verilator@1040 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-04-25 12:16:55 +00:00
Wilson Snyder	8e812058cb	Change website references to veripool.org git-svn-id: file://localhost/svn/verilator/trunk/verilator@1039 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-04-25 12:14:27 +00:00
Wilson Snyder	506c36beed	Fix ranges on gate primitive instantiations git-svn-id: file://localhost/svn/verilator/trunk/verilator@1038 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-04-25 11:48:18 +00:00
Wilson Snyder	0110f0193e	Allow /**/ comments in -f option files. git-svn-id: file://localhost/svn/verilator/trunk/verilator@1037 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-04-24 15:36:46 +00:00
Wilson Snyder	7b870f4b2a	Remove old unused vlint script git-svn-id: file://localhost/svn/verilator/trunk/verilator@1036 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-04-24 15:14:40 +00:00
Wilson Snyder	aa2630f837	Ignore old standard(ish) Verilog-XL defines git-svn-id: file://localhost/svn/verilator/trunk/verilator@1035 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-04-24 15:04:01 +00:00
Wilson Snyder	e137e93f94	Support optional argument to and . git-svn-id: file://localhost/svn/verilator/trunk/verilator@1034 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-04-24 14:32:39 +00:00
Wilson Snyder	215bdfccc2	Use GCC 4 compiler builtins for XORs git-svn-id: file://localhost/svn/verilator/trunk/verilator@1033 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-04-24 14:26:01 +00:00
Wilson Snyder	956a0a9c99	Add Verilog 2005 () function. git-svn-id: file://localhost/svn/verilator/trunk/verilator@1032 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-04-24 13:52:51 +00:00
Wilson Snyder	ab83717b7d	Fix internal error when params get non-constants. [Johan Wouters] git-svn-id: file://localhost/svn/verilator/trunk/verilator@1031 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-04-17 15:47:16 +00:00
Wilson Snyder	61e876e4bf	Add bookmarks to pdf, and fix date git-svn-id: file://localhost/svn/verilator/trunk/verilator@1030 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-04-16 21:52:23 +00:00
Wilson Snyder	9ca3dbc140	Allow defines terminated in EOF, though against spec. [Stefan Thiede] git-svn-id: file://localhost/svn/verilator/trunk/verilator@1029 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-04-15 19:12:25 +00:00
Wilson Snyder	a02e2e25bb	Fix "always @ ((a) or (b))" syntax error. [by Niranjan Prabhu] git-svn-id: file://localhost/svn/verilator/trunk/verilator@1028 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-04-14 21:47:39 +00:00
Wilson Snyder	a9281f2c37	Fix "output reg name=expr;" syntax error. [Martin Scharrer] git-svn-id: file://localhost/svn/verilator/trunk/verilator@1027 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-04-14 21:10:34 +00:00
Wilson Snyder	95395a8b87	Fix multiple .v files being read in random order. [Stefan Thiede] git-svn-id: file://localhost/svn/verilator/trunk/verilator@1026 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-04-09 14:17:03 +00:00
Wilson Snyder	ecdbd72fa1	Add error message when modules have duplicate names. git-svn-id: file://localhost/svn/verilator/trunk/verilator@1025 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-04-09 13:56:40 +00:00
Wilson Snyder	3a2f8224e4	Version bump git-svn-id: file://localhost/svn/verilator/trunk/verilator@1022 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-04-04 18:30:51 +00:00
Wilson Snyder	15841fe5f6	Support functions with input git-svn-id: file://localhost/svn/verilator/trunk/verilator@1021 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-04-04 18:29:33 +00:00
Wilson Snyder	7e5a7b65a0	Unsized concatenates now give WIDTHCONCAT warnings. git-svn-id: file://localhost/svn/verilator/trunk/verilator@1020 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-04-02 12:53:53 +00:00
Wilson Snyder	549bf876e4	Ignore delays attached to gate UDPs. [Stefan Thiede] git-svn-id: file://localhost/svn/verilator/trunk/verilator@1019 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-04-01 19:26:06 +00:00
Wilson Snyder	bd60cf12f8	Match Verilog-Perl: Fix parse error on min:typ:max delay pairs git-svn-id: file://localhost/svn/verilator/trunk/verilator@1018 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-03-31 21:03:56 +00:00
Wilson Snyder	61fbab1910	Fix internal error after MSB < LSB error reported to user. [Stefan Thiede] git-svn-id: file://localhost/svn/verilator/trunk/verilator@1017 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-03-31 14:09:52 +00:00
Wilson Snyder	957f495314	Fix task output pin connected to non-variables. git-svn-id: file://localhost/svn/verilator/trunk/verilator@1016 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-03-28 21:55:23 +00:00
Wilson Snyder	280eb48ba4	Add --language option for supporting older code. [Stefan Thiede] git-svn-id: file://localhost/svn/verilator/trunk/verilator@1015 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-03-28 20:41:21 +00:00
Wilson Snyder	ebe5711b40	The --enable-defenv configure option added in 3.660 is now the default. git-svn-id: file://localhost/svn/verilator/trunk/verilator@1014 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-03-28 19:42:14 +00:00
Wilson Snyder	a16477d84f	Fix SystemVerilog parameterized defines and whitespace git-svn-id: file://localhost/svn/verilator/trunk/verilator@1013 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-03-27 13:21:49 +00:00
Wilson Snyder	f6fb2362c6	Fix dropping of backslash quoted-quote at end of . git-svn-id: file://localhost/svn/verilator/trunk/verilator@1012 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-03-26 14:58:30 +00:00
Wilson Snyder	170427bba1	Fix r1010; bad prefix default git-svn-id: file://localhost/svn/verilator/trunk/verilator@1011 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-03-26 14:53:53 +00:00
Wilson Snyder	93531e520a	Add --top-module option to select between multiple tops. [Stefan Thiede] git-svn-id: file://localhost/svn/verilator/trunk/verilator@1010 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-03-25 19:57:41 +00:00
Wilson Snyder	aa2db8fdde	Fix no-module include files on command line. [Stefan Thiede] git-svn-id: file://localhost/svn/verilator/trunk/verilator@1009 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-03-25 13:42:48 +00:00
Wilson Snyder	7c3c2af90b	Version bump git-svn-id: file://localhost/svn/verilator/trunk/verilator@1006 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-03-23 13:58:27 +00:00
Wilson Snyder	6dca9b4ba4	Add graph dfa complementing; not used yet. git-svn-id: file://localhost/svn/verilator/trunk/verilator@1005 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-03-23 13:56:06 +00:00
Wilson Snyder	ede37bb9d8	Allow assigns to create implicit wires git-svn-id: file://localhost/svn/verilator/trunk/verilator@1004 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-03-20 01:40:22 +00:00
Wilson Snyder	4a1729eaab	Allow __ in cell names by quoting them in C. git-svn-id: file://localhost/svn/verilator/trunk/verilator@1003 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-03-20 01:16:33 +00:00
Wilson Snyder	b1565f5b89	Add --error-limit option git-svn-id: file://localhost/svn/verilator/trunk/verilator@1002 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-03-20 00:14:26 +00:00
Wilson Snyder	4fb8dcfd4e	Convert re-defining macro error to warning. git-svn-id: file://localhost/svn/verilator/trunk/verilator@1001 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-03-19 15:05:08 +00:00
Wilson Snyder	16d1f2b835	Allow multiple .v files on command line. [Stefan Thiede] git-svn-id: file://localhost/svn/verilator/trunk/verilator@1000 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-03-19 14:22:05 +00:00
Wilson Snyder	73594e5aa5	Fix definitions in main file.v, referenced in library. [Stefan Thiede] git-svn-id: file://localhost/svn/verilator/trunk/verilator@999 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-03-19 00:44:54 +00:00
Wilson Snyder	c0a365bd34	With --enable-defenv, support for hard-coding VERILATOR_ROOT etc in the executables git-svn-id: file://localhost/svn/verilator/trunk/verilator@998 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-03-18 20:26:37 +00:00
Wilson Snyder	45940ff820	Move most env vars from wrapper to verilator_bin, and wrap in accessor functions. The functionallity should be mostly the same as before, except allow verilator_bin to be in the search-path and VERILATOR_ROOT not set. git-svn-id: file://localhost/svn/verilator/trunk/verilator@997 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-03-18 15:21:13 +00:00
Wilson Snyder	d545ae242c	Fix assignments to inputs inside functions/tasks. [Patricio Kaplan] git-svn-id: file://localhost/svn/verilator/trunk/verilator@996 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-03-18 12:41:59 +00:00
Wilson Snyder	e862aaf2e1	Fix genvar to be signed, so "< 0" works properly. [Niranjan Prabhu] git-svn-id: file://localhost/svn/verilator/trunk/verilator@995 77ca24e4-aefa-0310-84f0-b9a241c72d87	2008-03-17 20:58:43 +00:00