Version bump

git-svn-id: file://localhost/svn/verilator/trunk/verilator@928 77ca24e4-aefa-0310-84f0-b9a241c72d87

Changes

@@ -3,6 +3,45 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilator 3.651 5/22/2007
+
+***  Added verilator_profcfunc utility.  [Gene Weber]
+
+***  Treat modules within `celldefine and `endcelldefine as if in library.
+
+***  Support functions which return integers.  [Mark Nodine]
+
+**** Warn if flex is not installed.  [Ralf Karge]
+
+**** Ignore `protect and `endprotect.
+
+**** Allow empty case/endcase blocks.
+
+* Verilator 3.650 4/20/2007
+
+**   Add --compiler msvc option.  This is now required when Verilated code
+     is to be run through MSVC++.  This also enables fixing MSVC++ error
+     C1061, blocks nested too deeply.  [Ralf Karge]
+
+**   Add --lint-only option, to lint without creating other output.
+
+***  Add /*verilator lint_save*/ and /*verilator lint_restore*/ to allow
+     friendly control over re-enabling lint messages.  [Gerald Williams]
+
+***  Support SystemVerilog .name and .* interconnect.
+
+***  Support while and do-while loops.
+
+***  Use $(LINK) instead of $(CXX) for Makefile link rules.  [Gerald Williams]
+
+***  Add USER_CPPFLAGS and USER_LDFLAGS to Makefiles.  [Gerald Williams]
+
+**** Fix compile errors under Windows MINGW compiler.  [Gerald Williams]
+
+**** Fix dotted bit reference to local memory.  [Eugene Weber]
+
+**** Fix 3.640 `verilog forcing IEEE 1364-1995 only.  [David Hewson]
+
 * Verilator 3.640 3/12/2007
 
 ***  Support Verilog 2005 `begin_keywords and `end_keywords.

TODO

@@ -26,11 +26,11 @@ Features:
 		Points should be per-scope like everything else rather then per-module
 		Expression coverage (see notes)
 	More Verilog 2001 Support
-		C-style function and task arguments.  [Wim Michiels]
 		(* *) Attributes  (just ignore -- preprocessor?)
 		Real numbers (NEVER)
 		Recursive functions (NEVER)
 		Verilog configuration files (NEVER)
+	DPI to define C/C++ calls from Verilog
 
 Long-term Features
 	Assertions

bin/verilator

@@ -191,6 +191,7 @@ Verilator - Convert Verilog code to C++/SystemC
     verilator --cc [options] [top_level.v] [opt_c_files.cpp/c/cc]
     verilator --sc [options] [top_level.v] [opt_c_files.cpp/c/cc]
     verilator --sp [options] [top_level.v] [opt_c_files.cpp/c/cc]
+    verilator --lint-only ...
 
 =head1 DESCRIPTION
 
@@ -245,6 +246,27 @@ output files.
 
 Specifies C++ without SystemC output mode; see also --sc and --sp.
 
+=item --compiler I<compiler-name>
+
+Enables tunings and work-arounds for the specified C++ compiler.
+
+=over 4
+
+=item gcc
+
+Tune for Gnu C++, although generated code should work on almost any
+compliant C++ compiler.  Currently the default.
+
+=item msvc
+
+Tune for Microsoft Visual C++.  This may reduce execution speed as it
+enables several workarounds to avoid silly hardcoded limits in MSVC++.
+This includes breaking deeply nested parenthesized expressions into
+sub-expressions to avoid error C1009, and breaking deep blocks into
+functions to avoid error C1061.
+
+=back
+
 =item --coverage
 
 Enables all forms of coverage, alias for --coverage-line, --coverage-user
@@ -325,9 +347,13 @@ change the SystemC modules instantiated.
 Tune the inlining of modules.  The default value of 2000 specifies that up
 to 2000 new operations may be added to the model by inlining, if more then
 this number of operations would result, the module is not inlined.  Larger
-values, or -1 to inline everything, will lead to longer compile times, but
-potentially faster runtimes.  This setting is ignored for very small
-modules; they will always be inlined, if allowed.
+values, or a value <= 1 will inline everything, will lead to longer compile
+times, but potentially faster runtimes.  This setting is ignored for very
+small modules; they will always be inlined, if allowed.
+
+=item --lint-only
+
+Check the files for lint violations only, do not create any other output.
 
 =item --MMD
 
@@ -551,6 +577,7 @@ We'll compile this example into C++.
       int main(int argc, char **argv, char **env) {
           Vour* top = new Vour;
           while (!Verilated::gotFinish()) { top->eval(); }
+          exit(0);	
       }
     EOF
 
@@ -604,13 +631,13 @@ This is an example similar to the above, but using SystemPerl.
 
     cat <<EOF >sc_main.cpp
       #include "Vour.h"
-      #include "systemperl.h"
       int sc_main(int argc, char **argv) {
           sc_clock clk ("clk",10, 0.5, 3, true);
           Vour* top;
-          SP_CELL (top, Vour);
-          SP_PIN  (top, clk, clk);
+          top = new Vour("top");   // SP_CELL (top, Vour);
+          top->clk(clk);           // SP_PIN  (top, clk, clk);
           while (!Verilated::gotFinish()) { sc_start(1); }
+          exit(0);	
       }
     EOF
 
@@ -685,11 +712,13 @@ fast path, mostly code that is executed every cycle.  OPT_SLOW specifies
 optimizations for slow-path files (plus tracing), which execute only
 rarely, yet take a long time to compile with optimization on.  OPT
 specifies overall optimization and affects all compiles, including those
-OPT_FAST and OPT_SLOW affect.  For best results, use OPT="-O2".  Nearly the
-same results can be had with much better compile times with OPT_FAST="-O1
--fstrict-aliasing".  Unfortunately, using the optimizer with SystemC files
-can result in compiles taking several minutes.  (The SystemC libraries have
-many little inlined functions that drive the compiler nuts.)
+OPT_FAST and OPT_SLOW affect.  For best results, use OPT="-O2", and link
+with "-static".  Nearly the same results can be had with much better
+compile times with OPT_FAST="-O1 -fstrict-aliasing".
+
+Unfortunately, using the optimizer with SystemC files can result in
+compiles taking several minutes.  (The SystemC libraries have many little
+inlined functions that drive the compiler nuts.)
 
 For best results, use GCC 3.3 or newer.  GCC 3.2 and earlier have
 optimization bugs around pointer aliasing detection, which can result in 2x
@@ -701,16 +730,19 @@ feedback driven compilation.  With GCC, using -fprofile-arcs, then
 
 You may uncover further tuning possibilities by profiling the Verilog code.
 Use Verilator's --profile-cfuncs, then GCC's -g -pg.  You can then run
-either oprofile or gprof to see where in the C++ code, and by looking at
-the mangled function name where in the Verilog code most of the time is
-being spent.
+either oprofile or gprof to see where in the C++ code the time is spent.
+Run the gprof output through verilator_profcfunc and it will tell you what
+Verilog line numbers on which most of the time is being spent.
 
 When done, please let the author know the results.  I like to keep tabs on
 how Verilator compares, and may be able to suggest additional improvements.
 
 =head1 FILES
 
-Verilator creates the following files:
+All output files are placed in the output directory name specified with the
+-Mdir option, or "obj_dir" if not specified.
+
+Verilator creates the following files in the output directory:
 
     {prefix}.mk				// Make include file for compiling
     {prefix}_classes.mk			// Make include file with class names
@@ -722,7 +754,7 @@ For -cc and -sc mode, it also creates:
     {prefix}{each_verilog_module}.cpp	// Lower level internal C++ files
     {prefix}{each_verilog_module}.h	// Lower level internal header files
 
-For -sp mode, it also creates:
+For -sp mode, instead of .cpp and .h it creates:
 
     {prefix}.sp				// Top level SystemC file
     {prefix}{each_verilog_module}.sp	// Lower level internal SC files
@@ -744,7 +776,8 @@ It also creates internal files that can be mostly ignored:
     {prefix}{misc}.dot			// Debugging graph files (--debug)
     {prefix}{misc}.tree			// Debugging files (--debug)
 
-After running Make, the compiler will produce the following:
+After running Make, the C++ compiler should produce the following:
+
     {prefix}				// Final executable (w/--exe argument)
     {prefix}__ALL.a			// Library of all Verilated objects
     {prefix}{misc}.o			// Intermediate objects
@@ -893,7 +926,7 @@ as the build system.
 
 =head1 VERILOG 2001 (IEEE 1364-2001) SUPPORT
 
-Verilator supports the more common Verilog 2001 language features.  This
+Verilator supports almost all Verilog 2001 language features.  This
 includes signed numbers, "always @*", comma separated sensitivity lists,
 generate statements, multidimensional arrays, localparam, and C-style
 declarations inside port lists.
@@ -907,15 +940,16 @@ Verilator partially supports the uwire keyword.
 
 =head1 SYSTEMVERILOG (IEEE 1800-2005) SUPPORT
 
-Verilator currently has very minimal support for SystemVerilog as they
-become more common, contact the author if a feature you need is missing.
+Verilator currently has very minimal support for SystemVerilog. As
+SystemVerilog features enter common usage they will be added.  Contact the
+author if a feature you need is missing.
 
 Verilator implements the full SystemVerilog 1800-2005 preprocessor subset,
 including function call-like preprocessor defines.
 
 Verilator supports $bits, $countones, $error, $fatal, $info, $isunknown,
-$onehot, $onehot0, $warning, always_comb, always_ff, always_latch, and
-final.
+$onehot, $onehot0, $warning, always_comb, always_ff, always_latch,
+do-while, and final.  It also supports .name and .* interconnection.
 
 Verilator partially supports assert.
 
@@ -1073,7 +1107,9 @@ around compiler specific constructs.
 
 =item `verilog
 
-Switch back to processing Verilog code, after a `systemc_... mode switch.
+Switch back to processing Verilog code after a `systemc_... mode switch.
+The Verilog code returns to the last language mode specified with
+`begin_keywords, or SystemVerilog if none were specified.
 
 =item /*verilator clock_enable*/
 
@@ -1139,6 +1175,26 @@ Disable the specified warning message for any warnings following the comment.
 
 Re-enable the specified warning message for any warnings following the comment.
 
+=item /*verilator lint_restore*/
+
+After a /*verilator lint_save*/, pop the stack containing lint message
+state.  Often this is useful at the bottom of include files.
+
+=item /*verilator lint_save*/
+
+Push the current state of what lint messages are turned on or turned off to
+a stack.  Later meta-comments may then lint_on or lint_off specific
+messages, then return to the earlier message state by using /*verilator
+lint_restore*/.  For example:
+
+    // verilator lint_save
+    // verilator lint_off SOME_WARNING
+    ...  // code needing SOME_WARNING turned off
+    // verilator lint_restore
+
+If SOME_WARNING was on before the lint_off, it will now be restored to on,
+and if it was off before the lint_off it will remain off.
+
 =item /*verilator no_inline_task*/ 
 
 Used in a function or task variable definition section to specify the
@@ -1250,6 +1306,10 @@ users to use these names, so it should not matter.
 If you are having trouble determining where a dotted path goes wrong, note
 that Verilator will print a list of known scopes to help your debugging.
 
+=head2 Floating Point
+
+Floating Point numbers are not synthesizable, and so not supported.
+
 =head2 Latches
 
 Verilator is optimized for edge sensitive (flop based) designs.  It will
@@ -1306,7 +1366,8 @@ different.)
 
 Verilator attempts to deal with generated clocks correctly, however new
 cases may turn up bugs in the scheduling algorithm.  The safest option is
-to have all clocks as primary inputs to the model.
+to have all clocks as primary inputs to the model, or wires directly
+attached to primary inputs.
 
 =head2 Ranges must be big-bit-endian
 
@@ -1373,12 +1434,21 @@ This section describes specific limitations for each language keyword.
 
 =over 4
 
-=item always always_comb always_ff always_latch and assign begin buf case
-casex casez default defparam else end endcase endfunction endgenerate
-endmodule endspecify endtask final for function generate genvar if initial
-inout input integer localparam macromodule module nand negedge nor not or
-output parameter posedge reg scalared signed supply0 supply1 task tri
-vectored wire xnor xor
+=item `__FILE__, `__LINE__, `begin_keywords, `begin_keywords, `begin_keywords,
+`begin_keywords, `begin_keywords, `define, `else, `elsif, `end_keywords,
+`endif, `error, `ifdef, `ifndef, `include, `line, `systemc_ctor,
+`systemc_dtor, `systemc_header, `systemc_imp_header,
+`systemc_implementation, `systemc_interface, `timescale, `undef, `verilog
+
+Fully supported.
+
+=item always, always_comb, always_ff, always_latch, and, assign, begin,
+buf, case, casex, casez, default, defparam, do-while, else, end, endcase,
+endfunction, endgenerate, endmodule, endspecify, endtask, final, for,
+function, generate, genvar, if, initial, inout, input, integer, localparam,
+macromodule, module, nand, negedge, nor, not, or, output, parameter,
+posedge, reg, scalared, signed, supply0, supply1, task, tri, vectored,
+while, wire, xnor, xor
 
 Generally supported.
 
@@ -1391,8 +1461,9 @@ All specify blocks and timing checks are ignored.
 Verilator does not perform warning checking on uwires, it treats the uwire
 keyword as if it were the normal wire keyword.
 
-=item $bits, $countones, $finish, $isunknown, $onehot, $onehot0, $readmemb,
-$readmemh, $signed, $stop, $time, $unsigned
+=item $bits, $countones, $error, $fatal, $finish, $info, $isunknown,
+$onehot, $onehot0, $readmemb, $readmemh, $signed, $stop, $time, $unsigned,
+$warning.
 
 Generally supported.
 
@@ -1455,9 +1526,9 @@ List of all warnings:
 
 =item BLKANDNBLK
 
-Error that a variable comes from a mix of blocked and non-blocking
-assignments.  Generally, this is caused by a register driven by both combo
-logic and a flop:
+BLKANDNBLK is an error that a variable comes from a mix of blocked and
+non-blocking assignments.  Generally, this is caused by a register driven
+by both combo logic and a flop:
 
       always @ (posedge clk)  foo[0] <= ...
       always @* foo[1] = ...
@@ -1473,6 +1544,9 @@ This is good coding practice anyways.
 It is also possible to disable this error when one of the assignments is
 inside a public task.
 
+Ignoring this warning may make Verilator simulations differ from other
+simulators.
+
 =item CASEINCOMPLETE
 
 Warns that inside a case statement there is a stimulus pattern for which
@@ -1480,6 +1554,9 @@ there is no case item specified.  This is bad style, if a case is
 impossible, it's better to have a "default: $stop;" or just "default: ;" so
 that any design assumption violations will be discovered in simulation.
 
+Ignoring this warning will only suppress the lint check, it will simulate
+correctly.
+
 =item CASEOVERLAP
 
 Warns that inside a case statement you have case values which are detected
@@ -1487,17 +1564,26 @@ to be overlapping.  This is bad style, as moving the order of case values
 will cause different behavior.  Generally the values can be respecified to
 not overlap.
 
+Ignoring this warning will only suppress the lint check, it will simulate
+correctly.
+
 =item CASEX
 
 Warns that it is simply better style to use casez, and C<?> in place of
 C<x>'s.  See
 L<http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase_rev1_1.pdf>
 
+Ignoring this warning will only suppress the lint check, it will simulate
+correctly.
+
 =item CMPCONST
 
 Warns that you are comparing a value in a way that will always be constant.
 For example "X > 1" will always be true when X is a single bit wide.
 
+Ignoring this warning will only suppress the lint check, it will simulate
+correctly.
+
 =item COMBDLY
 
 Warns that you have a delayed assignment inside of a combinatorial block.
@@ -1507,6 +1593,9 @@ Verilator, like synthesis, will convert this to a non-delayed assignment,
 which may result in logic races or other nasties.  See
 L<http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA_rev1_2.pdf>
 
+Ignoring this warning may make Verilator simulations differ from other
+simulators.
+
 =item GENCLK
 
 Warns that the specified signal is generated, but is also being used as a
@@ -1517,6 +1606,9 @@ generate ALL clocks outside in C++/SystemC and make them primary inputs to
 your Verilog model.  (However once need to you have even one, don't sweat
 additional ones.)
 
+Ignoring this warning may make Verilator simulations differ from other
+simulators.
+
 =item IMPLICIT
 
 Warns that a wire is being implicitly declared (it is a single bit wide
@@ -1526,18 +1618,27 @@ signal before it is implicitly declared by a cell, and can lead to dangling
 nets.  A better option is the /*AUTOWIRE*/ feature of Verilog-Mode for
 Emacs, available from L<http://www.veripool.com/>
 
+Ignoring this warning will only suppress the lint check, it will simulate
+correctly.
+
 =item IMPURE
 
 Warns that a task or function that has been marked with /*verilator
 no_inline_task*/ references variables that are not local to the task.
 Verilator cannot schedule these variables correctly.
 
+Ignoring this warning may make Verilator simulations differ from other
+simulators.
+
 =item MULTIDRIVEN
 
 Warns that the specified signal comes from multiple always blocks.  This is
 often unsupported by synthesis tools, and is considered bad style.  It will
 also cause longer runtimes due to reduced optimizations.
 
+Ignoring this warning will only slow simulations, it will simulate
+correctly.
+
 =item MULTITOP
 
 Error that there are multiple top level modules, that is modules not
@@ -1576,6 +1677,9 @@ cases would result in simulator mismatches.
 
 Warns that the specified signal is never sourced.
 
+Ignoring this warning will only suppress the lint check, it will simulate
+correctly.
+
 =item UNOPT
 
 Warns that due to some construct, optimization of the specified signal or
@@ -1589,6 +1693,9 @@ blocks in both submodules, even if they are unrelated always blocks.  This
 affects performance because Verilator would have to evaluate each submodule
 multiple times to stabilize the signals crossing between the modules.
 
+Ignoring this warning will only slow simulations, it will simulate
+correctly.
+
 =item UNOPTFLAT
 
 Warns that due to some construct, optimization of the specified signal is
@@ -1640,16 +1747,25 @@ The UNOPTFLAT warning may also occur where outputs from a block of logic
 are independent, but occur in the same always block.  To fix this, use the
 isolate_assignments meta comment described above.
 
+Ignoring this warning will only slow simulations, it will simulate
+correctly.
+
 =item UNSIGNED
 
 Warns that you are comparing a unsigned value in a way that implies it is
 signed, for example "X < 0" will always be true when X is unsigned.
 
+Ignoring this warning will only suppress the lint check, it will simulate
+correctly.
+
 =item UNUSED
 
 Warns that the specified signal is never sinked.  This is a future message,
 currently Verilator will not produce this warning.
 
+Ignoring this warning will only suppress the lint check, it will simulate
+correctly.
+
 =item VARHIDDEN
 
 Warns that a task, function, or begin/end block is declaring a variable by
@@ -1657,6 +1773,9 @@ the same name as a variable in the upper level module or begin/end block
 (thus hiding the upper variable from being able to be used.)  Rename the
 variable to avoid confusion when reading the code.
 
+Ignoring this warning will only suppress the lint check, it will simulate
+correctly.
+
 =item WIDTH
 
 Warns that based on width rules of Verilog, two operands have different
@@ -1675,6 +1794,9 @@ The best fix, which clarifies intent and will also make all tools happy is:
 
 	wire [5:0] plus_one = from[5:0] + 6'd1 + {5'd0,carry[0]};
 
+Ignoring this warning will only suppress the lint check, it will simulate
+correctly.
+
 =back
 
 The following describes the less obvious errors:
@@ -1956,7 +2078,7 @@ Communications, Sun Microsystems, Nauticus Networks, and SiCortex.
 
 The people who have contributed code or other major functionality are Paul
 Wasson, Duane Galbi, and Wilson Snyder.  Major testers include Jeff Dutton,
-Ralf Karge and Wim Michiels.
+Ralf Karge, David Hewson, Wim Michiels, and Gene Weber.
 
 Some of the people who have provided ideas and feedback for Verilator
 include Hans Van Antwerpen, Jens Arm, David Black, Gregg Bouchard, Chris
@@ -1983,7 +2105,7 @@ Major concepts by Paul Wasson and Duane Galbi.
 
 =head1 SEE ALSO
 
-L<systemperl>, L<vcoverage>, L<make>
+L<verilator_profcfunc>, L<systemperl>, L<vcoverage>, L<make>
 
 =cut
 

bin/verilator_difftree

@@ -35,12 +35,13 @@ my $Opt_A;
 my $Opt_B;
 autoflush STDOUT 1;
 autoflush STDERR 1;
+Getopt::Long::config ("no_auto_abbrev");
 if (! GetOptions (
 		  "help"	=> \&usage,
 		  "debug"	=> \&debug,
 		  "<>"		=> \&parameter,
 		  )) {
-    usage();
+    die "%Error: Bad usage, try 'verilator_difftree --help'\n";
 }
 
 defined $Opt_A or die "%Error: No old diff filename\n";

bin/verilator_profcfunc

@@ -0,0 +1,211 @@
+: # -*-Mode: perl;-*- use perl, wherever it is
+eval 'exec perl -wS $0 ${1+"$@"}'
+  if 0;
+# $Id$
+######################################################################
+#
+# Copyright 2007-2007 by Wilson Snyder <[email protected]>.  This
+# program is free software; you can redistribute it and/or modify it under
+# the terms of either the GNU Lesser General Public License or the Perl
+# Artistic License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+######################################################################
+
+require 5.006_001;
+use warnings;
+use Getopt::Long;
+use IO::File;
+use Pod::Usage;
+use strict;
+use vars qw ($Debug);
+
+#======================================================================
+
+
+#======================================================================
+# main
+
+$Debug = 0;
+my $Opt_File;
+autoflush STDOUT 1;
+autoflush STDERR 1;
+Getopt::Long::config ("no_auto_abbrev");
+if (! GetOptions (
+		  "help"	=> \&usage,
+		  "debug"	=> \&debug,
+		  "<>"		=> \&parameter,
+		  )) {
+    die "%Error: Bad usage, try 'verilator_profcfunc --help'\n";
+}
+
+defined $Opt_File or die "%Error: No filename given\n";
+
+profcfunc($Opt_File);
+
+#----------------------------------------------------------------------
+
+sub usage {
+    print '$Id$ ', "\n";
+    pod2usage(-verbose=>2, -exitval => 2);
+    exit (1);
+}
+
+sub debug {
+    $Debug = 1;
+}
+
+sub parameter {
+    my $param = shift;
+    if (!defined $Opt_File) {
+	$Opt_File = $param;
+    } else {	
+	die "%Error: Unknown parameter: $param\n";
+    }
+}
+
+#######################################################################
+
+sub profcfunc {
+    my $filename = shift;
+    # Remove hex numbers before diffing
+    my $fh = IO::File->new ($filename) or die "%Error: $! $filename,";
+
+    my %funcs;
+
+    while (defined (my $line=$fh->getline())) {
+	if ($line =~ /^\s*([0-9.]+)\s+[0-9.]+\s+([0-9.]+)\s+([0-9.]+)\s+.*\s+(\S+)\s*$/) {
+	    my $pct=$1; my $sec=$2; my $calls=$3; my $func=$4;
+	    $funcs{$func}{pct} += $pct;
+	    $funcs{$func}{sec} += $sec;
+	    $funcs{$func}{calls} += $calls;
+	}
+    }
+    $fh->close;
+
+    # Find modules
+    my %verilated_mods;
+    foreach my $func (keys %funcs) {
+	if ($func =~ /(.*)::_eval\(.*__Syms.*\)$/) {
+	    $verilated_mods{$1} = qr/^$1/;
+	}
+    }
+
+    # Resort by Verilog name
+    my %vfuncs;
+    my %groups;
+    foreach my $func (keys %funcs) {
+	my $vfunc = $func;
+	my $design;
+	foreach my $vde (keys %verilated_mods) {
+	    if ($func =~ /$verilated_mods{$vde}/) {
+		$design=$vde;
+		last;
+	    }
+	}
+	if ($vfunc =~ /__PROF__([a-zA-Z_0-9]+)__([0-9]+)\(/) {
+	    $vfunc     = sprintf("VBlock    %s:%d", $1, $2);
+	    $groups{"Verilog Blocks under $design"} += $funcs{$func}{pct};
+	} else {
+	    if ($design) {
+		$vfunc = sprintf("VCommon   %s", $func);
+		$groups{"Common code under $design"} += $funcs{$func}{pct};
+	    } else {
+		$vfunc = sprintf("C++       %s", $func);
+		$groups{'C++'} += $funcs{$func}{pct};
+	    }
+	}
+	$vfuncs{$vfunc} = $funcs{$func};
+    }
+
+    print("Overall summary:\n");
+    print("  % time\n");
+    foreach (sort (keys %groups)) {
+	printf("  %6.2f  In all %s\n", $groups{$_}, $_);
+    }
+    print("\n");
+
+
+    print("Verilog code profile:\n");
+    print("   These are split into three categories:\n");
+    print("      C++:     Time in non-Verilated C++ code\n");
+    print("      VBlock:  Time attributable to a block in a Verilog file and line\n");
+    print("      VCommon: Time in a Verilated module, due to all parts of the design\n");
+    print("\n");
+
+    print("  %   cumulative   self              \n");
+    print(" time   seconds   seconds    calls   type      filename and line number\n");
+
+    my $cume = 0;
+    foreach my $func (sort {$vfuncs{$b}{sec} <=> $vfuncs{$a}{sec}
+			    || $a cmp $b}
+		      (keys %vfuncs)) {
+	$cume += $vfuncs{$func}{sec};
+	printf +("%6.2f %9.2f %8.2f %8d   %s\n",
+		 $vfuncs{$func}{pct},
+		 $cume, $vfuncs{$func}{sec},
+		 $vfuncs{$func}{calls},
+		 $func);
+    }
+}
+
+#######################################################################
+__END__
+
+=pod
+
+=head1 NAME
+
+verilator_profcfunc - Read gprof report created with --profile-cfuncs
+
+=head1 SYNOPSIS
+
+  verilator --profile-cfuncs ....
+  gcc --ggdb -pg ....
+  {run executable}
+  gprof
+  verilator_profcfuncs gprof.out
+
+=head1 DESCRIPTION
+
+Verilator_profcfunc reads a profile report created by gprof.  The names of
+the functions are then transformed, assuming the user used verilator's
+--profile-cfuncs, and a report printed showing the percentage of time, etc,
+in each Verilog block.
+
+=head1 ARGUMENTS
+
+=over 4
+
+=item --help
+
+Displays this message and program version and exits.
+
+=back
+
+=head1 DISTRIBUTION
+
+The latest version is available from L<http://www.veripool.com/>.
+
+Copyright 2007-2007 by Wilson Snyder.  This package is free software; you
+can redistribute it and/or modify it under the terms of either the GNU
+Lesser General Public License or the Perl Artistic License.
+
+=head1 AUTHORS
+
+Wilson Snyder <[email protected]>
+
+=head1 SEE ALSO
+
+C<verilator>
+
+=cut
+
+######################################################################
+### Local Variables:
+### compile-command: "$V4/bin/verilator_profcfunc  $V4/test_c/obj_dir/V*_03_*.tree $V4N/test_c/obj_dir/V*_03_*.tree"
+### End:

configure.ac

@@ -16,8 +16,17 @@ AC_PROG_CC
 AC_PROG_CXX
 AC_PROG_INSTALL
 AC_PATH_PROG(PERL,perl)
-AC_PATH_PROG(YACC,bison)
+if test "x$PERL" = "x" ; then
+   AC_MSG_ERROR([Cannot find "perl" in your PATH, please install it])
+fi
 AC_PATH_PROG(LEX,flex)
+if test "x$LEX" = "x" ; then
+   AC_MSG_ERROR([Cannot find "flex" in your PATH, please install it])
+fi
+AC_PATH_PROG(YACC,bison)
+if test "x$YACC" = "x" ; then
+   AC_MSG_ERROR([Cannot find "bison" in your PATH, please install it])
+fi
 
 dnl Checks for libraries.
 

include/verilated.cpp

@@ -72,7 +72,8 @@ void vl_fatal (const char* filename, int linenum, const char* hier, const char*
 // Random reset -- Only called at init time, so don't inline.
 
 IData VL_RAND32() {
-#ifdef _MSC_VER
+#if defined(_WIN32) && !defined(__CYGWIN__)
+    // Windows doesn't have lrand48(), although Cygwin does.
     return (rand()<<16) | rand();
 #else
     return (lrand48()<<16) | lrand48();

include/verilated.h

@@ -513,10 +513,10 @@ static inline IData VL_COUNTONES_W(int words, WDataInP lwp) {
 }
 
 static inline IData VL_ONEHOT_I(IData lhs) {
-    return ((lhs & (lhs-1))==0 & lhs!=0);
+    return (((lhs & (lhs-1))==0) & (lhs!=0));
 }
 static inline IData VL_ONEHOT_Q(QData lhs) {
-    return ((lhs & (lhs-1))==0 & lhs!=0);
+    return (((lhs & (lhs-1))==0) & (lhs!=0));
 }
 static inline IData VL_ONEHOT_W(int words, WDataInP lwp) {
     IData one=0;

include/verilated.mk.in

@@ -49,7 +49,12 @@ VPATH += $(VERILATOR_ROOT)/include
 CPPFLAGS += $(OPT)
 
 CPPFLAGS += $(M32)
-LDFLAGS += $(M32)
+LDFLAGS  += $(M32)
+
+# Allow upper level user makefiles to specify flags they want.
+# These aren't ever set by Verilator, so users are free to override them.
+CPPFLAGS += $(USER_CPPFLAGS)
+LDFLAGS  += $(USER_LDFLAGS)
 
 # See the benchmarking section of bin/verilator.
 # Support class optimizations.  This includes the tracing and symbol table.

include/verilatedos.h

@@ -83,7 +83,7 @@ typedef long  			vlsint32_t;	///< 32-bit signed type
 typedef unsigned long           vluint32_t;	///< 32-bit unsigned type
 typedef long long      		vlsint64_t;	///< 64-bit signed type
 typedef unsigned long long      vluint64_t;	///< 64-bit unsigned type
-#elif defined(_WIN32)
+#elif defined(_WIN32) && !defined(__MINGW32__)
 typedef unsigned char           uint8_t;	///< 8-bit unsigned type (backward compatibility)
 typedef unsigned short int      uint16_t;	///< 16-bit unsigned type (backward compatibility)
 typedef unsigned long           uint32_t;	///< 32-bit unsigned type (backward compatibility)

nodist/bisonreader

@@ -0,0 +1,67 @@
+#!/usr/bin/perl -w
+#$Id$
+######################################################################
+#
+# Copyright 2007-2007 by Wilson Snyder.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of either the GNU General Public License or the
+# Perl Artistic License.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the Perl Artistic License
+# along with this module; see the file COPYING.  If not, see
+# www.cpan.org
+#                                                                           
+######################################################################
+
+# DESCRIPTION: Debugging of bison output
+
+use strict;
+
+my $Debug;
+
+my %declared;
+my %used;
+
+my $body = 0;
+my $rule = "";
+my $lineno = 0;
+foreach my $line (<STDIN>) {
+    $lineno++;
+    chomp $line;
+    $line =~ s!//.*$!!g;
+    $line =~ s!\s+! !g;
+    next if $line eq '';
+    if ($line =~ m!^\%\%!) {
+	$body++;
+    } elsif ($body == 1) {
+	$rule .= $line;
+	if ($line =~ m!^\s*;\s*$!) {
+	    #print "Rule: $rule\n";
+	    ($rule =~ /^([a-zA-Z0-9_]+):(.*)$/) or die "%Error: No rule name: $1\n";
+	    my $rulename = $1; my $preaction = $2;
+	    $declared{$rulename} = $lineno;
+	    $preaction =~ s/\{[^\}]*\}/ /g;
+	    #print "RULEN $rulename PA $preaction\n" if $Debug;
+	    $rule = '';
+	    foreach my $ref (split /\s+/, $preaction) {
+		next if $ref !~ /^[a-zA-Z]/;
+		next if $ref eq $rulename;
+		if (!$used{$ref} && $declared{$ref}) {
+		    print "   %Warning: $lineno: $ref used by $rulename after declaration\n";
+		}
+		$used{$ref} = $lineno;
+		print "  ref $ref\n" if $Debug;
+	    }
+	}
+    }
+}
+
+# Local Variables:
+# compile-command: "./bisonreader < verilog.y"
+# End:

nodist/invoke_ncverilog

@@ -0,0 +1,70 @@
+#!/usr/bin/perl -w
+# $Id$
+######################################################################
+#
+# Copyright 2007-2007 by Wilson Snyder <[email protected]>.  This
+# program is free software; you can redistribute it and/or modify it under
+# the terms of either the GNU Lesser General Public License or the Perl
+# Artistic License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+######################################################################
+
+require 5.006_001;
+use strict;
+
+#======================================================================
+# main
+
+delete $ENV{MODULE_VERSION};
+_setup_modules();
+module('add','cadence_verif');
+exec('ncverilog',@ARGV);
+
+#######################################################################
+# Modules package
+
+sub _setup_modules {
+    # Load the 'module' command into the environment
+    my $init = "/sicortex/$ENV{DIRPROJECT_ARCH}/lib/Modules/default/init/perl";
+    (-f $init) or die "%Error: Script not found: $init,";
+    require $init;
+}
+
+#######################################################################
+__END__
+
+=pod
+
+=head1 NAME
+
+invoke_ncverilog - Invoke tool under "modules" command
+
+=head1 SYNOPSIS
+
+  invoke_ncverilog  {ncv arguments}
+
+=head1 DESCRIPTION
+
+=head1 DISTRIBUTION
+
+Copyright 2007-2007 by Wilson Snyder.  This package is free software; you
+can redistribute it and/or modify it under the terms of either the GNU
+Lesser General Public License or the Perl Artistic License.
+
+=head1 AUTHORS
+
+Wilson Snyder <[email protected]>
+
+=head1 SEE ALSO
+
+=cut
+
+######################################################################
+### Local Variables:
+### compile-command: "./invoke_ncverilog -help"
+### End:

src/Makefile_obj.in

@@ -118,6 +118,7 @@ RAW_OBJS = \
 	V3Dead.o \
 	V3Delayed.o \
 	V3Depth.o \
+	V3DepthBlock.o \
 	V3Descope.o \
 	V3EmitC.o \
 	V3EmitCSyms.o \

src/V3Ast.h

@@ -999,7 +999,7 @@ private:
     AstNodeFTask*	m_taskp;	// [AfterLink] Pointer to task referenced
     string		m_name;		// Name of variable
     string		m_dotted;	// Dotted part of scope to task or ""
-    string		m_inlinedDots;	// Dotted hiearchy flattened out
+    string		m_inlinedDots;	// Dotted hierarchy flattened out
 public:
     AstNodeFTaskRef(FileLine* fl, AstNode* namep, AstNode* pinsp)
 	:AstNode(fl)

src/V3AstNodes.cpp

@@ -298,6 +298,7 @@ void AstCell::dump(ostream& str) {
     this->AstNode::dump(str);
     if (modp()) { str<<" -> "; modp()->dump(str); }
     else { str<<" ->UNLINKED:"<<modName(); }
+    if (pinStar()) str<<" [.*]";
 }
 void AstCellInline::dump(ostream& str) {
     this->AstNode::dump(str);
@@ -307,6 +308,7 @@ void AstPin::dump(ostream& str) {
     this->AstNode::dump(str);
     if (modVarp()) { str<<" -> "; modVarp()->dump(str); }
     else { str<<" ->UNLINKED"; }
+    if (svImplicit()) str<<" [.SV]";
 }
 void AstVarXRef::dump(ostream& str) {
     this->AstNode::dump(str);

src/V3AstNodes.h

@@ -421,7 +421,7 @@ struct AstScope : public AstNode {
 private:
     string	m_name;		// Name
     AstScope*	m_aboveScopep;	// Scope above this one in the hierarchy (NULL if top)
-    AstCell*	m_aboveCellp;	// Cell above this in the hiearchy (NULL if top)
+    AstCell*	m_aboveCellp;	// Cell above this in the hierarchy (NULL if top)
     AstModule*	m_modp;		// Module scope corresponds to
 public:
     AstScope(FileLine* fl, AstModule* modp, const string& name,
@@ -540,7 +540,7 @@ struct AstVarXRef : public AstNodeVarRef {
     // Includes pin on a cell, as part of a ASSIGN statement to connect I/Os until AstScope
 private:
     string	m_dotted;	// Scope name to connected to
-    string	m_inlinedDots;	// Dotted hiearchy flattened out
+    string	m_inlinedDots;	// Dotted hierarchy flattened out
 public:
     AstVarXRef(FileLine* fl, const string& name, const string& dotted, bool lvalue)
 	:AstNodeVarRef(fl, name, NULL, lvalue)
@@ -576,10 +576,11 @@ private:
     int		m_pinNum;	// Pin number
     string	m_name;		// Pin name, or "" for number based interconnect
     AstVar*	m_modVarp;	// Input/output this pin connects to on submodule.
+    bool	m_svImplicit;	// Pin is SystemVerilog .name'ed
 public:
     AstPin(FileLine* fl, int pinNum, const string& name, AstNode* exprp)
 	:AstNode(fl)
-	,m_name(name) {
+	,m_name(name), m_svImplicit(false) {
 	m_pinNum = pinNum;
 	m_modVarp = NULL;
 	setNOp1p(exprp); }
@@ -596,6 +597,8 @@ public:
     AstNode*	exprp()		const { return op1p()->castNode(); }	// op1 = Expression connected to pin
     AstVar*	modVarp()	const { return m_modVarp; }		// [After Link] Pointer to variable
     void  	modVarp(AstVar* varp) { m_modVarp=varp; }
+    bool	svImplicit()	const { return m_svImplicit; }
+    void        svImplicit(bool flag) { m_svImplicit=flag; }
 };
 
 struct AstModule : public AstNode {
@@ -652,12 +655,14 @@ private:
     string	m_name;		// Cell name
     string	m_origName;	// Original name before dot addition
     string	m_modName;	// Module the cell instances
+    bool	m_pinStar;	// Pin list has .*
     AstModule*	m_modp;		// [AfterLink] Pointer to module instanced
 public:
     AstCell(FileLine* fl, const string& instName, const string& modName,
 	    AstPin* pinsp, AstPin* paramsp, AstRange* rangep)
 	: AstNode(fl)
-	  , m_name(instName), m_origName(instName), m_modName(modName), m_modp(NULL) {
+	, m_name(instName), m_origName(instName), m_modName(modName)
+	, m_pinStar(false), m_modp(NULL) {
 	addNOp1p(pinsp); addNOp2p(paramsp); setNOp3p(rangep); }
     virtual ~AstCell() {}
     virtual AstType type() const { return AstType::CELL;}
@@ -674,6 +679,8 @@ public:
     void origName(const string& name) 	{ m_origName = name; }
     string modName()		const { return m_modName; }		// * = Instance name
     void modName(const string& name)	{ m_modName = name; }
+    bool pinStar()		const { return m_pinStar; }
+    void pinStar(bool flag)		{ m_pinStar = flag; }
     AstPin* pinsp()		const { return op1p()->castPin(); }	// op1 = List of cell ports
     AstPin* paramsp()		const { return op2p()->castPin(); }	// op2 = List of parameter #(##) values
     AstRange* rangep()		const { return op3p()->castRange(); }	// op3 = Range of arrayed instants (NULL=not ranged)

src/V3Case.cpp

@@ -62,9 +62,6 @@ private:
     //int debug() { return 9; }
 
     virtual void visit(AstNodeCase* nodep, AstNUser*) {
-	// We report a syntax error on empty "case (x) endcase" blocks, so never no items at all
-	if (!nodep->itemsp()) nodep->v3fatalSrc("No items (not even default) under case statement?\n");
-
 	// Detect multiple defaults
 	bool hitDefault = false;
 	for (AstCaseItem* itemp = nodep->itemsp(); itemp; itemp=itemp->nextp()->castCaseItem()) {

src/V3Depth.cpp

@@ -40,7 +40,6 @@
 #include "V3Ast.h"
 
 //######################################################################
-// Depth state, as a visitor of each AstNode
 
 class DepthVisitor : public AstNVisitor {
 private:
@@ -55,11 +54,6 @@ private:
 
     //int debug() { return 9; }
 
-    // MSVC++ has a limit of 100 parenthesis.  We have some operator
-    // defines that use 2 parens.  Thus we can't have a expression deeper
-    // then 50 operators.  We'll add some margin though.
-    enum en { MAX_EXPR_DEPTH = 40 };	// Expressions deeper then this need temp
-
     // METHODS
     void createDeepTemp(AstNode* nodep) {
 	UINFO(6,"  Deep  "<<nodep<<endl);
@@ -114,13 +108,15 @@ private:
     virtual void visit(AstNodeTermop* nodep, AstNUser*) {
     }
     virtual void visit(AstNodeMath* nodep, AstNUser*) {
-	m_depth++;
+	// We have some operator defines that use 2 parens, so += 2.
+	m_depth += 2;
 	if (m_depth>m_maxdepth) m_maxdepth=m_depth;
 	nodep->iterateChildren(*this); 
-	m_depth--;
+	m_depth -= 2;
 
-	if ((m_maxdepth-m_depth) > MAX_EXPR_DEPTH
-	    && m_stmtp
+	if (m_stmtp
+	    && (v3Global.opt.compLimitParens() >= 1)	// Else compiler doesn't need it
+	    && (m_maxdepth-m_depth) > v3Global.opt.compLimitParens()
 	    && !nodep->backp()->castNodeStmt()  // Not much point if we're about to use it
 	    ) {
 	    m_maxdepth = m_depth;
@@ -173,14 +169,10 @@ public:
     virtual ~DepthVisitor() {}
 };
 
-//----------------------------------------------------------------------
-// Top loop
-
 //######################################################################
 // Depth class functions
 
 void V3Depth::depthAll(AstNetlist* nodep) {
     UINFO(2,__FUNCTION__<<": "<<endl);
-    // We must do it in bottom-up module
     DepthVisitor visitor (nodep);
 }

src/V3DepthBlock.cpp

@@ -0,0 +1,139 @@
+// $Id$
+//*************************************************************************
+// DESCRIPTION: Verilator: Prevent very deep expressions
+//
+// Code available from: http://www.veripool.com/verilator
+//
+// AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
+//
+//*************************************************************************
+//
+// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// redistribute it and/or modify it under the terms of either the GNU
+// General Public License or the Perl Artistic License.
+//
+// Verilator is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+//*************************************************************************
+// V3DepthBlock's Transformations:
+//		
+// Each module:
+//	For each deep block, create cfunc including that block.
+//
+//*************************************************************************
+
+#include "config_build.h"
+#include "verilatedos.h"
+#include <stdio.h>
+#include <stdarg.h>
+#include <unistd.h>
+#include <algorithm>
+
+#include "V3Global.h"
+#include "V3DepthBlock.h"
+#include "V3Ast.h"
+#include "V3EmitCBase.h"
+
+//######################################################################
+
+class DepthBlockVisitor : public AstNVisitor {
+private:
+    // NODE STATE
+
+    // STATE
+    AstModule*		m_modp;		// Current module
+    AstCFunc*		m_funcp;	// Current function
+    int			m_depth;	// How deep in an expression
+    int			m_deepNum;	// How many functions made
+
+    //int debug() { return 9; }
+
+    // METHODS
+    AstCFunc* createDeepFunc(AstNode* nodep) {
+	AstNRelinker relinkHandle;
+	nodep->unlinkFrBack(&relinkHandle);
+	// Create function
+	string name = m_funcp->name()+"__deep"+cvtToStr(++m_deepNum);
+	AstCFunc* funcp = new AstCFunc(nodep->fileline(), name, NULL);
+	funcp->argTypes(EmitCBaseVisitor::symClassVar());
+	funcp->symProlog(true);
+	funcp->slow(m_funcp->slow());
+	funcp->addStmtsp(nodep);
+	m_modp->addStmtp(funcp);
+	// Call it at the point where the body was removed from
+	AstCCall* callp = new AstCCall(nodep->fileline(), funcp);
+	callp->argTypes("vlSymsp");
+	UINFO(6,"      New "<<callp<<endl);
+	//
+	relinkHandle.relink(callp);
+	return funcp;
+    }
+
+    // VISITORS
+    virtual void visit(AstModule* nodep, AstNUser*) {
+	UINFO(4," MOD   "<<nodep<<endl);
+	m_modp = nodep;
+	m_deepNum = 0;
+	nodep->iterateChildren(*this);
+    }
+    virtual void visit(AstCFunc* nodep, AstNUser*) {
+	// We recurse into this.
+	int lastDepth = m_depth;
+	AstCFunc* lastFuncp = m_funcp;
+	{
+	    m_depth = 0;
+	    m_funcp = nodep;
+	    nodep->iterateChildren(*this);
+	}
+	m_depth = lastDepth;
+	m_funcp = lastFuncp;
+    }
+    void visitStmt(AstNodeStmt* nodep) {
+	m_depth++;
+	if (m_depth > v3Global.opt.compLimitBlocks()
+	    && !nodep->castCCall()) {   // Already done
+	    UINFO(4, "DeepBlocks "<<m_depth<<" "<<nodep<<endl);
+	    AstNode* backp = nodep->backp();  // Only for debug
+	    if (debug()>=9) backp->dumpTree(cout,"-   pre : ");
+	    AstCFunc* funcp = createDeepFunc(nodep);
+	    funcp->accept(*this);
+	    if (debug()>=9) backp->dumpTree(cout,"-   post: ");
+	    if (debug()>=9) funcp->dumpTree(cout,"-   func: ");
+	} else {
+	    nodep->iterateChildren(*this);
+	}
+	m_depth--;
+    }
+    virtual void visit(AstNodeStmt* nodep, AstNUser*) {
+	visitStmt(nodep);
+    }
+
+    virtual void visit(AstNodeMath* nodep, AstNUser*) {}  // Accelerate
+    //--------------------
+    // Default: Just iterate
+    virtual void visit(AstVar* nodep, AstNUser*) {}	// Don't hit varrefs under vars
+    virtual void visit(AstNode* nodep, AstNUser*) {
+	nodep->iterateChildren(*this);
+    }
+
+public:
+    // CONSTUCTORS
+    DepthBlockVisitor(AstNode* nodep) {
+	m_modp=NULL;
+	m_depth=0;
+	//
+	nodep->accept(*this);
+    }
+    virtual ~DepthBlockVisitor() {}
+};
+
+//######################################################################
+// DepthBlock class functions
+
+void V3DepthBlock::depthBlockAll(AstNetlist* nodep) {
+    UINFO(2,__FUNCTION__<<": "<<endl);
+    DepthBlockVisitor visitor (nodep);
+}

src/V3DepthBlock.h

@@ -0,0 +1,36 @@
+// $Id$ //-*- C++ -*-
+//*************************************************************************
+// DESCRIPTION: Verilator: Prevent very deep expressions
+//
+// Code available from: http://www.veripool.com/verilator
+//
+// AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
+//
+//*************************************************************************
+//
+// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// redistribute it and/or modify it under the terms of either the GNU
+// General Public License or the Perl Artistic License.
+//
+// Verilator is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+//*************************************************************************
+
+#ifndef _V3DEPTHBLOCK_H_
+#define _V3DEPTHBLOCK_H_ 1
+#include "config_build.h"
+#include "verilatedos.h"
+#include "V3Error.h"
+#include "V3Ast.h"
+
+//============================================================================
+
+class V3DepthBlock {
+public:
+    static void depthBlockAll(AstNetlist* nodep);
+};
+
+#endif // Guard

src/V3EmitC.cpp

@@ -594,7 +594,14 @@ class EmitCImp : EmitCStmts {
 	if (filenum) filenameNoExt += "__"+cvtToStr(filenum);
 	filenameNoExt += (slow ? "__Slow":"");
 	V3OutCFile* ofp = NULL;
-	if (optSystemPerl()) {
+	if (v3Global.opt.lintOnly()) {
+	    // Unfortunately we have some lint checks here, so we can't just skip processing.
+	    // We should move them to a different stage.
+	    string filename = "/dev/null";
+	    newCFile(filename, slow, source);
+	    ofp = new V3OutSpFile (filename);
+	}
+	else if (optSystemPerl()) {
 	    string filename = filenameNoExt+".sp";
 	    newCFile(filename, slow, source);
 	    ofp = new V3OutSpFile (filename);

src/V3EmitMk.cpp

@@ -138,7 +138,7 @@ public:
 
 	    of.puts("\n# Link rules...\n");
 	    of.puts(v3Global.opt.prefix()+": $(VK_USER_OBJS) $(SP_SRCS) $(VM_PREFIX)__ALL.a\n");
-	    of.puts("\t$(CXX) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) 2>&1 | c++filt\n");
+	    of.puts("\t$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) 2>&1 | c++filt\n");
 	    of.puts("\n");
 	}
 

src/V3Error.h

@@ -198,7 +198,8 @@ public:
     void warnOff(V3ErrorCode code, bool flag) { m_warnOff.set(code,flag); }	// Turn on/off warning messages on this line.
     bool warnOff(const string& code, bool flag);  // Returns 1 if ok
     bool warnIsOff(V3ErrorCode code);
-    void warnResetDefault() { m_warnOff=s_defaultFileLine.m_warnOff; }
+    void warnStateFrom(const FileLine& from) { m_warnOff=from.m_warnOff; }
+    void warnResetDefault() { warnStateFrom(s_defaultFileLine); }
 
     void	v3errorEnd(ostringstream& str);
     inline bool operator==(FileLine rhs) { return (m_lineno==rhs.m_lineno && m_filename==rhs.m_filename); }

src/V3Link.cpp

@@ -372,7 +372,8 @@ private:
 	    }
 	}
 	// Deal with implicit definitions
-	if (m_idState==ID_RESOLVE && nodep->modVarp()) {
+	if (m_idState==ID_RESOLVE && nodep->modVarp()
+	    && !nodep->svImplicit()) {   // SV 19.11.3: .name pins don't allow implicit decls
 	    pinImplicitExprRecurse(nodep->exprp());
 	}
 	nodep->iterateChildren(*this);

src/V3LinkCells.cpp

@@ -163,6 +163,32 @@ private:
 		new V3GraphEdge(&m_graph, vertex(m_modp), vertex(modp), 1, false);
 	    }
 	}
+	// Convert .* to list of pins
+	if (nodep->modp() && nodep->pinStar()) {
+	    // Note what pins exist
+	    UINFO(9,"  CELL .* connect "<<nodep<<endl);
+	    V3SymTable  ports;		// Symbol table of all connected port names
+	    for (AstPin* pinp = nodep->pinsp(); pinp; pinp=pinp->nextp()->castPin()) {
+		if (pinp->name()=="") pinp->v3error("Connect by position is illegal in .* connected cells");
+		if (!ports.findIdName(pinp->name())) {
+		    ports.insert(pinp->name(), pinp);
+		}
+	    }
+	    // We search ports, rather then in/out declarations as they aren't resolved yet,
+	    // and it's easier to do it now then in V3Link when we'd need to repeat steps.
+	    for (AstNode* portnodep = nodep->modp()->stmtsp(); portnodep; portnodep=portnodep->nextp()) {
+		if (AstPort* portp = portnodep->castPort()) {
+		    if (!ports.findIdName(portp->name())) {
+			UINFO(9,"    need PORT  "<<portp<<endl);
+			// Create any not already connected
+			AstPin* newp = new AstPin(nodep->fileline(),0,portp->name(),
+						  new AstVarRef(nodep->fileline(),portp->name(),false));
+			newp->svImplicit(true);
+			nodep->addPinsp(newp);
+		    }
+		}
+	    }
+	}
 	// Convert unnamed pins to pin number based assignments
 	for (AstPin* pinp = nodep->pinsp(); pinp; pinp=pinp->nextp()->castPin()) {
 	    if (pinp->name()=="") pinp->name("__pinNumber"+cvtToStr(pinp->pinNum()));

src/V3LinkDot.cpp

@@ -21,7 +21,7 @@
 // LinkDot TRANSFORMATIONS:
 //	Top-down traversal
 //	    Cells:
-//		Make graph of cell hiearchy
+//		Make graph of cell hierarchy
 //	    Var/Funcs's:
 //		Collect all names into symtable under appropriate cell
 //	Top-down traversal
@@ -180,7 +180,7 @@ private:
     // TYPES
     typedef std::multimap<string,LinkDotCellVertex*> NameScopeMap;
     // MEMBERS
-    LinkDotGraph	m_graph;		// Graph of hiearchy
+    LinkDotGraph	m_graph;		// Graph of hierarchy
     NameScopeMap	m_nameScopeMap;		// Hash of scope referenced by non-pretty textual name
     bool		m_forPrearray;		// Compress cell__[array] refs
     bool		m_forScopeCreation;	// Remove VarXRefs for V3Scope
@@ -277,7 +277,7 @@ private:
 public:
     LinkDotBaseVertex* findDotted(LinkDotBaseVertex* cellVxp, const string& dotname,
 				  string& baddot, LinkDotBaseVertex*& okVxp) {
-	// Given a dotted hiearchy name, return where in scope it is
+	// Given a dotted hierarchy name, return where in scope it is
 	// Note when dotname=="" we just fall through and return cellVxp
 	UINFO(8,"    dottedFind "<<dotname<<endl);
 	bool firstId = true;
@@ -520,8 +520,8 @@ private:
     virtual void visit(AstScope* nodep, AstNUser*) {
 	UINFO(8,"  SCOPE "<<nodep<<endl);
 	if (!m_statep->forScopeCreation()) v3fatalSrc("Scopes should only exist right after V3Scope");
-	// Using the CELL names, we created all hiearchy.  We now need to match this Scope
-	// up with the hiearchy created by the CELL names.
+	// Using the CELL names, we created all hierarchy.  We now need to match this Scope
+	// up with the hierarchy created by the CELL names.
 	m_cellVxp = m_statep->findScope(nodep);
 	nodep->iterateChildren(*this);
 	m_cellVxp = NULL;
@@ -610,7 +610,7 @@ private:
 	UINFO(8,"     "<<nodep<<endl);
 	if (!m_cellVxp) {
 	    UINFO(9,"Dead module for "<<nodep<<endl);
-	    nodep->varp(NULL);  // Module that is not in hiearchy.  We'll be dead code eliminating it later.
+	    nodep->varp(NULL);  // Module that is not in hierarchy.  We'll be dead code eliminating it later.
 	} else {
 	    string baddot;
 	    LinkDotBaseVertex* okVxp;
@@ -657,7 +657,7 @@ private:
 	UINFO(8,"     "<<nodep<<endl);
 	if (!m_cellVxp) {
 	    UINFO(9,"Dead module for "<<nodep<<endl);
-	    nodep->taskp(NULL);  // Module that is not in hiearchy.  We'll be dead code eliminating it later.
+	    nodep->taskp(NULL);  // Module that is not in hierarchy.  We'll be dead code eliminating it later.
 	} else {
 	    string baddot;
 	    LinkDotBaseVertex* okVxp;

src/V3LinkParse.cpp

@@ -89,6 +89,10 @@ private:
 	// VarRef: Parse its reference
 	UINFO(5,"   "<<nodep<<endl);
 	// May be a varref inside a select, etc, so save state and recurse
+	string		oldText = m_dotText;
+	bool		oldDot = m_inModDot;
+	AstParseRefExp  oldExp = m_exp;
+	AstText*	oldBasep = m_baseTextp;
 	{
 	    // Replace the parsed item with its child IE the selection tree down to the varref itself
 	    // Do this before iterating, so we don't have to process the edited tree twice
@@ -117,8 +121,14 @@ private:
 	    } else {
 		nodep->v3fatalSrc("Unknown ParseRefExp type\n");
 	    }
+	    nodep->deleteTree(); nodep=NULL;
+	}
+	if (m_exp != AstParseRefExp::FUNC) {  // Fuctions need to look at the name themself
+	    m_dotText = oldText;
+	    m_inModDot = oldDot;
+	    m_exp = oldExp;
+	    m_baseTextp = oldBasep;
 	}
-	nodep->deleteTree(); nodep=NULL;
     }
     virtual void visit(AstDot* nodep, AstNUser*) {
 	UINFO(5,"     "<<nodep<<endl);

src/V3Options.cpp

@@ -383,6 +383,7 @@ void V3Options::parseOptsList(FileLine* fl, int argc, char** argv) {
 	    else if ( onoff   (sw, "-ignc", flag/*ref*/) )	{ m_ignc = flag; }
 	    else if ( onoff   (sw, "-inhibit-sim", flag/*ref*/)){ m_inhibitSim = flag; }
 	    else if ( onoff   (sw, "-l2name", flag/*ref*/) )	{ m_l2Name = flag; }
+	    else if ( onoff   (sw, "-lint-only", flag/*ref*/) )	{ m_lintOnly = flag; }
 	    else if ( onoff   (sw, "-pins64", flag/*ref*/) )	{ m_pins64 = flag; }
 	    else if ( !strcmp (sw, "-private") )		{ m_public = false; }
 	    else if ( onoff   (sw, "-profile-cfuncs", flag/*ref*/) )	{ m_profileCFuncs = flag; }
@@ -453,18 +454,20 @@ void V3Options::parseOptsList(FileLine* fl, int argc, char** argv) {
 		    V3Error::pretendError(code, true);
 		}
 	    }
-	    else if ( !strcmp (sw, "-x-assign") && (i+1)<argc) {
-		shift;
-		if (!strcmp (argv[i], "0")) { m_xAssign="0"; }
-		else if (!strcmp (argv[i], "1")) { m_xAssign="1"; }
-		else if (!strcmp (argv[i], "unique")) { m_xAssign="unique"; }
-		else {
-		    fl->v3fatal("Unknown setting for -x-assign: "<<sw);
-		}
-	    }
 	    else if ( !strcmp (sw, "-bin") && (i+1)<argc ) {
 		shift; m_bin = argv[i];
 	    }
+	    else if ( !strcmp (sw, "-compiler") && (i+1)<argc) {
+		shift;
+		if (!strcmp (argv[i], "gcc")) {
+		    m_compLimitParens = 0;
+		} else if (!strcmp (argv[i], "msvc")) {
+		    m_compLimitParens = 80;   // 128, but allow some room
+		    m_compLimitBlocks = 80;   // 128, but allow some room
+		} else {
+		    fl->v3fatal("Unknown setting for --compiler: "<<argv[i]);
+		}
+	    }
 	    else if ( !strcmp (sw, "-f") && (i+1)<argc ) {
 		shift;
 		parseOptsFile(fl, argv[i]);
@@ -479,6 +482,15 @@ void V3Options::parseOptsList(FileLine* fl, int argc, char** argv) {
 		shift; m_prefix = argv[i];
 		if (m_modPrefix=="") m_modPrefix = m_prefix;
 	    }
+	    else if ( !strcmp (sw, "-x-assign") && (i+1)<argc) {
+		shift;
+		if (!strcmp (argv[i], "0")) { m_xAssign="0"; }
+		else if (!strcmp (argv[i], "1")) { m_xAssign="1"; }
+		else if (!strcmp (argv[i], "unique")) { m_xAssign="unique"; }
+		else {
+		    fl->v3fatal("Unknown setting for --x-assign: "<<argv[i]);
+		}
+	    }
 	    else if ( !strcmp (sw, "-y")) {
 		shift; addIncDir (string (argv[i]));
 	    }
@@ -574,6 +586,7 @@ V3Options::V3Options() {
     m_exe = false;
     m_ignc = false;
     m_l2Name = true;
+    m_lintOnly = false;
     m_makeDepend = true;
     m_makePhony = false;
     m_outFormatOk = false;
@@ -597,6 +610,9 @@ V3Options::V3Options() {
     m_unrollCount = 64;
     m_unrollStmts = 20;
 
+    m_compLimitParens = 0;
+    m_compLimitBlocks = 0;
+
     m_makeDir = "obj_dir";
     m_bin = "";
     m_flags = "";

src/V3Options.h

@@ -56,6 +56,7 @@ class V3Options {
     bool	m_ignc;		// main switch: --ignc
     bool	m_inhibitSim;	// main switch: --inhibit-sim
     bool	m_l2Name;	// main switch: --l2name
+    bool	m_lintOnly;	// main switch: --lint-only
     bool	m_outFormatOk;	// main switch: --cc, --sc or --sp was specified
     bool	m_pins64;	// main switch: --pins64
     bool	m_profileCFuncs;// main switch: --profile-cfuncs
@@ -76,6 +77,9 @@ class V3Options {
     int		m_unrollCount;	// main switch: --unroll-count
     int		m_unrollStmts;	// main switch: --unroll-stmts
 
+    int		m_compLimitBlocks;	// compiler selection options
+    int		m_compLimitParens;	// compiler selection options
+
     string	m_bin;		// main switch: --bin {binary}
     string	m_flags;	// main switch: -f {name}
     string	m_top;		// main switch: Top .v file name
@@ -150,6 +154,7 @@ class V3Options {
     bool psl() const { return m_psl; }
     bool allPublic() const { return m_public; }
     bool l2Name() const { return m_l2Name; }
+    bool lintOnly() const { return m_lintOnly; }
     bool ignc() const { return m_ignc; }
     bool inhibitSim() const { return m_inhibitSim; }
 
@@ -160,6 +165,9 @@ class V3Options {
     int	   unrollCount() const { return m_unrollCount; }
     int	   unrollStmts() const { return m_unrollStmts; }
 
+    int    compLimitBlocks() const { return m_compLimitBlocks; }
+    int    compLimitParens() const { return m_compLimitParens; }
+
     string makeDir() const { return m_makeDir; }
     string prefix() const { return m_prefix; }
     string modPrefix() const { return m_modPrefix; }
@@ -167,6 +175,7 @@ class V3Options {
     const V3StringSet& cppFiles() const { return m_cppFiles; }
     const V3StringSet& libraryFiles() const { return m_libraryFiles; }
 
+
     // ACCESSORS (optimization options)
     bool oAcycSimp() const { return m_oAcycSimp; }
     bool oCase() const { return m_oCase; }

src/V3PreLex.l

@@ -57,6 +57,9 @@ static void pslMoreNeeded(bool flag) { V3PreLex::s_currentLexp->m_pslMoreNeeded
 %x DEFMODE
 %x ARGMODE
 %x INCMODE
+%x PRTMODE
+
+/* drop: Drop Ctrl-Z - can't pass thru or may EOF the output too soon */
 
 ws		[ \t\f\r]
 wsn		[ \t\f]
@@ -64,6 +67,7 @@ crnl		[\r]*[\n]
 quote		[\"]
 backslash	[\\]
 symb		[a-zA-Z_][a-zA-Z0-9_$]*
+drop		[\032]
 psl		[p]sl
 
 	/**************************************************************/
@@ -103,6 +107,13 @@ psl		[p]sl
 			  if (V3PreLex::s_currentLexp->m_parenLevel) appendDefValue(yytext,yyleng);
 			  else return (VP_STRING); }
 
+	/* Protected blocks */
+<INITIAL>"`protected"	{ yy_push_state(PRTMODE); yymore(); }
+<PRTMODE><<EOF>>	{ linenoInc(); yyerror("EOF in `protected"); yyleng=0; yyterminate(); }
+<PRTMODE>{crnl}		{ linenoInc(); yymore(); }
+<PRTMODE>.	 	{ yymore(); }
+<PRTMODE>"`endprotected" { yy_pop_state(); return (VP_TEXT); }
+
 	/* Pass-through include <> filenames */
 <INCMODE><<EOF>>	{ linenoInc(); yyerror("EOF in unterminated include filename"); yyleng=0; yyterminate(); }
 <INCMODE>{crnl}		{ linenoInc(); yyerror("Unterminated include filename"); BEGIN(INITIAL); }
@@ -113,6 +124,7 @@ psl		[p]sl
 	/* Reading definition */
 <DEFMODE>"/*"		{ yy_push_state(CMTMODE); yymore(); }
 <DEFMODE>"//"[^\n\r]*	{ return (VP_COMMENT);}
+<DEFMODE>{drop}		{ }
 <DEFMODE><<EOF>>	{ linenoInc(); yyerror("EOF (missing return?) in define value"); yyleng=0; yyterminate(); }
 <DEFMODE>{crnl}		{ linenoInc(); yy_pop_state(); yytext="\n"; yyleng=1; return (VP_DEFVALUE); }
 <DEFMODE>[\\]{crnl}	{ linenoInc(); appendDefValue("\n",1); } /* Include return so can maintain output line count */
@@ -123,6 +135,7 @@ psl		[p]sl
 	/* Define arguments */
 <ARGMODE>"/*"		{ yy_push_state(CMTMODE); yymore(); }
 <ARGMODE>"//"[^\n\r]*	{ return (VP_COMMENT);}
+<ARGMODE>{drop}		{ }
 <ARGMODE><<EOF>>	{ yyerror("EOF in define argument list\n"); yyleng = 0; yyterminate(); }
 <ARGMODE>{crnl}		{ linenoInc(); yytext="\n"; yyleng=1; return(VP_WHITE); }
 <ARGMODE>{quote}	{ yy_push_state(STRMODE); yymore(); }
@@ -179,8 +192,9 @@ psl		[p]sl
 	/* Generics */
 <INITIAL,PSLMULM>{crnl}		{ linenoInc(); yytext="\n"; yyleng=1; return(VP_WHITE); }
 <INITIAL,PSLMULM,PSLONEM>{symb}	{ return (VP_SYMBOL); }
-<INITIAL,PSLMULM,PSLONEM>[\r]	{ }
 <INITIAL,PSLMULM,PSLONEM>{wsn}+	{ return (VP_WHITE); }
+<INITIAL,PSLMULM,PSLONEM>{drop}	{ }
+<INITIAL,PSLMULM,PSLONEM>[\r]	{ }
 <INITIAL,PSLMULM,PSLONEM>.	{ return (VP_TEXT); }
 %%
 

src/V3PreShell.cpp

@@ -61,12 +61,6 @@ protected:
 	    s_preprocp->define(prefl,"verilator3", "1");
 	    s_preprocp->define(prefl,"systemc_clock", "/*verilator systemc_clock*/");
 	    s_preprocp->define(prefl,"coverage_block_off", "/*verilator coverage_block_off*/");
-	    // Standards - We ignore
-	    s_preprocp->define(prefl,"endcelldefine", "");
-	    s_preprocp->define(prefl,"celldefine", "");
-	    s_preprocp->define(prefl,"resetall", "");
-	    s_preprocp->define(prefl,"portcoerce", "");
-	    s_preprocp->define(prefl,"inline", "");
 	}
     }
 

src/V3Read.h

@@ -38,10 +38,13 @@ class V3Read {
     V3Lexer*	m_lexerp;	// Current FlexLexer
     static V3Read*	s_readp;	// Current THIS, bison() isn't class based
     FileLine*	m_fileline;	// Filename/linenumber currently active
-    bool	m_inLibrary;	// Currently reading a library vs. regular file
+    bool	m_inCellDefine;		// Inside a `celldefine
+    bool	m_inLibrary;		// Currently reading a library vs. regular file
     int		m_inBeginKwd;		// Inside a `begin_keywords
+    int		m_lastVerilogState;	// Last LEX state in `begin_keywords
     deque<string*> m_stringps;		// Created strings for later cleanup
     deque<V3Number*> m_numberps;	// Created numbers for later cleanup
+    deque<FileLine>  m_lintState;	// Current lint state for save/restore
     //int debug() { return 9; }
 
 protected:
@@ -54,9 +57,12 @@ protected:
     static void ppline (const char* text);
     static void incLineno() { s_readp->fileline()->incLineno(); }
     static void verilatorCmtLint(const char* text, bool on);
+    static void verilatorCmtLintSave();
+    static void verilatorCmtLintRestore();
     static void verilatorCmtBad(const char* text);
-    static void pushBeginKeywords() { s_readp->m_inBeginKwd++; }
+    static void pushBeginKeywords(int state) { s_readp->m_inBeginKwd++; s_readp->m_lastVerilogState=state; }
     static bool popBeginKeywords() { if (s_readp->m_inBeginKwd) { s_readp->m_inBeginKwd--; return true; } else return false; }
+    static int lastVerilogState() { return s_readp->m_lastVerilogState; }
 
 public: // But for internal use only
     static string* newString(const string& text) {
@@ -87,17 +93,22 @@ public: // But for internal use only
     static FileLine* fileline() { return s_readp->m_fileline; }
     static AstNetlist* rootp() { return s_readp->m_rootp; }
     static FileLine* copyOrSameFileLine() { return s_readp->fileline()->copyOrSameFileLine(); }
+    static bool inCellDefine() { return s_readp->m_inCellDefine; }
+    static void inCellDefine(bool flag) { s_readp->m_inCellDefine = flag; }
     static bool inLibrary() { return s_readp->m_inLibrary; }
     static void stateExitPsl();	// Parser -> lexer communication
     static void statePushVlg();	// Parser -> lexer communication
     static void statePop();	// Parser -> lexer communication
+    static int stateVerilogRecent();	// Parser -> lexer communication
 
 public:
     // CREATORS
     V3Read(AstNetlist* rootp) {
 	m_rootp = rootp; m_lexerp = NULL;
+	m_inCellDefine = false;
 	m_inLibrary = false;
 	m_inBeginKwd = 0;
+	m_lastVerilogState = stateVerilogRecent();
     }
     ~V3Read() {
 	for (deque<string*>::iterator it = m_stringps.begin(); it != m_stringps.end(); ++it) {

src/Verilator.cpp

@@ -41,6 +41,7 @@
 #include "V3Dead.h"
 #include "V3Delayed.h"
 #include "V3Depth.h"
+#include "V3DepthBlock.h"
 #include "V3Descope.h"
 #include "V3EmitC.h"
 #include "V3EmitMk.h"
@@ -379,6 +380,12 @@ void process () {
 
     //--MODULE OPTIMIZATIONS--------------
 
+    // Split deep blocks to appease MSVC++.  Must be before Localize.
+    if (!v3Global.opt.lintOnly() && v3Global.opt.compLimitBlocks()) {
+	V3DepthBlock::depthBlockAll(v3Global.rootp());
+	v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("deepblock.tree"));
+    }
+
     // Move BLOCKTEMPS from class to local variables
     if (v3Global.opt.oLocalize()) {
 	V3Localize::localizeAll(v3Global.rootp());
@@ -433,24 +440,28 @@ void process () {
 	v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("dead.tree"));
     }
 
-    // Fix very deep expressions
-    // Mark evaluation functions as member functions, if needed.
-    V3Depth::depthAll(v3Global.rootp());
-    //v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("depth.tree"));
+    if (!v3Global.opt.lintOnly()) {
+	// Fix very deep expressions
+	// Mark evaluation functions as member functions, if needed.
+	V3Depth::depthAll(v3Global.rootp());
+	//v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("depth.tree"));
 
-    // Branch prediction
-    V3Branch::branchAll(v3Global.rootp());
+	// Branch prediction
+	V3Branch::branchAll(v3Global.rootp());
 
-    // Add C casts when longs need to become long-long and vice-versa
-    // Note depth may insert something needing a cast, so this must be last.
-    V3Cast::castAll(v3Global.rootp());
-    v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("cast.tree"));
+	// Add C casts when longs need to become long-long and vice-versa
+	// Note depth may insert something needing a cast, so this must be last.
+	V3Cast::castAll(v3Global.rootp());
+	v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("cast.tree"));	
+    }
 
     V3Error::abortIfErrors();
 
     // Output the text
-    V3EmitC::emitcSyms();
-    V3EmitC::emitcTrace();
+    if (!v3Global.opt.lintOnly()) {
+	V3EmitC::emitcSyms();
+	V3EmitC::emitcTrace();
+    }
     V3EmitC::emitc();
 
     // Statistics
@@ -459,8 +470,10 @@ void process () {
 	V3Stats::statsReport();
     }
 
-    // Makefile must be after all other emitters
-    V3EmitMk::emitmk(v3Global.rootp());
+    if (!v3Global.opt.lintOnly()) {
+	// Makefile must be after all other emitters
+	V3EmitMk::emitmk(v3Global.rootp());
+    }
 }
 
 //######################################################################
@@ -481,11 +494,11 @@ int main(int argc, char** argv, char** env) {
     v3Global.opt.bin(argv[0]);
     string argString = V3Options::argString(argc-1, argv+1);
     v3Global.opt.parseOpts(new FileLine("COMMAND_LINE",0), argc-1, argv+1);
-    if (v3Global.opt.coverage() && !v3Global.opt.systemPerl()) {
+    if (v3Global.opt.coverage() && !v3Global.opt.systemPerl() && !v3Global.opt.lintOnly()) {
 	v3fatal("Unsupported: Coverage analysis requires --sp output.");
     }
-    if (!v3Global.opt.outFormatOk() && !v3Global.opt.preprocOnly()) {
-	v3fatal("verilator: Need --cc, --sc, --sp or --E option");
+    if (!v3Global.opt.outFormatOk() && !v3Global.opt.preprocOnly() && !v3Global.opt.lintOnly()) {
+	v3fatal("verilator: Need --cc, --sc, --sp, --lint-only or --E option");
     }
 
     V3Error::abortIfErrors();
@@ -494,6 +507,7 @@ int main(int argc, char** argv, char** env) {
     V3File::addSrcDepend(v3Global.opt.bin());
     if (v3Global.opt.skipIdentical()
 	&& !v3Global.opt.preprocOnly()
+	&& !v3Global.opt.lintOnly()
 	&& V3File::checkTimes(v3Global.opt.makeDir()+"/"+v3Global.opt.prefix()+"__verFiles.dat", argString)) {
 	UINFO(1,"--skip-identical: No change to any source files, exiting\n");
 	exit(0);
@@ -526,10 +540,11 @@ int main(int argc, char** argv, char** env) {
     v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("final.tree",99));
     V3Error::abortIfErrors();
 
-    if (v3Global.opt.makeDepend()) {
+    if (!v3Global.opt.lintOnly() && v3Global.opt.makeDepend()) {
 	V3File::writeDepend(v3Global.opt.makeDir()+"/"+v3Global.opt.prefix()+"__ver.d");
     }
-    if (v3Global.opt.skipIdentical() || v3Global.opt.makeDepend()) { 
+    if (!v3Global.opt.lintOnly()
+	&& (v3Global.opt.skipIdentical() || v3Global.opt.makeDepend())) { 
 	V3File::writeTimes(v3Global.opt.makeDir()+"/"+v3Global.opt.prefix()+"__verFiles.dat", argString);
     }
 

src/config_build.h.in

@@ -24,7 +24,7 @@
 //**********************************************************************
 //**** Version and host name
 
-#define DTVERSION	"Verilator 3.640 3/12/2007"
+#define DTVERSION	"Verilator 3.651 4/20/2007"
 
 //**********************************************************************
 //**** Functions

src/flexfix

@@ -19,7 +19,7 @@
 #                                                                           
 ######################################################################
 
-# DESCRIPTION: Edits flex output to get around Redhat 8.0 broken flex.
+# DESCRIPTION: Edits flex output to get around various broken flex issues.
 
 foreach my $line (<STDIN>) {
     # Fix flex 2.5.4 namespace omission
@@ -28,5 +28,9 @@ foreach my $line (<STDIN>) {
     $line =~ s!(\#define\s+yyFlexLexer\s+yyFlexLexer)!//flexfix: $1!g;
     # Fix flex 2.5.1 yytext_ptr undef
     $line =~ s!(\#undef\s+yytext_ptr)!//flexfix: $1!g;
+    # Fix flex 2.5.4 and GCC 4.1.0 warn_unused_result
+    $line =~ s!\(void\) *fwrite\((.*)\)!if (fwrite($1)) {}!g;
+    # Fix flex 2.5.33 and GCC 4.1.2 "warning: comparison between signed and unsigned integer expressions" in YY_INPUT
+    $line =~ s!for \( n = 0; n < max_size && !for ( n = 0; ((size_t)n < (size_t)max_size) && !g;
     print "$line";
 }

src/verilog.l

@@ -54,6 +54,19 @@ void V3Read::verilatorCmtLint(const char* textp, bool warnOff) {
 	yyerrorf("Unknown verilator lint message code: %s, in %s",msg.c_str(), textp);
     }
 }
+
+void V3Read::verilatorCmtLintSave() {
+    s_readp->m_lintState.push_back(*V3Read::fileline());
+}
+void V3Read::verilatorCmtLintRestore() {
+    if (s_readp->m_lintState.empty()) {
+	yyerror("/*verilator lint_restore*/ without matching save.");
+	return;
+    }
+    V3Read::fileline()->warnStateFrom(s_readp->m_lintState.back());
+    s_readp->m_lintState.pop_back();
+}
+
 void V3Read::verilatorCmtBad(const char* textp) {
     yyerrorf("Unknown verilator comment: %s",textp);
 }
@@ -91,11 +104,12 @@ void yyerrorf(const char* format, ...) {
 %o 25000
 
 %s V95 V01 V05 S05
-%s PSL STRING
+%s PSL STRING ATTRMODE
 %s SYSCHDR SYSCINT SYSCIMP SYSCIMPH SYSCCTOR SYSCDTOR
 %s IGNORE
 
 ws	[ \t\f\r]+
+wsnr	[ \t\f]+
 	/* identifier */
 id	[a-zA-Z_][a-zA-Z0-9_$]*
 	/* escaped identifier */
@@ -117,38 +131,39 @@ escid	\\[^ \t\f\r\n]+
   "$fdisplay"		{yylval.fileline = CRELINE(); return yD_FDISPLAY;}
   "$finish"		{yylval.fileline = CRELINE(); return yD_FINISH;}
   "$fopen"		{yylval.fileline = CRELINE(); return yD_FOPEN;}
-  "$fullskew"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
+  "$fullskew"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
   "$fwrite"		{yylval.fileline = CRELINE(); return yD_FWRITE;}
-  "$hold"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-  "$nochange"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-  "$period"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
+  "$hold"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
+  "$nochange"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
+  "$period"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
   "$readmemb"		{yylval.fileline = CRELINE(); return yD_READMEMB;}
   "$readmemh"		{yylval.fileline = CRELINE(); return yD_READMEMH;}
   "$realtime"		{yylval.fileline = CRELINE(); return yD_TIME;}
-  "$recovery"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-  "$recrem"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-  "$removal"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-  "$setup"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-  "$setuphold"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-  "$skew"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
+  "$recovery"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
+  "$recrem"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
+  "$removal"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
+  "$setup"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
+  "$setuphold"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
+  "$skew"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
   "$stop"		{yylval.fileline = CRELINE(); return yD_STOP;}
   "$time"		{yylval.fileline = CRELINE(); return yD_TIME;}
-  "$timeskew"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-  "$width"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
+  "$timeskew"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
+  "$width"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
   "$write"		{yylval.fileline = CRELINE(); return yD_WRITE;}
   /*     Keywords */
   "always"		{yylval.fileline = CRELINE(); return yALWAYS;}
   "and"			{yylval.fileline = CRELINE(); return yAND;}
   "assign"		{yylval.fileline = CRELINE(); return yASSIGN;}
-  "begin"		{yylval.fileline = CRELINE(); return yBBEGIN;}
+  "begin"		{yylval.fileline = CRELINE(); return yBEGIN;}
   "buf"			{yylval.fileline = CRELINE(); return yBUF;}
   "case"		{yylval.fileline = CRELINE(); return yCASE;}
   "casex"		{yylval.fileline = CRELINE(); return yCASEX;}
   "casez"		{yylval.fileline = CRELINE(); return yCASEZ;}
   "default"		{yylval.fileline = CRELINE(); return yDEFAULT;}
   "defparam"		{yylval.fileline = CRELINE(); return yDEFPARAM;}
+  "edge"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
   "else"		{yylval.fileline = CRELINE(); return yELSE;}
-  "end"			{yylval.fileline = CRELINE(); return yBEND;}
+  "end"			{yylval.fileline = CRELINE(); return yEND;}
   "endcase"		{yylval.fileline = CRELINE(); return yENDCASE;}
   "endfunction"		{yylval.fileline = CRELINE(); return yENDFUNCTION;}
   "endmodule"		{yylval.fileline = CRELINE(); return yENDMODULE;}
@@ -169,17 +184,18 @@ escid	\\[^ \t\f\r\n]+
   "not"			{yylval.fileline = CRELINE(); return yNOT;}
   "or"			{yylval.fileline = CRELINE(); return yOR;}
   "output"		{yylval.fileline = CRELINE(); return yOUTPUT;}
-  "parameter"		{yylval.fileline = CRELINE(); return yPARAM;}
+  "parameter"		{yylval.fileline = CRELINE(); return yPARAMETER;}
   "posedge"		{yylval.fileline = CRELINE(); return yPOSEDGE;}
   "reg"			{yylval.fileline = CRELINE(); return yREG;}
   "scalared"		{yylval.fileline = CRELINE(); return ySCALARED;}
   "specify"		{yylval.fileline = CRELINE(); return ySPECIFY;}
-  "specparam"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
+  "specparam"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
   "supply0"		{yylval.fileline = CRELINE(); return ySUPPLY0;}
   "supply1"		{yylval.fileline = CRELINE(); return ySUPPLY1;}
   "task"		{yylval.fileline = CRELINE(); return yTASK;}
   "tri"			{yylval.fileline = CRELINE(); return yTRI;}
   "vectored"		{yylval.fileline = CRELINE(); return yVECTORED;}
+  "while"		{yylval.fileline = CRELINE(); return yWHILE;}
   "wire"		{yylval.fileline = CRELINE(); return yWIRE;}
   "xnor"		{yylval.fileline = CRELINE(); return yXNOR;}
   "xor"			{yylval.fileline = CRELINE(); return yXOR;}
@@ -202,7 +218,6 @@ escid	\\[^ \t\f\r\n]+
   "cmos"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
   "deassign"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
   "disable"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
-  "edge"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
   "endprimitive"	{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
   "endtable"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
   "event"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
@@ -250,7 +265,6 @@ escid	\\[^ \t\f\r\n]+
   "wand"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
   "weak0"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
   "weak1"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
-  "while"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
   "wor"			{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
 }
 
@@ -260,30 +274,30 @@ escid	\\[^ \t\f\r\n]+
   "$signed"		{yylval.fileline = CRELINE(); return yD_SIGNED;}
   "$unsigned"		{yylval.fileline = CRELINE(); return yD_UNSIGNED;}
   /*     Keywords */
+  "automatic"		{yylval.fileline = CRELINE(); return yAUTOMATIC;}
   "endgenerate"		{yylval.fileline = CRELINE(); return yENDGENERATE;}
   "generate"		{yylval.fileline = CRELINE(); return yGENERATE;}
   "genvar"		{yylval.fileline = CRELINE(); return yGENVAR;}
+  "ifnone"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
   "localparam"		{yylval.fileline = CRELINE(); return yLOCALPARAM;}
+  "noshowcancelled"	{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
+  "pulsestyle_ondetect"	{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
+  "pulsestyle_onevent"	{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
+  "showcancelled"	{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
   "signed"		{yylval.fileline = CRELINE(); return ySIGNED;}
+  "unsigned"		{yylval.fileline = CRELINE(); return yUNSIGNED;}
   /*     Special errors */
-  "include"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented; probably you want `include instead: %s",yytext);}
+  "include"		{yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented; probably you want `include instead: %s",yytext);}
   /*     Generic unsupported warnings */
-  "automatic"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "cell"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "config"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "design"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "endconfig"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "ifnone"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "incdir"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "instance"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "liblist"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "library"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "noshowcancelled"	{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "pulsestyle_ondetect"	{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "pulsestyle_onevent"	{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "showcancelled"	{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "unsigned"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "use"			{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
+  "cell"		{yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);}
+  "config"		{yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);}
+  "design"		{yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);}
+  "endconfig"		{yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);}
+  "incdir"		{yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);}
+  "instance"		{yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);}
+  "liblist"		{yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);}
+  "library"		{yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);}
+  "use"			{yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);}
 }
 
   /* Verilog 2005 */
@@ -308,6 +322,7 @@ escid	\\[^ \t\f\r\n]+
   "always_comb"		{yylval.fileline = CRELINE(); return yALWAYS;}
   "always_ff"		{yylval.fileline = CRELINE(); return yALWAYS;}
   "always_latch"	{yylval.fileline = CRELINE(); return yALWAYS;}
+  "do"			{yylval.fileline = CRELINE(); return yDO;}
   "final"		{yylval.fileline = CRELINE(); return yFINAL;}
   /*     Generic unsupported warnings */
   /* Note assert_strobe was in SystemVerilog 3.1, but removed for SystemVerilog 2005 */
@@ -328,7 +343,6 @@ escid	\\[^ \t\f\r\n]+
   "coverpoint"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
   "cross"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
   "dist"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
-  "do"			{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
   "endcass"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
   "endclocking"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
   "endgroup"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
@@ -515,6 +529,7 @@ escid	\\[^ \t\f\r\n]+
   "/*verilator coverage_block_off*/"	{yylval.fileline = CRELINE(); return yVL_COVER_OFF;}
   "/*verilator full_case*/"		{yylval.fileline = CRELINE(); return yVL_FULL_CASE;}
   "/*verilator inline_module*/"		{yylval.fileline = CRELINE(); return yVL_INLINE_MODULE;}
+  "/*verilator isolate_assignments*/"	{yylval.fileline = CRELINE(); return yVL_ISOLATE_ASSIGNMENTS;}
   "/*verilator no_inline_module*/"	{yylval.fileline = CRELINE(); return yVL_NO_INLINE_MODULE;}
   "/*verilator no_inline_task*/"	{yylval.fileline = CRELINE(); return yVL_NO_INLINE_TASK;}
   "/*verilator parallel_case*/"		{yylval.fileline = CRELINE(); return yVL_PARALLEL_CASE;}
@@ -522,12 +537,13 @@ escid	\\[^ \t\f\r\n]+
   "/*verilator public_flat*/"		{yylval.fileline = CRELINE(); return yVL_PUBLIC_FLAT;}
   "/*verilator public_module*/"		{yylval.fileline = CRELINE(); return yVL_PUBLIC_MODULE;}
   "/*verilator sc_clock*/"		{yylval.fileline = CRELINE(); return yVL_CLOCK;}
-  "/*verilator isolate_assignments*/"	{yylval.fileline = CRELINE(); return yVL_ISOLATE_ASSIGNMENTS;}
   "/*verilator systemc_clock*/"		{yylval.fileline = CRELINE(); return yVL_CLOCK;}
   "/*verilator tracing_off*/"		{yylval.fileline = CRELINE(); return yVL_TRACING_OFF;}
   "/*verilator tracing_on*/"		{yylval.fileline = CRELINE(); return yVL_TRACING_ON;}
   "/*verilator lint_off"[^*]*"*/"	{V3Read::verilatorCmtLint(yytext, true); }
   "/*verilator lint_on"[^*]*"*/"	{V3Read::verilatorCmtLint(yytext, false); }
+  "/*verilator lint_restore*/"		{V3Read::verilatorCmtLintRestore(); }
+  "/*verilator lint_save*/"		{V3Read::verilatorCmtLintSave(); }
 
   "/*"[^*]*"*/"				{V3Read::verilatorCmtBad(yytext); }
 }
@@ -537,45 +553,45 @@ escid	\\[^ \t\f\r\n]+
 
   /* Verilog 1995 Operators */
 <V95,V01,V05,S05,PSL>{
-  "&&"			{yylval.fileline = CRELINE(); return yANDAND;}
-  "||"			{yylval.fileline = CRELINE(); return yOROR;}
-  "<="			{yylval.fileline = CRELINE(); return yLTE;}
-  ">="			{yylval.fileline = CRELINE(); return yGTE;}
-  "<<"			{yylval.fileline = CRELINE(); return ySLEFT;}
-  ">>"			{yylval.fileline = CRELINE(); return ySRIGHT;}
-  "=="			{yylval.fileline = CRELINE(); return yEQUAL;}
-  "!="			{yylval.fileline = CRELINE(); return yNOTEQUAL;}
-  "==="			{yylval.fileline = CRELINE(); return yCASEEQUAL;}
-  "!=="			{yylval.fileline = CRELINE(); return yCASENOTEQUAL;}
-  "^~"			{yylval.fileline = CRELINE(); return yOP_XNOR;}
-  "~^"			{yylval.fileline = CRELINE(); return yOP_XNOR;}
-  "~&"			{yylval.fileline = CRELINE(); return yOP_NAND;}
-  "~|"			{yylval.fileline = CRELINE(); return yOP_NOR;}
+  "&&"			{yylval.fileline = CRELINE(); return yP_ANDAND;}
+  "||"			{yylval.fileline = CRELINE(); return yP_OROR;}
+  "<="			{yylval.fileline = CRELINE(); return yP_LTE;}
+  ">="			{yylval.fileline = CRELINE(); return yP_GTE;}
+  "<<"			{yylval.fileline = CRELINE(); return yP_SLEFT;}
+  ">>"			{yylval.fileline = CRELINE(); return yP_SRIGHT;}
+  "=="			{yylval.fileline = CRELINE(); return yP_EQUAL;}
+  "!="			{yylval.fileline = CRELINE(); return yP_NOTEQUAL;}
+  "==="			{yylval.fileline = CRELINE(); return yP_CASEEQUAL;}
+  "!=="			{yylval.fileline = CRELINE(); return yP_CASENOTEQUAL;}
+  "^~"			{yylval.fileline = CRELINE(); return yP_XNOR;}
+  "~^"			{yylval.fileline = CRELINE(); return yP_XNOR;}
+  "~&"			{yylval.fileline = CRELINE(); return yP_NAND;}
+  "~|"			{yylval.fileline = CRELINE(); return yP_NOR;}
 }
 
   /* Verilog 2001 Operators */
 <V01,V05,S05,PSL>{
-  "<<<"			{yylval.fileline = CRELINE(); return ySLEFT;}
-  ">>>"			{yylval.fileline = CRELINE(); return ySSRIGHT;}
-  "**"			{yylval.fileline = CRELINE(); return yPOW;}
-  "+:"			{yylval.fileline = CRELINE(); return yPLUSCOLON;}
-  "-:"			{yylval.fileline = CRELINE(); return yMINUSCOLON;}
+  "<<<"			{yylval.fileline = CRELINE(); return yP_SLEFT;}
+  ">>>"			{yylval.fileline = CRELINE(); return yP_SSRIGHT;}
+  "**"			{yylval.fileline = CRELINE(); return yP_POW;}
+  "+:"			{yylval.fileline = CRELINE(); return yP_PLUSCOLON;}
+  "-:"			{yylval.fileline = CRELINE(); return yP_MINUSCOLON;}
 }
 
   /* PSL Operators */
 <PSL>{
   "{"			{yylval.fileline = CRELINE(); return yPSL_BRA;}	// Avoid parser hitting concatenate.
   "}"			{yylval.fileline = CRELINE(); return yPSL_KET;}	// Avoid parser hitting concatenate.
-  "->"			{yylval.fileline = CRELINE(); return yOP_LOGIF;}
+  "->"			{yylval.fileline = CRELINE(); return yP_LOGIF;}
   "<->"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} //Unsup in other tools
-  "[*"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yBRA_STAR
-  "[*]"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yBRA_STAR_KET
-  "[+]"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yBRA_PLUS_KET
-  "[->"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yBRA_MINUS_GT
-  "[->]"		{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yBRA_MINUS_GT_KET
-  "[="			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yBRA_EQ
-  "|->"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yOR_MINUS_GT
-  "|=>"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yOR_EQ_GT
+  "[*"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_BRA_STAR
+  "[*]"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_BRA_STAR_KET
+  "[+]"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_BRA_PLUS_KET
+  "[->"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_BRA_MINUS_GT
+  "[->]"		{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_BRA_MINUS_GT_KET
+  "[="			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_BRA_EQ
+  "|->"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_OR_MINUS_GT
+  "|=>"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_OR_EQ_GT
 }
 
   /* Identifiers and numbers */
@@ -589,45 +605,42 @@ escid	\\[^ \t\f\r\n]+
 			   } else {
 			       yylval.strp = V3Read::newString(yytext); // Need _ as "6..." isn't legal ID
 			   }
-			   return yID;
+			   return yaID;
 			 }
 
   {id}			{  yylval.strp = V3Read::newString(yytext);
-			   return yID;
+			   return yaID;
 			 }
 
   \"[^\"\\]*\"		{  yylval.strp = V3Read::newString(yytext+1,yyleng-2);
-			   return ySTRING;
+			   return yaSTRING;
 			}
   \" 			{ yy_push_state(STRING); yymore(); }
 
 
   [0-9]*?['']s?[bcodhBCODH][ \t]*[A-Fa-f0-9xXzZ_?]*	{
 			  yylval.nump = V3Read::newNumber(V3Read::fileline(),(char*)yytext);
-                          return yINTNUM;
+                          return yaINTNUM;
 			}
   [0-9]*?['']s?[01xXzZ]	{	/* SystemVerilog */
 			  yylval.nump = V3Read::newNumber(V3Read::fileline(),(char*)yytext);
-                          return yINTNUM;
+                          return yaINTNUM;
 			}
-  [0-9]+[_0-9]*[ \t]*['']s?[bcodhBCODH]?[ \t]*[A-Fa-f0-9xXzZ_?]*	{
+  [0-9][_0-9]*[ \t]*['']s?[bcodhBCODH]?[ \t]*[A-Fa-f0-9xXzZ_?]*	{
 			  yylval.nump = V3Read::newNumber(V3Read::fileline(),(char*)yytext);
-                          return yINTNUM;
+                          return yaINTNUM;
 			}
-  [0-9]*		{ yylval.nump = V3Read::newNumber(V3Read::fileline(),(char*)yytext);
-                          return yINTNUM;
+  [0-9][_0-9]*		{ yylval.nump = V3Read::newNumber(V3Read::fileline(),(char*)yytext);
+                          return yaINTNUM;
 			}
-  [-+]?[0-9]+(\.[0-9]+)([eE][-+]?[0-9]+)? {
+  [0-9][_0-9]*(\.[_0-9]+)([eE][-+]?[_0-9]+)? {
     			  yylval.cdouble = 0;  /* Only for delays, not used yet */
-                          return yFLOATNUM;
+                          return yaFLOATNUM;
 			}
-  [-+]?[0-9]+(\.[0-9]+)?([eE][-+]?[0-9]+) {
+  [0-9][_0-9]*(\.[_0-9]+)?([eE][-+]?[_0-9]+) {
     			  yylval.cdouble = 0;  /* Only for delays, not used yet */
-                          return yFLOATNUM;
+                          return yaFLOATNUM;
 			}
-
-  "`timescale"{ws}+[^\n]*	{}
-  "`line"{ws}+[^\n]*\n		{V3Read::ppline(yytext);}
 }
 
   /************************************************************************/
@@ -638,42 +651,65 @@ escid	\\[^ \t\f\r\n]+
 <STRING>\\.	 	{ yymore(); }
 <STRING>\" 		{ yy_pop_state();
 			  yylval.strp = V3Read::newString(yytext+1,yyleng-2);
-			  return ySTRING; }
+			  return yaSTRING; }
 
   /************************************************************************/
+  /* Attributes */
+<ATTRMODE>\n		{ yymore(); NEXTLINE(); }
+<ATTRMODE>"*)"		{ yy_pop_state(); } 
+<ATTRMODE>. 		{ yymore(); }
+<ATTRMODE><<EOF>>	{ yyerror("EOF in (*");
+			  yyleng = 0; }
+
+  /************************************************************************/
+  /* Attributes */
+<V95,V01,V05,S05>{
+    "(*" 		{ yymore(); yy_push_state(ATTRMODE); }
+}
+
+  /************************************************************************/
+  /* Preprocessor*/
   /* Common for all SYSC header states */
   /* OPTIMIZE: we return one per line, make it one for the entire block */
 <V95,V01,V05,S05,PSL,SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{
-  [ \t]*"`verilog"			{ BEGIN V95; }
-  [ \t]*"`psl"				{ if (V3Read::optPsl()) { BEGIN PSL; } else { BEGIN IGNORE; } }
-  [ \t]*"`systemc_header"		{ BEGIN SYSCHDR; }
-  [ \t]*"`systemc_ctor"			{ BEGIN SYSCCTOR; }
-  [ \t]*"`systemc_dtor"			{ BEGIN SYSCDTOR; }
-  [ \t]*"`systemc_interface"		{ BEGIN SYSCINT; }
-  [ \t]*"`systemc_implementation"	{ BEGIN SYSCIMP; }
-  [ \t]*"`systemc_imp_header"		{ BEGIN SYSCIMPH; }
+  "`celldefine"				{ V3Read::inCellDefine(true); }
+  "`endcelldefine"			{ V3Read::inCellDefine(false); }
+  "`endprotect"				{ }
+  "`inline"				{ }
+  "`line"{ws}+[^\n]*\n			{ V3Read::ppline(yytext); }
+  "`portcoerce"				{ }
+  "`protect"				{ }
+  "`psl"				{ if (V3Read::optPsl()) { BEGIN PSL; } else { BEGIN IGNORE; } }
+  "`resetall"				{ }
+  "`systemc_ctor"			{ BEGIN SYSCCTOR; }
+  "`systemc_dtor"			{ BEGIN SYSCDTOR; }
+  "`systemc_header"			{ BEGIN SYSCHDR; }
+  "`systemc_imp_header"			{ BEGIN SYSCIMPH; }
+  "`systemc_implementation"		{ BEGIN SYSCIMP; }
+  "`systemc_interface"			{ BEGIN SYSCINT; }
+  "`timescale"{ws}+[^\n]*		{}
+  "`verilog"				{ BEGIN V3Read::lastVerilogState(); }
 
-  [ \t]*"`begin_keywords"[ \t]*\"1364-1995\"		{ yy_push_state(V95); V3Read::pushBeginKeywords();}
-  [ \t]*"`begin_keywords"[ \t]*\"1364-2001\"		{ yy_push_state(V01); V3Read::pushBeginKeywords();}
-  [ \t]*"`begin_keywords"[ \t]*\"1364-2001-noconfig\"	{ yy_push_state(V01); V3Read::pushBeginKeywords();}
-  [ \t]*"`begin_keywords"[ \t]*\"1364-2005\"		{ yy_push_state(V05); V3Read::pushBeginKeywords();}
-  [ \t]*"`begin_keywords"[ \t]*\"1800-2005\"		{ yy_push_state(S05); V3Read::pushBeginKeywords();}
-  [ \t]*"`end_keywords"					{ yy_pop_state(); if (!V3Read::popBeginKeywords()) yyerrorf("`end_keywords when not inside `begin_keywords block"); }
-
-  "`line"[ \t][^\n]*\n			{V3Read::ppline(yytext);}
+  "`begin_keywords"[ \t]*\"1364-1995\"		{ yy_push_state(V95); V3Read::pushBeginKeywords(YY_START);}
+  "`begin_keywords"[ \t]*\"1364-2001\"		{ yy_push_state(V01); V3Read::pushBeginKeywords(YY_START);}
+  "`begin_keywords"[ \t]*\"1364-2001-noconfig\"	{ yy_push_state(V01); V3Read::pushBeginKeywords(YY_START);}
+  "`begin_keywords"[ \t]*\"1364-2005\"		{ yy_push_state(V05); V3Read::pushBeginKeywords(YY_START);}
+  "`begin_keywords"[ \t]*\"1800-2005\"		{ yy_push_state(S05); V3Read::pushBeginKeywords(YY_START);}
+  "`end_keywords"					{ yy_pop_state(); if (!V3Read::popBeginKeywords()) yyerrorf("`end_keywords when not inside `begin_keywords block"); }
 }
 
-<SYSCHDR>[ \t]*[^` \t\n][^\n]*\n	{ NEXTLINE(); yylval.strp = V3Read::newString(yytext); return ySCHDR;}
-<SYSCINT>[ \t]*[^` \t\n][^\n]*\n	{ NEXTLINE(); yylval.strp = V3Read::newString(yytext); return ySCINT;}
-<SYSCIMP>[ \t]*[^` \t\n][^\n]*\n	{ NEXTLINE(); yylval.strp = V3Read::newString(yytext); return ySCIMP;}
-<SYSCIMPH>[ \t]*[^` \t\n][^\n]*\n	{ NEXTLINE(); yylval.strp = V3Read::newString(yytext); return ySCIMPH;}
-<SYSCCTOR>[ \t]*[^` \t\n][^\n]*\n	{ NEXTLINE(); yylval.strp = V3Read::newString(yytext); return ySCCTOR;}
-<SYSCDTOR>[ \t]*[^` \t\n][^\n]*\n	{ NEXTLINE(); yylval.strp = V3Read::newString(yytext); return ySCDTOR;}
+<SYSCHDR>[ \t]*[^` \t\n][^\n]*\n	{ NEXTLINE(); yylval.strp = V3Read::newString(yytext); return yaSCHDR;}
+<SYSCINT>[ \t]*[^` \t\n][^\n]*\n	{ NEXTLINE(); yylval.strp = V3Read::newString(yytext); return yaSCINT;}
+<SYSCIMP>[ \t]*[^` \t\n][^\n]*\n	{ NEXTLINE(); yylval.strp = V3Read::newString(yytext); return yaSCIMP;}
+<SYSCIMPH>[ \t]*[^` \t\n][^\n]*\n	{ NEXTLINE(); yylval.strp = V3Read::newString(yytext); return yaSCIMPH;}
+<SYSCCTOR>[ \t]*[^` \t\n][^\n]*\n	{ NEXTLINE(); yylval.strp = V3Read::newString(yytext); return yaSCCTOR;}
+<SYSCDTOR>[ \t]*[^` \t\n][^\n]*\n	{ NEXTLINE(); yylval.strp = V3Read::newString(yytext); return yaSCDTOR;}
 <IGNORE>[ \t]*[^` \t\n][^\n]*\n		{ NEXTLINE(); }
 
   /* Pick up text-type data */
 <SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{
-  [ \t]*\n		{ NEXTLINE(); yymore();}
+  {wsnr}*		{ yymore();}
+  \n			{ NEXTLINE(); yymore();}
   \r			;
 }
 
@@ -682,13 +718,11 @@ escid	\\[^ \t\f\r\n]+
 
 <V95,V01,V05,S05,PSL>{
   "`"[a-zA-Z_0-9]+	{ yyerrorf("Define or directive not defined: %s",yytext); }
-
   "//"[^\n]+		{ }  /* throw away single line comments */
-
   .			{yylval.fileline = CRELINE(); return yytext[0];}	/* return single char ops. */
 }
 
   /* Catch all - absolutely last */
 <*>.|\n     		{ yyerrorf("Missing verilog.l rule: Default rule invoked in state %d: %s", YY_START, yytext); }
 %%
-
+int V3Read::stateVerilogRecent() { return STATE_VERILOG_RECENT; }

test_c/Makefile_obj

@@ -34,6 +34,6 @@ ifeq ($(VM_TRACE),1)
 endif
 
 simx: sim_main.o $(SP_SRCS) $(VM_PREFIX)__ALL.a
-	$(CXX) $(LDFLAGS) -g $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) 2>&1 | c++filt
+	$(LINK) $(LDFLAGS) -g $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) 2>&1 | c++filt
 
 sim_main.o: sim_main.cpp $(VM_PREFIX).h

test_regress/Makefile_obj

@@ -43,7 +43,7 @@ endif
 
 #Default compile, using normal make rules
 #$(VM_PREFIX): $(SP_SRCS) $(VK_OBJS)
-#	$(CXX) $(LDFLAGS) -g $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) 2>&1 | c++filt
+#	$(LINK) $(LDFLAGS) -g $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) 2>&1 | c++filt
 
 #Our own compile rules; Faster compile, all in one file
 $(VM_PREFIX)__ALLboth.cpp: $(VK_CLASSES_CPP) $(VK_SUPPORT_CPP)
@@ -54,5 +54,5 @@ $(VM_PREFIX)__ALLboth.o: $(VM_PREFIX)__ALLboth.cpp
 
 ifneq ($(MAKE_MAIN),0)
    $(VM_PREFIX): $(VM_PREFIX)__ALLboth.o
-	$(CXX) $(LDFLAGS) -g $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) 2>&1 | c++filt
+	$(LINK) $(LDFLAGS) -g $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) 2>&1 | c++filt
 endif

test_regress/driver.pl

@@ -32,8 +32,8 @@ use vars qw ($Debug %Vars $Driver $Fork);
 
 $::Driver = 1;
 
-eval "use Parallel::Forker; \$Fork=Parallel::Forker->new();";
-$Fork = Forker->new() if !$Fork;
+eval "use Parallel::Forker; \$Fork=Parallel::Forker->new(use_sig_child=>1);";
+$Fork = Forker->new(use_sig_child=>1) if !$Fork;
 $SIG{CHLD} = sub { $Fork->sig_child() if $Fork; };
 $SIG{TERM} = sub { $Fork->kill_tree_all('TERM') if $Fork; die "Quitting...\n"; };
 
@@ -205,6 +205,7 @@ sub new {
 	# Verilator
 	'v3' => 0,
 	verilator_flags => [split(/\s+/,"-cc")],
+	verilator_flags2 => [],
 	verilator_make_gcc => 1,
 	verilated_debug => $Opt_Verilated_Debug,
 	stdout_filename => undef,	# Redirect stdout
@@ -292,7 +293,7 @@ sub compile {
 	$self->_make_top();
 	$self->_run(logfile=>"obj_dir/".$self->{name}."_vcs_compile.log",
 		    fails=>$param{fails},
-		    cmd=>["vcs",
+		    cmd=>[($ENV{VERILATOR_VCS}||"vcs"),
 			  @{$param{vcs_flags}},
 			  @{$param{vcs_flags2}},
 			  @{$param{v_flags}},
@@ -306,7 +307,7 @@ sub compile {
 	$self->_make_top();
 	$self->_run(logfile=>"obj_dir/".$self->{name}."_nc_compile.log",
 		    fails=>$param{fails},
-		    cmd=>["ncverilog",
+		    cmd=>[($ENV{VERILATOR_NCVERILOG}||"ncverilog"),
 			  @{$param{nc_flags}},
 			  @{$param{nc_flags2}},
 			  @{$param{v_flags}},
@@ -338,6 +339,7 @@ sub compile {
 	my @v3args = ("perl","../bin/verilator",
 		      "--prefix ".$self->{VM_PREFIX},
 		      @{$param{verilator_flags}},
+		      @{$param{verilator_flags2}},
 		      @{$param{v_flags}},
 		      @{$param{v_flags2}},
 		      $param{top_filename},
@@ -846,6 +848,24 @@ Run using Verilator.
 
 =back
 
+=head1 ENVIRONMENT
+
+=over 4
+
+=item SYSTEMC
+
+Root directory name of SystemC kit.
+
+=item VERILATOR_NCVERILOG
+
+Command to use to invoke ncverilog.
+
+=item VERILATOR_VCS
+
+Command to use to invoke VCS.
+
+=back
+
 =head1 SEE ALSO
 
 =head1 AUTHORS

test_regress/t/t_case_deep.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 verilator_flags2 => ["--compiler msvc"],  # We have deep expressions we want to test
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_case_deep.v

@@ -0,0 +1,342 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer 	cyc=0;
+   reg [63:0] 	crc;
+   reg [63:0] 	sum;
+
+   // Take CRC data and apply to testblock inputs
+   wire [33:0]  in = crc[33:0];
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [31:0]		code;			// From test of Test.v
+   wire [4:0]		len;			// From test of Test.v
+   wire			next;			// From test of Test.v
+   // End of automatics
+
+   Test test (/*AUTOINST*/
+	      // Outputs
+	      .next			(next),
+	      .code			(code[31:0]),
+	      .len			(len[4:0]),
+	      // Inputs
+	      .clk			(clk),
+	      .in			(in[33:0]));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = {26'h0, next, len, code};
+
+   // What checksum will we end up with
+`define EXPECTED_SUM 64'h5537fa30d49bf865
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+	 // Setup
+	 crc <= 64'h5aef0c8d_d70a4497;
+      end
+      else if (cyc<10) begin
+	 sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 if (sum !== `EXPECTED_SUM) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+endmodule
+
+module Test (/*AUTOARG*/
+   // Outputs
+   next, code, len,
+   // Inputs
+   clk, in
+   );
+
+   input clk;
+   input  [33:0] in;   
+   output 	 next;
+   output [31:0] code;
+   output [4:0]	 len;
+
+   /*AUTOREG*/
+   // Beginning of automatic regs (for this module's undeclared outputs)
+   reg [31:0]		code;
+   reg [4:0]		len;
+   reg			next;
+   // End of automatics
+
+/*
+#!/usr/bin/perl -w
+srand(5);
+my @used;
+pat:
+  for (my $pat=0; 1; ) {
+    last if $pat > 196;
+    my $len = int($pat / (6 + $pat/50)) + 4;  $len=20 if $len>20;
+    my ($try, $val, $mask);
+  try:
+    for ($try=0; ; $try++) {
+	next pat if $try>50;
+	$val = 0;
+	for (my $bit=23; $bit>(23-$len); $bit--) {
+	    my $b = int(rand()*2);
+	    $val |= (1<<$bit) if $b;
+	}
+	$mask = (1<<(23-$len+1))-1;
+	for (my $testval = $val; $testval <= ($val + $mask); $testval ++) {
+	    next try if $used[$testval];
+	}
+	last;
+    }
+    my $bits = "";
+    my $val2 = 0;
+    for (my $bit=23; $bit>(23-$len); $bit--) {
+	my $b = ($val & (1<<$bit));
+	$bits .= $b?'1':'0';
+    }
+    for (my $testval = $val; $testval <= ($val + $mask); $testval++) {
+	$used[$testval]= 1; #printf "U%08x\n", $testval;
+    }
+    if ($try<90) {
+	printf +("     24'b%s: {next, len, code} = {in[%02d], 5'd%02d, 32'd%03d};\n"
+		 ,$bits.("?"x(24-$len)), 31-$len, $len, $pat);
+	$pat++;
+    }
+}
+*/
+
+   always @* begin
+      next = 1'b0;
+      code = 32'd0;
+      len  = 5'b11111;
+      casez (in[31:8])
+	24'b1010????????????????????: {next, len, code} = {in[27], 5'd04, 32'd000};
+	24'b1100????????????????????: {next, len, code} = {in[27], 5'd04, 32'd001};
+	24'b0110????????????????????: {next, len, code} = {in[27], 5'd04, 32'd002};
+	24'b1001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd003};
+	24'b1101????????????????????: {next, len, code} = {in[27], 5'd04, 32'd004};
+	24'b0011????????????????????: {next, len, code} = {in[27], 5'd04, 32'd005};
+	24'b0001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd006};
+	24'b10001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd007};
+	24'b01110???????????????????: {next, len, code} = {in[26], 5'd05, 32'd008};
+	24'b01000???????????????????: {next, len, code} = {in[26], 5'd05, 32'd009};
+	24'b00001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd010};
+	24'b11100???????????????????: {next, len, code} = {in[26], 5'd05, 32'd011};
+	24'b01011???????????????????: {next, len, code} = {in[26], 5'd05, 32'd012};
+	24'b100001??????????????????: {next, len, code} = {in[25], 5'd06, 32'd013};
+	24'b111110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd014};
+	24'b010010??????????????????: {next, len, code} = {in[25], 5'd06, 32'd015};
+	24'b001011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd016};
+	24'b101110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd017};
+	24'b111011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd018};
+	24'b0111101?????????????????: {next, len, code} = {in[24], 5'd07, 32'd020};
+	24'b0010100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd021};
+	24'b0111111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd022};
+	24'b1011010?????????????????: {next, len, code} = {in[24], 5'd07, 32'd023};
+	24'b1000000?????????????????: {next, len, code} = {in[24], 5'd07, 32'd024};
+	24'b1011111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd025};
+	24'b1110100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd026};
+	24'b01111100????????????????: {next, len, code} = {in[23], 5'd08, 32'd027};
+	24'b00000110????????????????: {next, len, code} = {in[23], 5'd08, 32'd028};
+	24'b00000101????????????????: {next, len, code} = {in[23], 5'd08, 32'd029};
+	24'b01001100????????????????: {next, len, code} = {in[23], 5'd08, 32'd030};
+	24'b10110110????????????????: {next, len, code} = {in[23], 5'd08, 32'd031};
+	24'b00100110????????????????: {next, len, code} = {in[23], 5'd08, 32'd032};
+	24'b11110010????????????????: {next, len, code} = {in[23], 5'd08, 32'd033};
+	24'b010011101???????????????: {next, len, code} = {in[22], 5'd09, 32'd034};
+	24'b001000000???????????????: {next, len, code} = {in[22], 5'd09, 32'd035};
+	24'b010101111???????????????: {next, len, code} = {in[22], 5'd09, 32'd036};
+	24'b010101010???????????????: {next, len, code} = {in[22], 5'd09, 32'd037};
+	24'b010011011???????????????: {next, len, code} = {in[22], 5'd09, 32'd038};
+	24'b010100011???????????????: {next, len, code} = {in[22], 5'd09, 32'd039};
+	24'b010101000???????????????: {next, len, code} = {in[22], 5'd09, 32'd040};
+	24'b1111010101??????????????: {next, len, code} = {in[21], 5'd10, 32'd041};
+	24'b0010001000??????????????: {next, len, code} = {in[21], 5'd10, 32'd042};
+	24'b0101001101??????????????: {next, len, code} = {in[21], 5'd10, 32'd043};
+	24'b0010010100??????????????: {next, len, code} = {in[21], 5'd10, 32'd044};
+	24'b1011001110??????????????: {next, len, code} = {in[21], 5'd10, 32'd045};
+	24'b1111000011??????????????: {next, len, code} = {in[21], 5'd10, 32'd046};
+	24'b0101000000??????????????: {next, len, code} = {in[21], 5'd10, 32'd047};
+	24'b1111110000??????????????: {next, len, code} = {in[21], 5'd10, 32'd048};
+	24'b10110111010?????????????: {next, len, code} = {in[20], 5'd11, 32'd049};
+	24'b11110000011?????????????: {next, len, code} = {in[20], 5'd11, 32'd050};
+	24'b01001111011?????????????: {next, len, code} = {in[20], 5'd11, 32'd051};
+	24'b00101011011?????????????: {next, len, code} = {in[20], 5'd11, 32'd052};
+	24'b01010010100?????????????: {next, len, code} = {in[20], 5'd11, 32'd053};
+	24'b11110111100?????????????: {next, len, code} = {in[20], 5'd11, 32'd054};
+	24'b00100111001?????????????: {next, len, code} = {in[20], 5'd11, 32'd055};
+	24'b10110001010?????????????: {next, len, code} = {in[20], 5'd11, 32'd056};
+	24'b10000010000?????????????: {next, len, code} = {in[20], 5'd11, 32'd057};
+	24'b111111101100????????????: {next, len, code} = {in[19], 5'd12, 32'd058};
+	24'b100000111110????????????: {next, len, code} = {in[19], 5'd12, 32'd059};
+	24'b100000110010????????????: {next, len, code} = {in[19], 5'd12, 32'd060};
+	24'b100000111001????????????: {next, len, code} = {in[19], 5'd12, 32'd061};
+	24'b010100101111????????????: {next, len, code} = {in[19], 5'd12, 32'd062};
+	24'b001000001100????????????: {next, len, code} = {in[19], 5'd12, 32'd063};
+	24'b000001111111????????????: {next, len, code} = {in[19], 5'd12, 32'd064};
+	24'b011111010100????????????: {next, len, code} = {in[19], 5'd12, 32'd065};
+	24'b1110101111101???????????: {next, len, code} = {in[18], 5'd13, 32'd066};
+	24'b0100110101110???????????: {next, len, code} = {in[18], 5'd13, 32'd067};
+	24'b1111111011011???????????: {next, len, code} = {in[18], 5'd13, 32'd068};
+	24'b0101011011001???????????: {next, len, code} = {in[18], 5'd13, 32'd069};
+	24'b0010000101100???????????: {next, len, code} = {in[18], 5'd13, 32'd070};
+	24'b1111111101101???????????: {next, len, code} = {in[18], 5'd13, 32'd071};
+	24'b1011110010110???????????: {next, len, code} = {in[18], 5'd13, 32'd072};
+	24'b0101010111010???????????: {next, len, code} = {in[18], 5'd13, 32'd073};
+	24'b1111011010010???????????: {next, len, code} = {in[18], 5'd13, 32'd074};
+	24'b01010100100011??????????: {next, len, code} = {in[17], 5'd14, 32'd075};
+	24'b10110000110010??????????: {next, len, code} = {in[17], 5'd14, 32'd076};
+	24'b10111101001111??????????: {next, len, code} = {in[17], 5'd14, 32'd077};
+	24'b10110000010101??????????: {next, len, code} = {in[17], 5'd14, 32'd078};
+	24'b00101011001111??????????: {next, len, code} = {in[17], 5'd14, 32'd079};
+	24'b00100000101100??????????: {next, len, code} = {in[17], 5'd14, 32'd080};
+	24'b11111110010111??????????: {next, len, code} = {in[17], 5'd14, 32'd081};
+	24'b10110010100000??????????: {next, len, code} = {in[17], 5'd14, 32'd082};
+	24'b11101011101000??????????: {next, len, code} = {in[17], 5'd14, 32'd083};
+	24'b01010000011111??????????: {next, len, code} = {in[17], 5'd14, 32'd084};
+	24'b101111011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd085};
+	24'b101111010001100?????????: {next, len, code} = {in[16], 5'd15, 32'd086};
+	24'b100000111100111?????????: {next, len, code} = {in[16], 5'd15, 32'd087};
+	24'b001010101011000?????????: {next, len, code} = {in[16], 5'd15, 32'd088};
+	24'b111111100100001?????????: {next, len, code} = {in[16], 5'd15, 32'd089};
+	24'b001001011000010?????????: {next, len, code} = {in[16], 5'd15, 32'd090};
+	24'b011110011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd091};
+	24'b111111111111010?????????: {next, len, code} = {in[16], 5'd15, 32'd092};
+	24'b101111001010011?????????: {next, len, code} = {in[16], 5'd15, 32'd093};
+	24'b100000110000111?????????: {next, len, code} = {in[16], 5'd15, 32'd094};
+	24'b0010010000000101????????: {next, len, code} = {in[15], 5'd16, 32'd095};
+	24'b0010010010101001????????: {next, len, code} = {in[15], 5'd16, 32'd096};
+	24'b1111011010110010????????: {next, len, code} = {in[15], 5'd16, 32'd097};
+	24'b0010010001100100????????: {next, len, code} = {in[15], 5'd16, 32'd098};
+	24'b0101011101110100????????: {next, len, code} = {in[15], 5'd16, 32'd099};
+	24'b0101011010001111????????: {next, len, code} = {in[15], 5'd16, 32'd100};
+	24'b0010000110011111????????: {next, len, code} = {in[15], 5'd16, 32'd101};
+	24'b0101010010000101????????: {next, len, code} = {in[15], 5'd16, 32'd102};
+	24'b1110101011000000????????: {next, len, code} = {in[15], 5'd16, 32'd103};
+	24'b1111000000110010????????: {next, len, code} = {in[15], 5'd16, 32'd104};
+	24'b0111100010001101????????: {next, len, code} = {in[15], 5'd16, 32'd105};
+	24'b00100010110001100???????: {next, len, code} = {in[14], 5'd17, 32'd106};
+	24'b00100010101101010???????: {next, len, code} = {in[14], 5'd17, 32'd107};
+	24'b11111110111100000???????: {next, len, code} = {in[14], 5'd17, 32'd108};
+	24'b00100000111010000???????: {next, len, code} = {in[14], 5'd17, 32'd109};
+	24'b00100111011101001???????: {next, len, code} = {in[14], 5'd17, 32'd110};
+	24'b11111110111000011???????: {next, len, code} = {in[14], 5'd17, 32'd111};
+	24'b11110001101000100???????: {next, len, code} = {in[14], 5'd17, 32'd112};
+	24'b11101011101011101???????: {next, len, code} = {in[14], 5'd17, 32'd113};
+	24'b01010000100101011???????: {next, len, code} = {in[14], 5'd17, 32'd114};
+	24'b00100100110011001???????: {next, len, code} = {in[14], 5'd17, 32'd115};
+	24'b01001110010101000???????: {next, len, code} = {in[14], 5'd17, 32'd116};
+	24'b010011110101001000??????: {next, len, code} = {in[13], 5'd18, 32'd117};
+	24'b111010101110010010??????: {next, len, code} = {in[13], 5'd18, 32'd118};
+	24'b001001001001111000??????: {next, len, code} = {in[13], 5'd18, 32'd119};
+	24'b101111000110111101??????: {next, len, code} = {in[13], 5'd18, 32'd120};
+	24'b101101111010101001??????: {next, len, code} = {in[13], 5'd18, 32'd121};
+	24'b111101110010111110??????: {next, len, code} = {in[13], 5'd18, 32'd122};
+	24'b010100100011010000??????: {next, len, code} = {in[13], 5'd18, 32'd123};
+	24'b001001001111011001??????: {next, len, code} = {in[13], 5'd18, 32'd124};
+	24'b010100110010001001??????: {next, len, code} = {in[13], 5'd18, 32'd125};
+	24'b111010110000111000??????: {next, len, code} = {in[13], 5'd18, 32'd126};
+	24'b111010110011000101??????: {next, len, code} = {in[13], 5'd18, 32'd127};
+	24'b010100001000111001??????: {next, len, code} = {in[13], 5'd18, 32'd128};
+	24'b1000001011000110100?????: {next, len, code} = {in[12], 5'd19, 32'd129};
+	24'b0010010111001110110?????: {next, len, code} = {in[12], 5'd19, 32'd130};
+	24'b0101011001000001101?????: {next, len, code} = {in[12], 5'd19, 32'd131};
+	24'b0101000010010101011?????: {next, len, code} = {in[12], 5'd19, 32'd132};
+	24'b1111011111101001101?????: {next, len, code} = {in[12], 5'd19, 32'd133};
+	24'b1011001000101010110?????: {next, len, code} = {in[12], 5'd19, 32'd134};
+	24'b1011000001000100001?????: {next, len, code} = {in[12], 5'd19, 32'd135};
+	24'b1110101100010011001?????: {next, len, code} = {in[12], 5'd19, 32'd136};
+	24'b0010010111010111110?????: {next, len, code} = {in[12], 5'd19, 32'd137};
+	24'b0010010001100111100?????: {next, len, code} = {in[12], 5'd19, 32'd138};
+	24'b1011001011100000101?????: {next, len, code} = {in[12], 5'd19, 32'd139};
+	24'b1011000100010100101?????: {next, len, code} = {in[12], 5'd19, 32'd140};
+	24'b1111111001000111011?????: {next, len, code} = {in[12], 5'd19, 32'd141};
+	24'b00100010111101101101????: {next, len, code} = {in[11], 5'd20, 32'd142};
+	24'b10000010101010101101????: {next, len, code} = {in[11], 5'd20, 32'd143};
+	24'b10110010100101001101????: {next, len, code} = {in[11], 5'd20, 32'd144};
+	24'b01010110111100010000????: {next, len, code} = {in[11], 5'd20, 32'd145};
+	24'b10110111110011001001????: {next, len, code} = {in[11], 5'd20, 32'd146};
+	24'b11111101101100100101????: {next, len, code} = {in[11], 5'd20, 32'd147};
+	24'b10110000010100100001????: {next, len, code} = {in[11], 5'd20, 32'd148};
+	24'b10110010011010110110????: {next, len, code} = {in[11], 5'd20, 32'd149};
+	24'b01111001010000011000????: {next, len, code} = {in[11], 5'd20, 32'd150};
+	24'b11110110001011011011????: {next, len, code} = {in[11], 5'd20, 32'd151};
+	24'b01010000100100001011????: {next, len, code} = {in[11], 5'd20, 32'd152};
+	24'b10110001100101110111????: {next, len, code} = {in[11], 5'd20, 32'd153};
+	24'b10111100110111101000????: {next, len, code} = {in[11], 5'd20, 32'd154};
+	24'b01010001010111010000????: {next, len, code} = {in[11], 5'd20, 32'd155};
+	24'b01010100111110001110????: {next, len, code} = {in[11], 5'd20, 32'd156};
+	24'b11111110011001100111????: {next, len, code} = {in[11], 5'd20, 32'd157};
+	24'b11110111111101010001????: {next, len, code} = {in[11], 5'd20, 32'd158};
+	24'b10110000010111100000????: {next, len, code} = {in[11], 5'd20, 32'd159};
+	24'b01001111100001000101????: {next, len, code} = {in[11], 5'd20, 32'd160};
+	24'b01010010000111010110????: {next, len, code} = {in[11], 5'd20, 32'd161};
+	24'b11101010101011101111????: {next, len, code} = {in[11], 5'd20, 32'd162};
+	24'b11111110010011100011????: {next, len, code} = {in[11], 5'd20, 32'd163};
+	24'b01010111001111101111????: {next, len, code} = {in[11], 5'd20, 32'd164};
+	24'b10110001111111111101????: {next, len, code} = {in[11], 5'd20, 32'd165};
+	24'b10110001001100110000????: {next, len, code} = {in[11], 5'd20, 32'd166};
+	24'b11110100011000111101????: {next, len, code} = {in[11], 5'd20, 32'd167};
+	24'b00101011101110100011????: {next, len, code} = {in[11], 5'd20, 32'd168};
+	24'b01010000011011111110????: {next, len, code} = {in[11], 5'd20, 32'd169};
+	24'b00000111000010000010????: {next, len, code} = {in[11], 5'd20, 32'd170};
+	24'b00101010000011001000????: {next, len, code} = {in[11], 5'd20, 32'd171};
+	24'b01001110010100101110????: {next, len, code} = {in[11], 5'd20, 32'd172};
+	24'b11110000000010000000????: {next, len, code} = {in[11], 5'd20, 32'd173};
+	24'b01001101011001111001????: {next, len, code} = {in[11], 5'd20, 32'd174};
+	24'b11110111000111010101????: {next, len, code} = {in[11], 5'd20, 32'd175};
+	24'b01111001101001110110????: {next, len, code} = {in[11], 5'd20, 32'd176};
+	24'b11110000101011101111????: {next, len, code} = {in[11], 5'd20, 32'd177};
+	24'b00100100100110101010????: {next, len, code} = {in[11], 5'd20, 32'd178};
+	24'b11110001011011000011????: {next, len, code} = {in[11], 5'd20, 32'd179};
+	24'b01010111001000110011????: {next, len, code} = {in[11], 5'd20, 32'd180};
+	24'b01111000000100010101????: {next, len, code} = {in[11], 5'd20, 32'd181};
+	24'b00100101101011001101????: {next, len, code} = {in[11], 5'd20, 32'd182};
+	24'b10110010110000111001????: {next, len, code} = {in[11], 5'd20, 32'd183};
+	24'b10110000101010000011????: {next, len, code} = {in[11], 5'd20, 32'd184};
+	24'b00100100111110001101????: {next, len, code} = {in[11], 5'd20, 32'd185};
+	24'b01111001101001101011????: {next, len, code} = {in[11], 5'd20, 32'd186};
+	24'b01010001000000010001????: {next, len, code} = {in[11], 5'd20, 32'd187};
+	24'b11110101111111101110????: {next, len, code} = {in[11], 5'd20, 32'd188};
+	24'b10000010111110110011????: {next, len, code} = {in[11], 5'd20, 32'd189};
+	24'b00000100011110100111????: {next, len, code} = {in[11], 5'd20, 32'd190};
+	24'b11111101001111101100????: {next, len, code} = {in[11], 5'd20, 32'd191};
+	24'b00101011100011110000????: {next, len, code} = {in[11], 5'd20, 32'd192};
+	24'b00100100111001011001????: {next, len, code} = {in[11], 5'd20, 32'd193};
+	24'b10000010101000000100????: {next, len, code} = {in[11], 5'd20, 32'd194};
+	24'b11110001001000111100????: {next, len, code} = {in[11], 5'd20, 32'd195};
+	24'b10111100011010011001????: {next, len, code} = {in[11], 5'd20, 32'd196};
+	24'b000000??????????????????: begin
+	   casez (in[33:32])
+	     2'b1?:   {next, len, code} = {1'b0, 5'd18, 32'd197};
+	     2'b01:   {next, len, code} = {1'b0, 5'd19, 32'd198};
+	     2'b00:   {next, len, code} = {1'b0, 5'd19, 32'd199};
+	     default: ;
+	   endcase
+	end
+	default: ;
+      endcase
+   end
+endmodule

test_regress/t/t_case_default_bad.pl

@@ -1,6 +1,6 @@
 #!/usr/bin/perl
 if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
-# $Id:$
+# $Id$
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can
@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
 '%Error: t/t_case_default_bad.v:\d+: Multiple default statements in case statement.

test_regress/t/t_case_genx_bad.pl

@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
 '%Error: t/t_case_genx_bad.v:\d+: Use of x/\? constant in generate case statement, \(no such thing as \'generate casez\'\)

test_regress/t/t_case_wild.v

@@ -60,6 +60,9 @@ module sub (/*AUTOARG*/
    output reg [4:0]  out2;
 
    always @* begin
+      // Test empty cases
+      casez (in[0])
+      endcase
       casez (in)
 	24'b0000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b0,5'h00};
 	24'b????_????_????_????_????_???1 : {out1,out2} = {1'b1,5'h00};

test_regress/t/t_case_x_bad.pl

@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
 '%Error: t/t_case_x_bad.v:\d+: Use of x/. constant in case statement, \(perhaps intended casex/casez\)

test_regress/t/t_display_bad.pl

@@ -1,6 +1,6 @@
 #!/usr/bin/perl
 if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
-# $Id:$
+# $Id$
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can
@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
 '%Error: t/t_display_bad.v:\d+: Missing arguments for \$display format

test_regress/t/t_flag_werror_bad1.pl

@@ -10,6 +10,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 top_filename("t/t_flag_werror.v");
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>$Last_Self->{v3},
 	 expect=>
 '%Warning-WIDTH: t/t_flag_werror.v:\d+: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS.s CONST generates 6 bits.

test_regress/t/t_flag_werror_bad2.pl

@@ -10,6 +10,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 top_filename("t/t_flag_werror.v");
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>$Last_Self->{v3},
 	 verilator_flags=> [qw(-sp -Werror-WIDTH)],
 	 expect=>

test_regress/t/t_for_count.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -34,6 +34,27 @@ module t (/*AUTOARG*/
       end
    end
 
+   // While loop
+   integer w;
+   initial begin
+      while (w<10) w=w+1;
+      if (w!=10) $stop;
+      while (w<20) begin w=w+2; end
+      while (w<20) begin w=w+99999; end  // NEVER
+      if (w!=20) $stop;
+   end
+
+   // Do-While loop
+   integer dw;
+   initial begin
+      do dw=dw+1; while (dw<10);
+      if (dw!=10) $stop;
+      do dw=dw+2; while (dw<20);
+      if (dw!=20) $stop;
+      do dw=dw+5; while (dw<20);  // Once
+      if (dw!=25) $stop;
+   end
+
    always @ (posedge clk) begin
       cam_lookup_hit_vector <= 0;
       if (cyc!=0) begin
@@ -49,7 +70,7 @@ module t (/*AUTOARG*/
 	    if (hit_count != 32'd5) $stop;
 	    if (wide_for_count != 32'h80) $stop;
 	 end
-	 if (cyc==4) begin
+	 if (cyc==9) begin
 	    $write("*-* All Finished *-*\n");
 	    $finish;
 	 end

test_regress/t/t_func.v

@@ -16,6 +16,7 @@ module t;
       if (add(add(3'd1)) != 3'd3) $stop;
       if (global != 4) $stop;
       if (munge4(4'b0010) != 4'b1011) $stop;
+      if (toint(2) != 3) $stop;
       if (global != 5) $stop;
       setit;
       incr(global,global,32'h10);
@@ -104,4 +105,9 @@ module t;
       nil_func = fa + fb;
    endfunction
 
+   function integer toint;
+      input integer fa;
+      toint = fa + 32'h1;
+   endfunction
+
 endmodule

test_regress/t/t_func_bad.pl

@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
 '%Error: t/t_func_bad.v:\d+: Too few arguments in function call

test_regress/t/t_func_bad2.pl

@@ -1,6 +1,6 @@
 #!/usr/bin/perl
 if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
-# $Id:$
+# $Id$
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_func_bad_width.pl

@@ -1,6 +1,6 @@
 #!/usr/bin/perl
 if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
-# $Id:$
+# $Id$
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can
@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>$Last_Self->{v3},
 	 expect=>
 '%Warning-WIDTH: t/t_func_bad_width.v:\d+: Operator FUNCREF expects 40 bits on the Function Argument, but Function Argument.s VARREF generates 39 bits.

test_regress/t/t_func_crc.pl

@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 verilator_flags2 => ["--compiler msvc"],  # We have deep expressions we want to test
 	 );
 
 execute (

test_regress/t/t_gen_var_bad.pl

@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
 '.*%Error: t/t_gen_var_bad.v:\d+: Non-genvar used in generate for: i

test_regress/t/t_if_deep.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 verilator_flags2 => ["--compiler msvc"],  # We have deep expressions we want to test
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_if_deep.v

@@ -0,0 +1,141 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer 	cyc=0;
+   reg [63:0] 	crc;
+   reg [63:0] 	sum;
+
+   // Take CRC data and apply to testblock inputs
+   wire [31:0]  in = crc[31:0];
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [31:0]		out;			// From test of Test.v
+   // End of automatics
+
+   Test test (/*AUTOINST*/
+	      // Outputs
+	      .out			(out[31:0]),
+	      // Inputs
+	      .clk			(clk),
+	      .in			(in[31:0]));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = {32'h0, out};
+
+   // What checksum will we end up with
+`define EXPECTED_SUM 64'h966e272fd829e672
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+	 // Setup
+	 crc <= 64'h5aef0c8d_d70a4497;
+      end
+      else if (cyc<10) begin
+	 sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 if (sum !== `EXPECTED_SUM) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+endmodule
+
+module Test (/*AUTOARG*/
+   // Outputs
+   out,
+   // Inputs
+   clk, in
+   );
+
+   input clk;
+   input  [31:0] in;   
+   output [31:0] out;
+
+   /*AUTOREG*/
+   // Beginning of automatic regs (for this module's undeclared outputs)
+   reg [31:0]		out;
+   // End of automatics
+
+`ifdef verilator
+ `define dontOptimize $c1("1")
+`else
+ `define dontOptimize 1'b1
+`endif
+
+   always @(posedge clk) begin
+      out <= in;
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+	if (in[0])
+	  out <= ~in;
+   end
+endmodule

test_regress/t/t_inst_array_bad.pl

@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
 '%Error: t/t_inst_array_bad.v:19: Port connection __pinNumber2 as part of a module instance array  requires 1 or 8 bits, but connection\'s VARREF generates 9 bits.

test_regress/t/t_inst_overwide_bad.pl

@@ -1,6 +1,6 @@
 #!/usr/bin/perl
 if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
-# $Id:$
+# $Id$
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2004 by Wilson Snyder. This program is free software; you can
@@ -10,6 +10,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 top_filename("t/t_inst_overwide.v");
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 make_top_shell=>0,
 	 verilator_flags=> [qw(-sp)],
 	 verilator_make_gcc=>0,

test_regress/t/t_inst_sv.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_inst_sv.v

@@ -0,0 +1,75 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+   integer cyc; initial cyc=1;
+
+   supply0 [1:0] low;
+   supply1 [1:0] high;
+
+   reg [7:0] isizedwire;
+   reg ionewire;
+
+   wire oonewire;
+   wire [7:0]		osizedreg;		// From sub of t_inst_v2k_sub.v
+
+   t_inst sub
+     (
+      .osizedreg,
+      .oonewire,
+      // Inputs
+      .isizedwire			(isizedwire[7:0]),
+      .*
+      //.ionewire			(ionewire)
+      );
+
+   always @ (posedge clk) begin
+      if (cyc!=0) begin
+	 cyc <= cyc + 1;
+	 if (cyc==1) begin
+	    ionewire <= 1'b1;
+	    isizedwire <= 8'd8;
+	 end
+	 if (cyc==2) begin
+	    if (low != 2'b00) $stop;
+	    if (high != 2'b11) $stop;
+	    if (oonewire !== 1'b1) $stop;
+	    if (isizedwire !== 8'd8) $stop;
+	 end
+	 if (cyc==3) begin
+	    ionewire <= 1'b0;
+	    isizedwire <= 8'd7;
+	 end
+	 if (cyc==4) begin
+	    if (oonewire !== 1'b0) $stop;
+	    if (isizedwire !== 8'd7) $stop;
+	    $write("*-* All Finished *-*\n");
+	    $finish;
+	 end
+      end
+   end
+endmodule
+
+module t_inst
+  (
+   output reg [7:0] osizedreg,
+   output wire oonewire /*verilator public*/,
+   input [7:0] isizedwire,
+   input wire ionewire
+   );
+
+   assign oonewire = ionewire;
+
+   always @* begin
+      osizedreg = isizedwire;
+   end
+
+endmodule

test_regress/t/t_inst_v2k.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -24,6 +24,8 @@ module t (/*AUTOARG*/
 
    wire [7:0]		osizedreg;		// From sub of t_inst_v2k_sub.v
 
+   hello hsub;
+
    t_inst_v2k_sub sub
      (
       // Outputs
@@ -55,6 +57,10 @@ module t (/*AUTOARG*/
 
 endmodule
 
+module hello;
+   initial $write ("Hello\n");
+endmodule
+
 // Local Variables:
 // compile-command: "./vlint __FILE__"
 // End:

test_regress/t/t_lint_only.pl

@@ -0,0 +1,23 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 make_top_shell => 0,
+	 make_main => 0,
+	 v_flags2 => ["--lint-only"],
+	 verilator_make_gcc => 0,
+	 ) if $Last_Self->{v3};
+
+foreach my $file (glob("obj_dir/*t_lint_only*")) {
+    next if $file =~ /simx_compile.log/;  # Made by driver.pl, not Verilator
+    $Last_Self->error("%Error: Created $file, but --lint-only shouldn't create files");
+}
+
+ok(1);
+1;

test_regress/t/t_lint_only.v

@@ -0,0 +1,11 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2006 by Wilson Snyder.
+
+module t ();
+   initial begin
+      $stop;
+   end
+endmodule

test_regress/t/t_lint_restore_bad.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 v_flags2 => ["--lint-only"],
+	 fails=>1,
+	 expect=>
+'.*%Warning-WIDTH: t/t_lint_restore_bad.v:\d+: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST generates 64 bits.
+%Warning-WIDTH: Use .*
+%Error: Exiting due to.*',
+	 ) if $Last_Self->{v3};
+
+ok(1);
+1;

test_regress/t/t_lint_restore_bad.v

@@ -0,0 +1,23 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t ();
+
+   reg [3:0] four;
+   reg [4:0] five;
+
+   // verilator lint_save
+
+   // verilator lint_off WIDTH
+   initial four = 64'h1;
+
+   // verilator lint_restore
+
+   initial five = 64'h1;
+
+   initial $stop;
+
+endmodule

test_regress/t/t_math_imm.pl

@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 verilator_flags2 => ["--compiler msvc"],  # We have deep expressions we want to test
 	 );
 
 execute (

test_regress/t/t_pp_misdef_bad.pl

@@ -1,6 +1,6 @@
 #!/usr/bin/perl
 if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
-# $Id:$
+# $Id$
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can
@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
 '%Error: t/t_pp_misdef_bad.v:11: Define or directive not defined: `NOTDEF

test_regress/t/t_select_bad_range.pl

@@ -1,6 +1,6 @@
 #!/usr/bin/perl
 if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
-# $Id:$
+# $Id$
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can
@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>$Last_Self->{v3},
 	 expect=>
 '%Error: t/t_select_bad_range.v:\d+: Selection index out of range: 44:44 outside 43:0

test_regress/t/t_var_bad_hide.pl

@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>$Last_Self->{v3},
 	 expect=>
 '%Warning-VARHIDDEN: t/t_var_bad_hide.v:\d+: Declaration of signal hides declaration in upper scope: top

test_regress/t/t_var_dotted.v

@@ -16,6 +16,8 @@ module t (/*AUTOARG*/
    wire [31:0] outb1c0;
    wire [31:0] outb1c1;
 
+   reg [7:0]   lclmem [7:0];
+
    ma ma0 (.outb0c0(outb0c0), .outb0c1(outb0c1),
 	   .outb1c0(outb1c0), .outb1c1(outb1c1)
 	   );
@@ -25,7 +27,6 @@ module t (/*AUTOARG*/
 
    input clk;
    integer cyc=1;
-
    always @ (posedge clk) begin
       cyc <= cyc + 1;
       //$write("[%0t] cyc%0d: %0x %0x %0x %0x\n", $time, cyc, outb0c0, outb0c1, outb1c0, outb1c1);
@@ -45,12 +46,17 @@ module t (/*AUTOARG*/
 	 ma0.mb1.mc1.out <= ma0.mb1.mc1.out + 32'h100;
       end
       if (cyc==4) begin
+	 // Can we do dotted's inside array sels?
+	 ma0.rmtmem[ma0.mb0.mc0.out[2:0]] = 8'h12;
+	 lclmem[ma0.mb0.mc0.out[2:0]] = 8'h24;
 	 if (outb0c0 != 32'h100) $stop;
 	 if (outb0c1 != 32'h101) $stop;
 	 if (outb1c0 != 32'h110) $stop;
 	 if (outb1c1 != 32'h111) $stop;
       end
       if (cyc==5) begin
+	 if (ma0.rmtmem[ma0.mb0.mc0.out[2:0]] != 8'h12) $stop;
+	 if (lclmem[ma0.mb0.mc0.out[2:0]] != 8'h24) $stop;
 	 if (outb0c0 != 32'h1100) $stop;
 	 if (outb0c1 != 32'h2101) $stop;
 	 if (outb1c0 != 32'h2110) $stop;
@@ -97,6 +103,9 @@ module ma (
     output wire [31:0] outb1c1
 	   );
    `INLINE_MODULE
+
+     reg [7:0] rmtmem [7:0];
+
    mb #(0) mb0 (.outc0(outb0c0), .outc1(outb0c1));
    mb #(1) mb1 (.outc0(outb1c0), .outc1(outb1c1));
 endmodule

test_regress/t/t_var_in_assign_bad.pl

@@ -1,6 +1,6 @@
 #!/usr/bin/perl
 if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
-# $Id:$
+# $Id$
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2005 by Wilson Snyder. This program is free software; you can
@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
 '%Error: t/t_var_in_assign_bad.v:\d+: Assigning to input variable: value

test_sc/Makefile_obj

@@ -32,7 +32,7 @@ SC_LIB = $(SYSTEMC)/lib-$(VM_SC_TARGET_ARCH)/libsystemc.a
 
 simx: sc_main.o $(SP_SRCS) \
 	  $(VM_PREFIX)__ALL.a $(SC_LIB)
-	$(CXX) $(LDFLAGS) -g $^ $(LOADLIBES) $(LDLIBS) -o $@ $(SC_LIBS) $(LIBS) 2>&1 | c++filt
+	$(LINK) $(LDFLAGS) -g $^ $(LOADLIBES) $(LDLIBS) -o $@ $(SC_LIBS) $(LIBS) 2>&1 | c++filt
 
 VPATH += ../test_sp
 

test_sp/Makefile_obj

@@ -36,6 +36,6 @@ SC_LIB = $(SYSTEMC)/lib-$(VM_SC_TARGET_ARCH)/libsystemc.a
 
 simx: sc_main.o $(SP_SRCS) \
 	  $(VM_PREFIX)__ALL.a $(SC_LIB)
-	$(CXX) $(LDFLAGS) -g $^ $(LOADLIBES) $(LDLIBS) -o $@ $(SC_LIBS) $(LIBS) 2>&1 | c++filt
+	$(LINK) $(LDFLAGS) -g $^ $(LOADLIBES) $(LDLIBS) -o $@ $(SC_LIBS) $(LIBS) 2>&1 | c++filt
 
 sc_main.o: sc_main.cpp $(VM_PREFIX).h

test_verilated/Makefile_obj

@@ -32,6 +32,6 @@ SP_SRCS = verilated.o
 #SP_SRCS = sp_log.o SpTraceVcd.o
 
 simx: sim_main.o $(SP_SRCS) $(VM_PREFIX)__ALL.a
-	$(CXX) $(LDFLAGS) -g $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) 2>&1 | c++filt
+	$(LINK) $(LDFLAGS) -g $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) 2>&1 | c++filt
 
 sim_main.o: sim_main.cpp $(VM_PREFIX).h