Version bump

git-svn-id: file://localhost/svn/verilator/trunk/verilator@901 77ca24e4-aefa-0310-84f0-b9a241c72d87

Changes

@@ -3,6 +3,40 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilator 3.640 3/12/2007
+
+***  Support Verilog 2005 `begin_keywords and `end_keywords.
+
+***  Updated list of SystemVerilog keywords to correspond to IEEE 1800-2005.
+
+***  Add /*verilator public_flat*/.  [Eugene Weber]
+
+**** Try all +libext's in the exact order given.  [Michael Shinkarovsky]
+
+**** Fix elimination of public signals assigned to constants.  [Eugene Weber]
+
+**** Fix internal error when public for loop has empty body.  [David Addison]
+
+**** Fix "Loops detected" assertion when model exceeds 4GB.  [David Hewson]
+
+**** Fix display %m names inside named blocks.
+
+* Verilator 3.633 2/7/2007
+
+***  Add --trace-depth option for minimizing VCD file size. [Emerson Suguimoto]
+
+***  With VL_DEBUG, show wires causing convergence errors. [Mike Shinkarovsky]
+
+**** Fix isolate_assignments when many signals per always. [Mike Shinkarovsky]
+
+**** Fix isolate_assignments across task/func temporaries. [Mike Shinkarovsky]
+
+**** Fix $display's with array select followed by wide AND.  [David Hewson]
+
+* Verilator 3.632 1/17/2007
+
+***  Add /*verilator isolate_assignments*/ attribute.  [Mike Shinkarovsky]
+
 * Verilator 3.631 1/2/2007
 
 **   Support standard NAME[#] for cells created by arraying or generate for.
@@ -79,7 +113,7 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Removed coverage request variable; see Coverage limitations in docs.
 
-**** Fix DOS carrage returns in multiline defines.  [Ralf Karge]
+**** Fix DOS carriage returns in multiline defines.  [Ralf Karge]
 
 **** Fix printf format warnings on 64-bit linux.
 
@@ -91,7 +125,7 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***  Added --inhibit-sim flag for environments using old __Vm_inhibitSim.
 
-***  Added `systemc_dtor for destructor extentions.  [Allan Cochrane]
+***  Added `systemc_dtor for destructor extensions.  [Allan Cochrane]
 
 ***  Added -MP to make phony dependencies, ala GCC's.
 
@@ -126,7 +160,7 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Fix extraneous UNSIGNED warning when comparing genvars.  [David Hewson]
 
-**** Fix extra whitespace in $display %c.  [by David Addison]
+**** Fix extra white space in $display %c.  [by David Addison]
 
 **** vl_finish and vl_fatal now print via VL_PRINTF rather then cerr/cout.
 
@@ -229,7 +263,7 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Fix functions where regs are declared before inputs.  [Danny Ding]
 
-**** Fix bad deep expressions with bitselects and rotate.  [Prabhat Gupta]
+**** Fix bad deep expressions with bit-selects and rotate.  [Prabhat Gupta]
 
 * Verilator 3.500 10/30/2005 Stable
 

TODO

@@ -47,6 +47,10 @@ Testing:
 	Better graph viewer with search and zoom
 	Port and test against opencores.org code
 
+Usability:
+	Better reporting of unopt problems, including what lines of code
+	Report more errors (all of them?) before exiting [Eugene Weber]	
+
 Performance:
 	Constant propagation
 		Extra cleaning AND:  1 & ((VARREF >> 1) | ((&VARREF >> 1) & VARREF))

bin/verilator

@@ -104,10 +104,11 @@ if ($Opt_Sp) {
 }
 if ($Opt_Sp eq 'sp' || $Opt_Trace) {
     if (!defined $ENV{SYSTEMPERL}) {
-	my $try = "$ENV{W}/hw/utils/perltools/SystemC/src";
+	my $try = "$ENV{W}/hw/utils/perltools/SystemC";
 	$ENV{SYSTEMPERL} = $try if -d $try;
     }
     (defined $ENV{SYSTEMPERL}) or die "%Error: verilator: Need \$SYSTEMPERL in environment for --sp or --trace\nProbably System-Perl isn't installed, see http://www.veripool.com/systemperl.html\n";
+    (-d "$ENV{SYSTEMPERL}/src") or die "%Error: verilator: \$SYSTEMPERL environment var doesn't seem to point to System-Perl kit\n";
 }
 
 # Determine runtime flags
@@ -236,7 +237,7 @@ desired, but other assertions are, use --assert --nopsl.)
 =item --bin I<filename>
 
 Rarely needed.  Override the default filename for Verilator itself.  When a
-dependancy (.d) file is created, this filename will become a source
+dependency (.d) file is created, this filename will become a source
 dependency, such that a change in this binary will have make rebuild the
 output files.
 
@@ -253,7 +254,7 @@ Enables all forms of coverage, alias for --coverage-line, --coverage-user
 Specifies basic block line coverage analysis code should be inserted.
 
 Coverage analysis adds statements at each code flow change point, which are
-the branches of IF and CASE statements, a superset of normal Verilog Line
+the branches of IF and CASE statements, a super-set of normal Verilog Line
 Coverage.  At each such branch a unique counter is incremented.  At the end
 of a test, the counters along with the filename and line number
 corresponding to each counter are written into logs/coverage.pl.
@@ -422,8 +423,8 @@ enable functional coverage.
 
 =item --public
 
-This is only for debug, and may result in mis-simulation of generated
-clocks.
+This is only for historical debug use.  Using it may result in
+mis-simulation of generated clocks.
 
 Declares all signals and modules public.  This will turn off signal
 optimizations as if all signals had a /*verilator public*/ comments and
@@ -449,6 +450,13 @@ Adds waveform tracing code to the model.  Having tracing compiled in may
 result in some small performance losses, even when waveforms are not turned
 on during model execution.
 
+=item --trace-depth I<levels>
+
+Specify the number of levels deep to enable tracing, for example
+--trace-level 1 to only see the top level's signals.  Defaults to the
+entire model.  Using a small number will decrease visibility, but greatly
+improve runtime and trace file size.
+
 =item --underline-zero
 
 Rarely needed.  Signals starting with a underline should be initialized to
@@ -857,7 +865,7 @@ order of magnitude.
 
 =head1 CROSS COMPILATION
 
-Verilator supports cross-compling Verilated code.  This is generally used
+Verilator supports cross-compiling Verilated code.  This is generally used
 to run Verilator on a Linux system and produce C++ code that is then compiled
 on Windows.
 
@@ -883,30 +891,45 @@ The target system may also require edits to the Makefiles, the simple
 Makefiles produced by Verilator presume the target system is the same type
 as the build system.
 
-=head1 VERILOG 2001 SUPPORT
+=head1 VERILOG 2001 (IEEE 1364-2001) SUPPORT
 
 Verilator supports the more common Verilog 2001 language features.  This
 includes signed numbers, "always @*", comma separated sensitivity lists,
 generate statements, multidimensional arrays, localparam, and C-style
 declarations inside port lists.
 
-=head1 SYSTEMVERILOG 3.1 SUPPORT
+=head1 VERILOG 2005 (IEEE 1364-2005) SUPPORT
 
-Verilator currently has very minimal support for SystemVerilog.
+Verilator supports the `begin_keywords and `end_keywords compiler
+directives.
 
-Verilator implement the full SystemVerilog 3.1 preprocessor subset,
-including function call-like preprocessor defines.  Verilator also
-implements $bits, $countones, $isunknown, $onehot, and $onehot0,
-always_comb, always_ff, always_latch, and final.
+Verilator partially supports the uwire keyword.
+
+=head1 SYSTEMVERILOG (IEEE 1800-2005) SUPPORT
+
+Verilator currently has very minimal support for SystemVerilog as they
+become more common, contact the author if a feature you need is missing.
+
+Verilator implements the full SystemVerilog 1800-2005 preprocessor subset,
+including function call-like preprocessor defines.
+
+Verilator supports $bits, $countones, $error, $fatal, $info, $isunknown,
+$onehot, $onehot0, $warning, always_comb, always_ff, always_latch, and
+final.
+
+Verilator partially supports assert.
 
 =head1 SUGAR/PSL SUPPORT
 
-With the --assert switch, Verilator is just beginning to support the
-Property Specification Language (PSL), specifically the simple subset
-without time-branching primitives.  Verilator currently only converts PSL
+Most future work is being directed towards improving SystemVerilog
+assertions instead of PSL.  If you are using these PSL features, please
+contact the author as they may be depreciated in future versions.
+
+With the --assert switch, Verilator enables support of the Property
+Specification Language (PSL), specifically the simple PSL subset without
+time-branching primitives.  Verilator currently only converts PSL
 assertions to simple "if (...) error" statements, and coverage statements
-to increment the line counters described in the coverage section.  If you
-need additional features please contact the author.
+to increment the line counters described in the coverage section.
 
 Verilator implements these keywords: assert, assume (same as assert),
 default (for clocking), countones, cover, isunknown, onehot, onehot0,
@@ -915,18 +938,16 @@ report, true.
 Verilator implements these operators: -> (logical if).
 
 Verilator does not support SEREs yet.  All assertion and coverage
-statements must be simple expressions that complete in one cycle.
-(Arguably SEREs are the whole point of PSL, but one must start somewhere.)
-
-PSL vmode/vprop/vunits are not supported.  PSL statements must be in the
-module they reference, at the module level where you would put an
+statements must be simple expressions that complete in one cycle.  PSL
+vmode/vprop/vunits are not supported.  PSL statements must be in the module
+they reference, at the module level where you would put an
 initial... statement.
 
 Verilator only supports (posedge CLK) or (negedge CLK), where CLK is the
 name of a one bit signal.  You may not use arbitrary expressions as
 assertion clocks.
 
-=head1 SYNTHESIS DIRECTIVE ASSERTIONS
+=head1 SYNTHESIS DIRECTIVE ASSERTION SUPPORT
 
 With the --assert switch, Verilator reads any "//synopsys full_case" or "//
 synopsys parallel_case" directives.  The same applies to any "//cadence" or
@@ -1075,6 +1096,41 @@ submodules will be named I<submodule>__DOT__I<subsignal> as C++ does not
 allow "." in signal names.  SystemPerl when tracing such signals will
 replace the __DOT__ with the period.
 
+=item /*verilator isolate_assignments*/
+
+Used after a signal declaration to indicate the assignments to this signal
+in any blocks should be isolated into new blocks.  When there is a large
+combinatorial block that is resulting in a UNOPTFLAT warning, attaching
+this to the signal causing a false loop may clear up the problem.
+
+IE, with the following
+
+    reg splitme /* verilator isolate_assignments*/;
+    always @* begin
+      if (....) begin
+         splitme = ....;
+         other assignments
+      end
+    end
+
+Verilator will internally split the block that assigns to "splitme" into
+two blocks:
+
+It would then internally break it into (sort of):
+
+    // All assignments excluding those to splitme
+    always @* begin
+      if (....) begin
+         other assignments
+      end
+    end
+    // All assignments to splitme
+    always @* begin
+      if (....) begin
+         splitme = ....;
+      end
+    end
+
 =item /*verilator lint_off I<msg>*/
 
 Disable the specified warning message for any warnings following the comment.
@@ -1091,26 +1147,12 @@ reduce the size of the final executable when a task is used a very large
 number of times.  For this flag to work, the task and tasks below it must
 be pure; they cannot reference any variables outside the task itself.
 
-=item /*verilator sc_clock*/
-
-Used after a input declaration to indicate the signal should be declared in
-SystemC as a sc_clock instead of a bool.
-
-=item /*verilator tracing_off*/
-
-Disable waveform tracing for all future signals that are declared in this
-module.  Often this is placed just after a primitive's module statement, so
-that the entire module is not traced.
-
-=item /*verilator tracing_on*/
-
-Re-enable waveform tracing for all future signals that are declared.
-
 =item /*verilator public*/ (variable)
 
 Used after a input, output, register, or wire declaration to indicate the
 signal should be declared so that C code may read or write the value
-of the signal.
+of the signal.  This will also declare this module public, otherwise use
+/*verilator public_flat*/.
 
 =item /*verilator public*/ (task/function)
 
@@ -1132,6 +1174,14 @@ stored state (flops) should be written, as the model will NOT notice
 changes made to variables in these functions.  (Same as when a signal is
 declared public.)
 
+=item /*verilator public_flat*/ (variable)
+
+Used after a input, output, register, or wire declaration to indicate the
+signal should be declared so that C code may read or write the value of the
+signal.  This will not declare this module public, which means the name of
+the signal or path to it may change based upon the module inlining which
+takes place.
+
 =item /*verilator public_module*/
 
 Used after a module statement to indicate the module should not be inlined
@@ -1140,6 +1190,21 @@ Verilator automatically sets this attribute when the module contains any
 public signals or `systemc_ directives.  Also set for all modules when
 using the --public switch.
 
+=item /*verilator sc_clock*/
+
+Used after a input declaration to indicate the signal should be declared in
+SystemC as a sc_clock instead of a bool.
+
+=item /*verilator tracing_off*/
+
+Disable waveform tracing for all future signals that are declared in this
+module.  Often this is placed just after a primitive's module statement, so
+that the entire module is not traced.
+
+=item /*verilator tracing_on*/
+
+Re-enable waveform tracing for all future signals that are declared.
+
 =back
 
 =head1 LANGUAGE LIMITATIONS
@@ -1237,12 +1302,6 @@ prepended.  (If you don't know what this means, Verilator will do what you
 probably expect -- what C does. The default behavior of Verilog is
 different.)
 
-=head2 Generate Statements
-
-All instantiations and variables in generate blocks will be placed under
-hierarchy that has a name different from that required in the language
-specification.
-
 =head2 Generated Clocks
 
 Verilator attempts to deal with generated clocks correctly, however new
@@ -1297,6 +1356,46 @@ will give a width warning and wrap around the power-of-2 size.  For
 non-power-of-2 sizes, it will return a unspecified constant of the
 appropriate width.
 
+=head2 Assertions
+
+Verilator is beginning to add support for assertions.  Verilator currently
+only converts assertions to simple "if (...) error" statements, and
+coverage statements to increment the line counters described in the
+coverage section.
+
+Verilator does not support SEREs yet.  All assertion and coverage
+statements must be simple expressions that complete in one cycle.
+(Arguably SEREs are much of the point, but one must start somewhere.)
+
+=head1 LANGUAGE KEYWORD LIMITATIONS
+
+This section describes specific limitations for each language keyword.
+
+=over 4
+
+=item always always_comb always_ff always_latch and assign begin buf case
+casex casez default defparam else end endcase endfunction endgenerate
+endmodule endspecify endtask final for function generate genvar if initial
+inout input integer localparam macromodule module nand negedge nor not or
+output parameter posedge reg scalared signed supply0 supply1 task tri
+vectored wire xnor xor
+
+Generally supported.
+
+=item specify specparam
+
+All specify blocks and timing checks are ignored.
+
+=item uwire
+
+Verilator does not perform warning checking on uwires, it treats the uwire
+keyword as if it were the normal wire keyword.
+
+=item $bits, $countones, $finish, $isunknown, $onehot, $onehot0, $readmemb,
+$readmemh, $signed, $stop, $time, $unsigned
+
+Generally supported.
+
 =item $display, $write, $fdisplay, $fwrite
 
 $display and friends must have a constant format string as the first
@@ -1317,12 +1416,23 @@ are 32 bits while FILE*s may be 64 bits, the descriptor must be stored in a
 reg [63:0] rather then an integer.  The define `verilator_file_descriptor in
 verilated.v can be used to hide this difference.
 
+=item $fullskew, $hold, $nochange, $period, $recovery, $recrem, $removal,
+$setup, $setuphold, $skew, $timeskew, $width
+
+All specify blocks and timing checks are ignored.
+
 =item $readmemb, $readmemh
 
 Read memory commands should work properly.  Note Verilator and the Verilog
 specification does not include support for readmem to multi-dimensional
 arrays.
 
+=item $realtime
+
+Treated as $time.
+
+=back
+
 =head1 ERRORS AND WARNINGS
 
 Warnings may be disabled in two ways.  First, when the warning is
@@ -1343,6 +1453,26 @@ List of all warnings:
 
 =over 4
 
+=item BLKANDNBLK
+
+Error that a variable comes from a mix of blocked and non-blocking
+assignments.  Generally, this is caused by a register driven by both combo
+logic and a flop:
+
+      always @ (posedge clk)  foo[0] <= ...
+      always @* foo[1] = ...
+
+Simply use a different register for the flop:
+
+      always @ (posedge clk)  foo_flopped[0] <= ...
+      always @* foo[0] = foo_flopped[0];
+      always @* foo[1] = ...
+
+This is good coding practice anyways.
+
+It is also possible to disable this error when one of the assignments is
+inside a public task.
+
 =item CASEINCOMPLETE
 
 Warns that inside a case statement there is a stimulus pattern for which
@@ -1408,6 +1538,17 @@ Warns that the specified signal comes from multiple always blocks.  This is
 often unsupported by synthesis tools, and is considered bad style.  It will
 also cause longer runtimes due to reduced optimizations.
 
+=item MULTITOP
+
+Error that there are multiple top level modules, that is modules not
+instantiated by any other module.  Verilator only supports a single top
+level, if you need more, create a module that wraps all of the top modules.
+
+Often this error is because some low level cell is being read in, but is
+not really needed.  The best solution is to insure that each module is in a
+unique file by the same name.  Otherwise, make sure all library files are
+read in as libraries with -v, instead of automatically with -y.
+
 =item TASKNSVAR
 
 Error when a call to a task or function has a output from that task tied to
@@ -1495,6 +1636,10 @@ The UNOPTFLAT warning may also be due to clock enables, identified from the
 reported path going through a clock gating cell.  To fix these, use the
 clock_enable meta comment described above.
 
+The UNOPTFLAT warning may also occur where outputs from a block of logic
+are independent, but occur in the same always block.  To fix this, use the
+isolate_assignments meta comment described above.
+
 =item UNSIGNED
 
 Warns that you are comparing a unsigned value in a way that implies it is
@@ -1557,12 +1702,18 @@ For example:
    always @ (b)  a=b
 
 will toggle forever and thus the executable will give the didn't converge
-error to prevent an infinite loop.  To debug this, compile the Verilated
-.cpp files with -DVL_DEBUG, then call Verilated::debug(1) in your main.cpp.
-This will cause each module to print a message when it's invoked.  From
-that it should be obvious what routine(s) are part of the infinite loop.
-Then in Gdb, add a break point at the routine entry point and "print *this"
-on each loop so you can see what variables are changing each invocation.
+error to prevent an infinite loop.
+
+To debug this, run Verilator with --profile-cfuncs.  Run make on the
+generated files with "OPT=-DVL_DEBUG". Then call Verilated::debug(1) in
+your main.cpp.
+
+This will cause each change in a variable to print a message.  Near the
+bottom you'll see the code and variable that causes the problem.  For the
+program above:
+
+        CHANGE: filename.v:1: b
+        CHANGE: filename.v:2: a
 
 =back
 

include/verilated.mk.in

@@ -84,8 +84,8 @@ endif
 ##### SystemPerl builds
 
 ifeq ($(VM_SP),1)
-  CPPFLAGS += -I$(SYSTEMPERL) -I$(SYSTEMPERL)/src -DSYSTEMPERL
-  VPATH    +=   $(SYSTEMPERL)   $(SYSTEMPERL)/src
+  CPPFLAGS += -I$(SYSTEMPERL)/src -DSYSTEMPERL
+  VPATH    +=   $(SYSTEMPERL)/src
 
   VK_CLASSES_SP = $(addsuffix .sp, $(VM_CLASSES))
 
@@ -104,8 +104,8 @@ endif
 ifeq ($(VM_PCLI),1)
   LIBS   += -lm -lstdc++
  ifeq ($(VM_TRACE),1)
-  CPPFLAGS += -I$(SYSTEMPERL) -I$(SYSTEMPERL)/src
-  VPATH    +=   $(SYSTEMPERL)   $(SYSTEMPERL)/src
+  CPPFLAGS += -I$(SYSTEMPERL)/src
+  VPATH    +=   $(SYSTEMPERL)/src
  endif
 endif
 

include/verilatedos.h

@@ -39,6 +39,8 @@
 # define VL_ATTR_UNUSED __attribute__ ((unused))
 # define VL_LIKELY(x)	__builtin_expect(!!(x), 1)
 # define VL_UNLIKELY(x)	__builtin_expect(!!(x), 0)
+# define VL_PREFETCH_RD(p) __builtin_prefetch((p),0)
+# define VL_PREFETCH_RW(p) __builtin_prefetch((p),1)
 #else
 # define VL_ATTR_PRINTF(fmtArgNum)	///< Function with printf format checking
 # define VL_ATTR_ALIGNED(alignment)	///< Align structure to specified byte alignment
@@ -46,6 +48,8 @@
 # define VL_ATTR_UNUSED			///< Function that may be never used
 # define VL_LIKELY(x)	(!!(x))		///< Boolean expression more often true then false
 # define VL_UNLIKELY(x)	(!!(x))		///< Boolean expression more often false then true
+# define VL_PREFETCH_RD(p)		///< Prefetch data with read intent
+# define VL_PREFETCH_RW(p)		///< Prefetch data with read/write intent
 #endif
 
 #ifdef VL_THREADED

nodist/dot_importer

@@ -0,0 +1,174 @@
+#!/usr/bin/perl -w
+# $Id$
+######################################################################
+#
+# Copyright 2005-2007 by Wilson Snyder <[email protected]>.  This
+# program is free software; you can redistribute it and/or modify it under
+# the terms of either the GNU Lesser General Public License or the Perl
+# Artistic License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+######################################################################
+
+require 5.006_001;
+use Getopt::Long;
+use IO::File;
+use Pod::Usage;
+use Data::Dumper; $Data::Dumper::Indent=1;
+use strict;
+use vars qw ($Debug);
+
+#======================================================================
+
+our @Header;
+our %Vertexes;
+our @Edges;
+our %Edges;
+
+#======================================================================
+# main
+
+$Debug = 0;
+my $opt_filename;
+autoflush STDOUT 1;
+autoflush STDERR 1;
+if (! GetOptions (
+		  "help"	=> \&usage,
+		  "debug"	=> \&debug,
+		  "<>"		=> \&parameter,
+		  )) {
+    usage();
+}
+
+dotread ($opt_filename);
+cwrite ("graph_export.cpp");
+
+#----------------------------------------------------------------------
+
+sub usage {
+    print '$Id$ ', "\n";
+    pod2usage(-verbose=>2, -exitval => 2);
+    exit (1);
+}
+
+sub debug {
+    $Debug = 1;
+}
+
+sub parameter {
+    my $param = shift;
+    if (!$opt_filename) {
+	$opt_filename = $param;
+    } else {
+	die "%Error: Unknown parameter: $param\n";
+    }
+}
+
+#######################################################################
+
+sub dotread {
+    my $filename = shift;
+
+    my $fh = IO::File->new($filename) or die "%Error: $! $filename,";
+    my $header = 1;
+    my $vnum = 0;
+    while (defined (my $line = $fh->getline)) {
+	if ($line =~ /^\t([a-zA-Z0-9_]+)\t(.*)$/) {
+	    next if $1 eq 'nTITLE';
+	    $header = 0;
+	    $Vertexes{$1} = {num => $vnum++,
+			     line => $line,
+			     name => $1,};
+	}
+	elsif ($line =~ /^\t([a-zA-Z0-9_]+)\s+->\s+([a-zA-Z0-9_]+)\s+(.*)$/) {
+	    my $from=$1; my $to=$2;
+	    my $weight = 1; $weight = $1 if $line =~ /weight=(\d+)/;
+	    my $cutable = undef; $cutable = $1 if $line =~ /style=(\S+)/;
+	    my $edge =  {num => $vnum++,
+			 line => $line,
+			 weight => $weight,
+			 cutable => $cutable,
+			 from => $from,
+			 to => $to,};
+	    push @Edges, $edge;
+	    $Edges{$from}{$to} = $edge;
+	}
+	elsif ($header) {
+	    push @Header, $line;
+	    print "IGNORE: $line";
+	}
+    }
+}
+
+#######################################################################
+
+sub cwrite {
+    my $filename = shift;
+
+    my $fh = IO::File->new(">$filename") or die "%Error: $! $filename,";
+    $fh->print("void V3GraphTestImport::dotImport() {\n");
+    $fh->print("    DfaGraph* gp = &m_graph;\n");
+    foreach my $ver (sort {$a->{num} <=> $b->{num}} (values %Vertexes)) {
+	$fh->printf("    V3GraphTestVertex* %s = new V3GraphTestVertex(gp, \"%s\");  if (%s) {}\n",
+		    $ver->{name}, $ver->{name}, $ver->{name});
+    }
+    $fh->print("\n");
+    foreach my $edge (@Edges) {
+	$fh->printf("    new V3GraphEdge(gp, %s, %s, %s, %s);\n",
+		    $edge->{from}, $edge->{to},
+		    $edge->{weight}, $edge->{cutable}?"true":"false");	       
+    }
+    $fh->print("}\n");
+}
+
+#######################################################################
+__END__
+
+=pod
+
+=head1 NAME
+
+dot_importer - Take graph .dot file and convert into .cpp file
+
+=head1 SYNOPSIS
+
+  dot_importer a.dot
+
+=head1 DESCRIPTION
+
+Dot_importer takes a graphvis .dot file and converts into .cpp file.  This
+.cpp file is then manually included in V3GraphTest.cpp to verify various
+sub-algorithms.
+
+=head1 ARGUMENTS
+
+=over 4
+
+=item --help
+
+Displays this message and program version and exits.
+
+=back
+
+=head1 DISTRIBUTION
+
+Copyright 2005-2007 by Wilson Snyder.  This package is free software; you
+can redistribute it and/or modify it under the terms of either the GNU
+Lesser General Public License or the Perl Artistic License.
+
+=head1 AUTHORS
+
+Wilson Snyder <[email protected]>
+
+=head1 SEE ALSO
+
+=cut
+
+######################################################################
+### Local Variables:
+### compile-command: "./dot_importer | tee ~/d/a.dot"
+### End:

src/Makefile_obj.in

@@ -156,6 +156,7 @@ RAW_OBJS = \
 	V3Scope.o \
 	V3Signed.o \
 	V3Split.o \
+	V3SplitAs.o \
 	V3Stats.o \
 	V3StatsReport.o \
 	V3Subst.o \

src/V3Assert.cpp

@@ -47,28 +47,58 @@ private:
     V3Double0	m_statAsCover;	// Statistic tracking
     V3Double0	m_statAsPsl;	// Statistic tracking
     V3Double0	m_statAsFull;	// Statistic tracking
+    V3Double0	m_statAsSV;	// Statistic tracking
 
     // METHODS
-    AstNode* newFireAssert(AstNode* nodep, const string& message) {
-	AstNode* bodysp = new AstDisplay
-	    (nodep->fileline(), '\0',
-	     (string("[%0t] %%Error: ")+nodep->fileline()->filebasename()
-	      +":"+cvtToStr(nodep->fileline()->lineno())
-	      +": Assertion failed in %m"
-	      +((message != "")?": ":"")+message
-	      +"\\n"),
-	     NULL,
-	     new AstTime(nodep->fileline()));
-	bodysp->addNext(new AstStop (nodep->fileline()));
+    string assertDisplayMessage(AstNode* nodep, const string& prefix, const string& message) {
+	return (string("[%0t] "+prefix+": ")+nodep->fileline()->filebasename()
+		+":"+cvtToStr(nodep->fileline()->lineno())
+		+": Assertion failed in %m"
+		+((message != "")?": ":"")+message
+		+"\\n");
+    }
+    void replaceDisplay(AstDisplay* nodep, const string& prefix) {
+	nodep->displayType(AstDisplayType::WRITE);
+	nodep->text(assertDisplayMessage(nodep, prefix, nodep->text()));
+	AstNode* timesp = nodep->exprsp(); if (timesp) timesp->unlinkFrBack();
+	timesp = timesp->addNext(new AstTime(nodep->fileline()));
+	nodep->exprsp(timesp);
+    }
+
+    AstNode* newIfAssertOn(AstNode* nodep) {
 	// Add a internal if to check assertions are on.
 	// Don't make this a AND term, as it's unlikely to need to test this.
-	bodysp = new AstIf (nodep->fileline(),
-			    new AstCMath(nodep->fileline(), "Verilated::assertOn()", 1),
-			    bodysp, NULL);
+	return new AstIf (nodep->fileline(),
+			  // If assertions are off, have constant propagation rip them out later
+			  // This allows syntax errors and such to be detected normally.
+			  (v3Global.opt.assertOn()
+			   ? (AstNode*)(new AstCMath(nodep->fileline(), "Verilated::assertOn()", 1))
+			   : (AstNode*)(new AstConst(nodep->fileline(), V3Number(nodep->fileline(), 1, 0)))),
+			  nodep, NULL);
+    }
+
+    AstNode* newIfCoverageOn(AstNode* nodep) {
+	// Add a internal if to check coverage is on
+	// Don't make this a AND term, as it's unlikely to need to test this.
+	return new AstIf (nodep->fileline(),
+			  // If assertions are off, have constant propagation rip them out later
+			  // This allows syntax errors and such to be detected normally.
+			  (v3Global.opt.coverage()
+			   ? (AstNode*)(new AstConst(nodep->fileline(), V3Number(nodep->fileline(), 1, 1)))
+			   : (AstNode*)(new AstConst(nodep->fileline(), V3Number(nodep->fileline(), 1, 0)))),
+			  nodep, NULL);
+    }
+
+    AstNode* newFireAssert(AstNode* nodep, const string& message) {
+	AstDisplay* dispp = new AstDisplay (nodep->fileline(), AstDisplayType::ERROR, message, NULL, NULL);
+	AstNode* bodysp = dispp;
+	replaceDisplay(dispp, "%%Error");   // Convert to standard DISPLAY format
+	bodysp->addNext(new AstStop (nodep->fileline()));
+	bodysp = newIfAssertOn(bodysp);
 	return bodysp;
     }
 
-    void newAssertion(AstNode* nodep, AstNode* propp, AstSenTree* sentreep, const string& message) {
+    void newPslAssertion(AstNode* nodep, AstNode* propp, AstSenTree* sentreep, const string& message) {
 	propp->unlinkFrBack();
 	sentreep->unlinkFrBack();
 	//
@@ -114,6 +144,28 @@ private:
 	pushDeletep(nodep); nodep=NULL;
     }
 
+    void newVAssertion(AstVAssert* nodep, AstNode* propp) {
+	propp->unlinkFrBackWithNext();
+	AstNode* passsp = nodep->passsp(); if (passsp) passsp->unlinkFrBackWithNext();
+	AstNode* failsp = nodep->failsp(); if (failsp) failsp->unlinkFrBackWithNext();
+	//
+	if (nodep->castVAssert()) {
+	    if (passsp) passsp = newIfAssertOn(passsp);
+	    if (failsp) failsp = newIfAssertOn(failsp);
+	} else {
+	    nodep->v3fatalSrc("Unknown node type");
+	}
+
+	AstIf* ifp = new AstIf (nodep->fileline(), propp, passsp, failsp);
+	AstNode* newp = ifp;
+	if (nodep->castVAssert()) ifp->branchPred(AstBranchPred::UNLIKELY);
+	//
+	// Install it
+	nodep->replaceWith(newp);
+	// Bye
+	pushDeletep(nodep); nodep=NULL;
+    }
+
     // VISITORS  //========== Case assertions
     virtual void visit(AstCase* nodep, AstNUser*) {
 	nodep->iterateChildren(*this);
@@ -163,16 +215,34 @@ private:
     }
 
     // VISITORS  //========== Statements
+    virtual void visit(AstDisplay* nodep, AstNUser*) {
+	nodep->iterateChildren(*this);
+	// Replace the special types with standard text
+	if (nodep->displayType()==AstDisplayType::INFO) {
+	    replaceDisplay(nodep, "-Info");
+	} else if (nodep->displayType()==AstDisplayType::WARNING) {
+	    replaceDisplay(nodep, "%%Warning");
+	} else if (nodep->displayType()==AstDisplayType::ERROR
+		   || nodep->displayType()==AstDisplayType::FATAL) {
+	    replaceDisplay(nodep, "%%Error");
+	}
+    }
+
     virtual void visit(AstPslCover* nodep, AstNUser*) {
 	nodep->iterateChildren(*this);
-	newAssertion(nodep, nodep->propp(), nodep->sentreep(), nodep->name()); nodep=NULL;
+	newPslAssertion(nodep, nodep->propp(), nodep->sentreep(), nodep->name()); nodep=NULL;
 	m_statAsCover++;
     }
     virtual void visit(AstPslAssert* nodep, AstNUser*) {
 	nodep->iterateChildren(*this);
-	newAssertion(nodep, nodep->propp(), nodep->sentreep(), nodep->name()); nodep=NULL;
+	newPslAssertion(nodep, nodep->propp(), nodep->sentreep(), nodep->name()); nodep=NULL;
 	m_statAsPsl++;
     }
+    virtual void visit(AstVAssert* nodep, AstNUser*) {
+	nodep->iterateChildren(*this);
+	newVAssertion(nodep, nodep->propp()); nodep=NULL;
+	m_statAsSV++;
+    }
 
     virtual void visit(AstModule* nodep, AstNUser*) {
 	m_modp = nodep;
@@ -203,6 +273,7 @@ public:
     }
     virtual ~AssertVisitor() {
 	V3Stats::addStat("Assertions, PSL asserts", m_statAsPsl);
+	V3Stats::addStat("Assertions, SystemVerilog asserts", m_statAsSV);
 	V3Stats::addStat("Assertions, cover statements", m_statAsCover);
 	V3Stats::addStat("Assertions, full/parallel case", m_statAsFull);
     }

src/V3Ast.cpp

@@ -789,7 +789,7 @@ void AstNode::dumpTreeFile(const string& filename, bool append) {
 	    if (logsp->fail()) v3fatalSrc("Can't write "<<filename);
 	    *logsp<<"Tree Dump from <e"<<dec<<editCountLast()<<">";
 	    *logsp<<" to <e"<<dec<<editCountGbl()<<">"<<endl;
-	    if (editCountGbl()==editCountLast() && 0) {  // Off, as messes up tree diffing
+	    if (editCountGbl()==editCountLast() && 1) {  // Off, as messes up tree diffing
 		*logsp<<endl;
 		*logsp<<"No changes since last dump!\n";
 	    } else {

src/V3Ast.h

@@ -250,6 +250,34 @@ public:
 
 //######################################################################
 
+class AstDisplayType {
+public:
+    enum en {
+	DISPLAY,
+	WRITE,
+	INFO,
+	ERROR,
+	WARNING,
+	FATAL
+    };
+    enum en m_e;
+    inline AstDisplayType () {};
+    inline AstDisplayType (en _e) : m_e(_e) {};
+    explicit inline AstDisplayType (int _e) : m_e(static_cast<en>(_e)) {};
+    operator en () const { return m_e; };
+    bool addNewline() const { return m_e!=WRITE; }
+    bool needScopeTracking() const { return m_e!=DISPLAY && m_e!=WRITE; }
+    const char* ascii() const {
+	static const char* names[] = {
+	    "display","write","info","error","warning","fatal"};
+	return names[m_e];};
+  };
+  inline bool operator== (AstDisplayType lhs, AstDisplayType rhs) { return (lhs.m_e == rhs.m_e); }
+  inline bool operator== (AstDisplayType lhs, AstDisplayType::en rhs) { return (lhs.m_e == rhs); }
+  inline bool operator== (AstDisplayType::en lhs, AstDisplayType rhs) { return (lhs == rhs.m_e); }
+
+//######################################################################
+
 class AstParseRefExp {
 public:
     enum en {
@@ -505,6 +533,7 @@ public:
     AstNode*	op3p() const { return m_op3p; }
     AstNode*	op4p() const { return m_op4p; }
     AstNode*	clonep() const { return ((m_cloneCnt==s_cloneCntGbl)?m_clonep:NULL); }
+    AstNode*	firstAbovep() const { return ((backp() && backp()->nextp()!=this) ? backp() : NULL); }  // Returns NULL when second or later in list
     bool	brokeExists() const;
 
     // CONSTRUCTORS
@@ -905,6 +934,7 @@ public:
     virtual ~AstNodePli() {}
     virtual string name()	const { return m_text; }
     virtual int instrCount()	const { return instrCountPli(); }
+    void exprsp(AstNode* nodep)	{ addOp1p(nodep); }	// op1 = Expressions to output
     AstNode* exprsp()		const { return op1p()->castNode(); }	// op1 = Expressions to output
     string 	text()		const { return m_text; }		// * = Text to display
     void text(const string& text) { m_text=text; }

src/V3AstNodes.cpp

@@ -350,6 +350,7 @@ void AstVar::dump(ostream& str) {
     if (isUsedClock()) str<<" [C]";
     if (isSigPublic()) str<<" [P]";
     if (attrClockEn()) str<<" [aCLKEN]";
+    if (attrIsolateAssign()) str<<" [aISO]";
     if (attrFileDescr()) str<<" [aFD]";
     if (isFuncReturn()) str<<" [FUNCRTN]";
     else if (isFuncLocal()) str<<" [FUNC]";

src/V3AstNodes.h

@@ -236,11 +236,13 @@ private:
     bool	m_scClocked:1;	// SystemC sc_clk<> needed
     bool	m_scSensitive:1;// SystemC sensitive() needed
     bool	m_sigPublic:1;	// User C code accesses this signal
+    bool	m_sigModPublic:1;// User C code accesses this signal and module
     bool	m_usedClock:1;	// Signal used as a clock
     bool	m_usedParam:1;	// Parameter is referenced (on link; later signals not setup)
     bool	m_funcLocal:1;	// Local variable for a function
     bool	m_funcReturn:1;	// Return variable for a function
     bool	m_attrClockEn:1;// User clock enable attribute
+    bool	m_attrIsolateAssign:1;// User isolate_assignments attribute
     bool	m_fileDescr:1;	// File descriptor
     bool	m_isConst:1;	// Table contains constant data
     bool	m_isStatic:1;	// Static variable
@@ -251,8 +253,10 @@ private:
 	m_primaryIO=false;
 	m_sc=false; m_scClocked=false; m_scSensitive=false;
 	m_usedClock=false; m_usedParam=false;
-	m_sigPublic=false; m_funcLocal=false; m_funcReturn=false; 
-	m_attrClockEn=false; m_fileDescr=false; m_isConst=false; m_isStatic=false;
+	m_sigPublic=false; m_sigModPublic=false;
+	m_funcLocal=false; m_funcReturn=false; 
+	m_attrClockEn=false; m_attrIsolateAssign=false;
+	m_fileDescr=false; m_isConst=false; m_isStatic=false;
 	m_trace=false;
     }
 public:
@@ -301,9 +305,11 @@ public:
     void	attrClockEn(bool flag) { m_attrClockEn = flag; }
     void	attrFileDescr(bool flag) { m_fileDescr = flag; }
     void	attrScClocked(bool flag) { m_scClocked = flag; }
+    void	attrIsolateAssign(bool flag) { m_attrIsolateAssign = flag; }
     void	usedClock(bool flag) { m_usedClock = flag; }
     void	usedParam(bool flag) { m_usedParam = flag; }
     void	sigPublic(bool flag) { m_sigPublic = flag; }
+    void	sigModPublic(bool flag) { m_sigModPublic = flag; }
     void	sc(bool flag) { m_sc = flag; }
     void	scSensitive(bool flag) { m_scSensitive = flag; }
     void	primaryIO(bool flag) { m_primaryIO = flag; }
@@ -340,6 +346,7 @@ public:
     bool	isScWide() const;
     bool	isScSensitive() const { return m_scSensitive; }
     bool	isSigPublic()  const;
+    bool	isSigModPublic() const { return m_sigModPublic; }
     bool	isTrace() const { return m_trace; }
     bool	isConst() const { return m_isConst; }
     bool	isStatic() const { return m_isStatic; }
@@ -348,6 +355,7 @@ public:
     bool	attrClockEn() const { return m_attrClockEn; }
     bool	attrFileDescr() const { return m_fileDescr; }
     bool	attrScClocked() const { return m_scClocked; }
+    bool	attrIsolateAssign() const { return m_attrIsolateAssign; }
     int		widthAlignBytes() const;	// Structure alignment 1,2,4 or 8 bytes (arrays affect this)
     int		widthTotalBytes() const;	// Width in bytes rounding up 1,2,4,8,12,...
     uint32_t	msb() const { if (!rangep()) return 0; return rangep()->msbConst(); }
@@ -359,6 +367,7 @@ public:
 	// Note the method below too
 	if (fromp->attrClockEn()) attrClockEn(true);
 	if (fromp->attrFileDescr()) attrFileDescr(true);
+	if (fromp->attrIsolateAssign()) attrIsolateAssign(true);
     }
     bool	gateMultiInputOptimizable() const {
 	// Ok to gate optimize; must return false if propagateAttrFrom would do anything
@@ -369,6 +378,7 @@ public:
 	propagateAttrFrom(typevarp);
 	combineType(typevarp->varType());
 	if (typevarp->isSigPublic()) sigPublic(true);
+	if (typevarp->isSigModPublic()) sigModPublic(true);
 	if (typevarp->attrScClocked()) attrScClocked(true);
     }
     void	inlineAttrReset(const string& name) {
@@ -809,10 +819,13 @@ struct AstTask : public AstNodeFTask {
 };
 
 struct AstFunc : public AstNodeFTask {
+    bool	m_attrIsolateAssign:1;// User isolate_assignments attribute
+public:
     // A function inside a module
     AstFunc(FileLine* fl, const string& name, AstNode* stmtp, AstNode* fvarsp)
 	:AstNodeFTask(fl, name, stmtp) {
 	addNOp1p(fvarsp);
+	m_attrIsolateAssign = false;
     }
     virtual ~AstFunc() {}
     virtual AstType type() const { return AstType::FUNC;}
@@ -821,6 +834,8 @@ struct AstFunc : public AstNodeFTask {
     // op1 = Range output variable (functions only)
     AstNode*	fvarp() 	const { return op1p()->castNode(); }
     void addFvarp(AstNode* nodep) { addOp1p(nodep); }
+    void	attrIsolateAssign(bool flag) { m_attrIsolateAssign = flag; }
+    bool	attrIsolateAssign() const { return m_attrIsolateAssign; }
 };
 
 struct AstTaskRef : public AstNodeFTaskRef {
@@ -1221,19 +1236,19 @@ struct AstDisplay : public AstNodePli {
     // Parents: stmtlist
     // Children: file which must be a varref, MATH to print
 private:
-    char	m_newline;
+    AstDisplayType	m_displayType;
 public:
-    AstDisplay(FileLine* fileline, char newln, const string& text, AstNode* filep, AstNode* exprsp)
+    AstDisplay(FileLine* fileline, AstDisplayType dispType, const string& text, AstNode* filep, AstNode* exprsp)
 	: AstNodePli (fileline, text, exprsp) {
 	setNOp2p(filep);
-	m_newline = newln;
+	m_displayType = dispType;
     }
     virtual ~AstDisplay() {}
     virtual AstType type() const { return AstType::DISPLAY;}
     virtual AstNode* clone() { return new AstDisplay(*this); }
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
-    virtual string verilogKwd() const { return (filep() ? ((newline() == '\n')?"$fdisplay":"$fwrite")
-						: ((newline() == '\n')?"$display":"$write")); };
+    virtual string verilogKwd() const { return (filep() ? (string)"$f"+(string)displayType().ascii()
+						: (string)"$"+(string)displayType().ascii()); }
     virtual bool isGateOptimizable() const { return false; }
     virtual bool isPredictOptimizable() const { return false; }
     virtual bool isSplittable() const { return false; }	// SPECIAL: $display has 'visual' ordering
@@ -1241,15 +1256,19 @@ public:
     virtual bool isUnlikely() const { return true; }
     virtual V3Hash sameHash() const { return V3Hash(text()); }
     virtual bool same(AstNode* samep) const {
-	return newline()==samep->castDisplay()->newline()
+	return displayType()==samep->castDisplay()->displayType()
 	    && text()==samep->castDisplay()->text(); }
     // op1 used by AstNodePli
-    char	newline()	const { return m_newline; }		// * = Add a newline for $display
+    AstDisplayType	displayType()	const { return m_displayType; }
+    void	displayType(AstDisplayType type) { m_displayType = type; }
+    bool	addNewline() const { return displayType().addNewline(); }  // * = Add a newline for $display
     AstNode*	filep() const { return op2p(); }
     void 	filep(AstNodeVarRef* nodep) { setNOp2p(nodep); }
     AstNode*	scopeAttrp() const { return op3p(); }
     AstText*	scopeTextp() const { return op3p()->castText(); }
     void scopeAttrp(AstNode* nodep) { addOp3p(nodep); }
+    bool	needScopeTracking() { return (displayType().needScopeTracking()
+					      || name().find("%m") != string::npos); }
 };
 
 struct AstFClose : public AstNodeStmt {
@@ -2601,6 +2620,30 @@ struct AstReplicate : public AstNodeBiop {
     virtual int instrCount()	const { return widthInstrs()*2; }
 };
 
+//======================================================================
+// SysVerilog assertions
+
+struct AstVAssert : public AstNodeStmt {
+    // Verilog Assertion
+    // Parents:  {statement list}
+    // Children: expression, if pass statements, if fail statements
+    AstVAssert(FileLine* fl, AstNode* propp, AstNode* passsp, AstNode* failsp)
+	: AstNodeStmt(fl) {
+	addOp1p(propp);
+	addNOp2p(passsp);
+	addNOp3p(failsp);
+    }
+    virtual ~AstVAssert() {}
+    virtual AstType type() const { return AstType::VASSERT;}
+    virtual AstNode* clone() { return new AstVAssert(*this); }
+    virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
+    virtual V3Hash sameHash() const { return V3Hash(); }
+    virtual bool same(AstNode* samep) const { return true; }
+    AstNode*	propp()		const { return op1p(); }	// op1 = property
+    AstNode*	passsp()	const { return op2p(); }	// op2 = if passes
+    AstNode*	failsp()	const { return op3p(); }	// op3 = if fails
+};
+
 //======================================================================
 // PSL
 

src/V3Begin.cpp

@@ -131,6 +131,18 @@ private:
 	nodep->replaceWith(newp);
 	nodep->deleteTree(); nodep=NULL;
     }
+    virtual void visit(AstDisplay* nodep, AstNUser*) {
+	// If there's a %m in the display text, we add a special node that will contain the name()
+	// Similar code in V3Inline
+	if (m_beginScope != "" && nodep->needScopeTracking()) {
+	    // To keep correct visual order, must add before other Text's
+	    AstNode* afterp = nodep->scopeAttrp();
+	    if (afterp) afterp->unlinkFrBackWithNext();
+	    nodep->scopeAttrp(new AstText(nodep->fileline(), (string)"."+AstNode::prettyName(m_beginScope)));
+	    if (afterp) nodep->scopeAttrp(afterp);
+	}
+	nodep->iterateChildren(*this);
+    }
     virtual void visit(AstNode* nodep, AstNUser*) {
 	nodep->iterateChildren(*this);
     }

src/V3Clean.cpp

@@ -104,11 +104,8 @@ private:
 	nodep->unlinkFrBack(&relinkHandle);
 	//
 	computeCppWidth(nodep);
-	V3Number zero (nodep->fileline(), nodep->widthMin(),0);
-	V3Number masksmall (nodep->fileline(), nodep->widthMin());
-	masksmall.opNot(zero);
 	V3Number mask (nodep->fileline(), cppWidth(nodep));
-	mask.opAssign(masksmall);
+	mask.setMask(nodep->widthMin());
 	AstNode* cleanp = new AstAnd (nodep->fileline(),
 				      new AstConst (nodep->fileline(), mask),
 				      nodep);

src/V3Clock.cpp

@@ -472,7 +472,8 @@ private:
 	ifstmtp->addNext(new AstIf(fl,
 				   new AstLt (fl, new AstConst(fl, 100),
 					      new AstVarRef(fl, countVarp, false)),
-				   (new AstDisplay (fl, '\n', "%%Error: Verilated model didn't converge", NULL, NULL))
+				   (new AstDisplay (fl, AstDisplayType::DISPLAY,
+						    "%%Error: Verilated model didn't converge", NULL, NULL))
 				   ->addNext(new AstStop (fl)),
 				   NULL));
 	untilp->addBodysp(new AstIf(fl, new AstNeq(fl, new AstConst(fl, 0),

src/V3Const.cpp

@@ -246,9 +246,8 @@ private:
 	replaceNum(nodep, 0); nodep=NULL;
     }
     void replaceAllOnes (AstNode* nodep) {
-	V3Number num (nodep->fileline(), nodep->width(), 0);
-	V3Number ones (nodep->fileline(), nodep->width());
-	ones.opNot(num);
+	V3Number ones (nodep->fileline(), nodep->width(), 0);
+	ones.setMask(nodep->width());
 	replaceNum(nodep, ones); nodep=NULL;
     }
     void replaceConst(AstNodeUniop* nodep) {
@@ -388,7 +387,7 @@ private:
 	    AstNode* newp;
 	    V3Number mask1 (nodep->fileline(), nodep->width());
 	    V3Number ones (nodep->fileline(), nodep->width());
-	    ones.opNot(mask1);
+	    ones.setMask(nodep->width());
 	    if (shift1<0) {
 		mask1.opShiftR(ones,V3Number(nodep->fileline(),VL_WORDSIZE,-shift1));
 	    } else {
@@ -757,7 +756,8 @@ private:
 	    nodep->varp()->initp()->iterateAndNext(*this);
 	    if (operandConst(nodep->varp()->initp())
 		&& !nodep->lvalue()
-		&& ((v3Global.opt.oConst() && !m_params) // Can reduce constant wires into equations
+		&& ((v3Global.opt.oConst() && !m_params // Can reduce constant wires into equations
+		     && !nodep->varp()->isSigPublic())
 		    || nodep->varp()->isParam())) {
 		AstConst* constp = nodep->varp()->initp()->castConst();
 		const V3Number& num = constp->num();

src/V3Descope.cpp

@@ -160,8 +160,8 @@ private:
 		    }
 		}
 		// Not really any way the user could do this, and we'd need to come up with some return value
-		//newfuncp->addStmtsp(new AstDisplay (newfuncp->fileline(),
-		//				    '\n', string("%%Error: ")+name+"() called with bad scope", NULL));
+		//newfuncp->addStmtsp(new AstDisplay (newfuncp->fileline(), AstDisplayType::DISPLAY,
+		//				      string("%%Error: ")+name+"() called with bad scope", NULL));
 		//newfuncp->addStmtsp(new AstStop (newfuncp->fileline()));
 		if (debug()>=9) newfuncp->dumpTree(cout,"   newfunc: ");
 	    } else {

src/V3EmitC.cpp

@@ -687,6 +687,21 @@ class EmitCImp : EmitCStmts {
 	if (gotOne) {
 	    puts(");\n");
 	    //puts("VL_DEBUG_IF( if (__req) cout<<\"\tCLOCKREQ );");
+	    for (vector<AstChangeDet*>::iterator it = m_blkChangeDetVec.begin();
+		 it != m_blkChangeDetVec.end(); ++it) {
+		AstChangeDet* nodep = *it;
+		if (nodep->lhsp()) {
+		    puts("VL_DEBUG_IF( if(__req && (");
+		    bool gotOneIgnore = false;
+		    doubleOrDetect(nodep, gotOneIgnore);
+		    string varname;
+		    if (nodep->lhsp()->castVarRef()) {
+			varname = ": "+nodep->lhsp()->castVarRef()->varp()->prettyName();
+		    }
+		    puts(")) cout<<\"\tCHANGE: "+nodep->fileline()->ascii()
+			 +varname+"\"<<endl; );");
+		}
+	    }
 	}
     }
 
@@ -998,7 +1013,6 @@ void EmitCStmts::displayArg(AstDisplay* dispp, AstNode** elistp, string fmt, cha
 
 void EmitCStmts::visit(AstDisplay* nodep, AstNUser*) {
     string vformat = nodep->text();
-    bool addNewline = (nodep->newline() == '\n');
     AstNode* elistp = nodep->exprsp();
 
     // Convert Verilog display to C printf formats
@@ -1061,7 +1075,7 @@ void EmitCStmts::visit(AstDisplay* nodep, AstNUser*) {
     if (elistp != NULL) {
 	nodep->v3error("Extra arguments for $display format\n");
     }
-    if (addNewline) emitDispState.pushFormat("\\n");
+    if (nodep->addNewline()) emitDispState.pushFormat("\\n");
     displayEmit(nodep);
 }
 

src/V3Error.h

@@ -37,6 +37,7 @@ public:
 	FATAL,		// Kill the program
 	ERROR,		// General error out, can't suppress
 	// Error codes:
+	MULTITOP,	// Error: Multiple top level modules
 	TASKNSVAR,	// Error: Task I/O not simple
 	// Warning codes:
 	FIRST_WARN,	// Just a code so the program knows where to start warnings
@@ -71,7 +72,7 @@ public:
 	const char* names[] = {
 	    // Leading spaces indicate it can't be disabled.
 	    " SUPPRESS", " FATAL", " ERROR",
-	    "TASKNSVAR",
+	     "MULTITOP", "TASKNSVAR",
 	    " FIRST_WARN",
 	    "BLKANDNBLK",
 	    "CASEINCOMPLETE", "CASEOVERLAP", "CASEX", "CMPCONST",

src/V3Expand.cpp

@@ -65,11 +65,8 @@ private:
 	if (nodep->isWide()) {
 	    return V3Number (nodep->fileline(), VL_WORDSIZE, VL_MASK_I(nodep->widthMin()));
 	} else {
-	    V3Number zero (nodep->fileline(), nodep->widthMin(),0);
-	    V3Number masksmall (nodep->fileline(), nodep->widthMin());
-	    masksmall.opNot(zero);
 	    V3Number mask (nodep->fileline(), longOrQuadWidth(nodep));
-	    mask.opAssign(masksmall);
+	    mask.setMask(nodep->widthMin());
 	    return mask;
 	}
     }

src/V3Gate.cpp

@@ -198,10 +198,18 @@ public:
 	m_substTreep = NULL;
 	m_buffersOnly = buffersOnly;
 	m_lhsVarRef = NULL;
+	// Iterate
 	nodep->accept(*this);
+	// Check results
 	if (!m_substTreep) {
 	    clearSimple("No assignment found\n");
 	}
+	for (GateVarRefList::const_iterator it = rhsVarRefs().begin();
+	     it != rhsVarRefs().end(); ++it) {
+	    if (m_lhsVarRef && m_lhsVarRef->varScopep() == (*it)->varScopep()) {
+		clearSimple("Circular logic\n");  // Oh my, we'll get a UNOPTFLAT much later.
+	    }
+	}
 	if (debug()>=9 && !m_isSimple) {
 	    nodep->dumpTree(cout,"\tgate!Ok: ");
 	}
@@ -224,6 +232,7 @@ private:
     //Entire netlist:
     // AstVarScope::userp	-> GateVarVertex* for usage var, 0=not set yet
     // {statement}Node::userp	-> GateLogicVertex* for this statement
+
     // STATE
     V3Graph		m_graph;	// Scoreboard of var usages/dependencies
     GateLogicVertex*	m_logicVertexp;	// Current statement being tracked, NULL=ignored
@@ -458,6 +467,7 @@ void GateVisitor::optimizeSignals(bool allowMultiIn) {
 			    }
 			}
 		    }
+		    // Process it
 		    if (!doit) {
 			if (allowMultiIn && (debug()>=9)) {
 			    UINFO(9, "Not ok simp"<<okVisitor.isSimple()<<" mi"<<multiInputs

src/V3Graph.cpp

@@ -180,6 +180,7 @@ void V3Graph::userClearVertices() {
     // the extra code on each read of user() would probably slow things down more then help.
     for (V3GraphVertex* vertexp = verticesBeginp(); vertexp; vertexp=vertexp->verticesNextp()) {
 	vertexp->user(0);
+	vertexp->userp(NULL);	 // Its a union, but might be different size then user()
     }
 }
 
@@ -187,7 +188,8 @@ void V3Graph::userClearEdges() {
     // Clear user() in all of tree
     for (V3GraphVertex* vertexp = verticesBeginp(); vertexp; vertexp=vertexp->verticesNextp()) {
 	for (V3GraphEdge* edgep = vertexp->outBeginp(); edgep; edgep=edgep->outNextp()) {
-	    edgep->userp(NULL);
+	    edgep->user(0);
+	    edgep->userp(NULL);	 // Its a union, but might be different size then user()
 	}
     }
 }
@@ -253,6 +255,8 @@ void V3Graph::dumpDotFile(const string& filename, bool colorAsSubgraph) {
     *logp<<"digraph v3graph {\n";
     *logp<<"\trankdir="<<dotRankDir()<<"\n";
     *logp<<"\tsize="<<"\"7.5,10\""<<"\n";
+    *logp<<"\tnTITLE\t[fontsize=20 label=\""<<filename<<"\", shape=box, style=bold, color=black];\n";
+    *logp<<"\n";
 
     // List of all possible subgraphs
     typedef multimap<string,V3GraphVertex*> SubgraphMmap;

src/V3GraphAcyc.cpp

@@ -37,6 +37,7 @@
 //	Break the minimal number of backward edges to make the graph acyclic
 
 class GraphAcycVertex : public V3GraphVertex {
+    // user() is used for various sub-algorithm pieces
     V3GraphVertex*	m_origVertexp;		// Pointer to first vertex this represents
 protected:
     friend class GraphAcyc;
@@ -308,6 +309,9 @@ void GraphAcyc::simplifyOne (GraphAcycVertex* avertexp) {
 	    avertexp->setDelete();	// Mark so we won't delete it twice
 	    // Make a new edge connecting the two vertices directly
 	    // If both are breakable, we pick the one with less weight, else it's arbitrary
+	    // We can forget about the origEdge list for the "non-selected" set of edges,
+	    // as we need to break only one set or the other set of edges, not both.
+	    // (This is why we must give preference to the cutable set.)
 	    V3GraphEdge* templateEdgep = ( (inEdgep->cutable()
 					    && (!outEdgep->cutable()
 						|| inEdgep->weight()<outEdgep->weight() ))
@@ -353,7 +357,7 @@ void GraphAcyc::simplifyDup (GraphAcycVertex* avertexp) {
     if (avertexp->isDelete()) return;
     // Clear marks
     for (V3GraphEdge* edgep = avertexp->outBeginp(); edgep; edgep=edgep->outNextp()) {
-	edgep->top()->user(false);
+	edgep->top()->userp(NULL);
     }
     // Mark edges and detect duplications
     for (V3GraphEdge* nextp, *edgep = avertexp->outBeginp(); edgep; edgep=nextp) {
@@ -364,16 +368,16 @@ void GraphAcyc::simplifyDup (GraphAcycVertex* avertexp) {
 	    if (!prevEdgep->cutable()) {
 		// !cutable duplicates prev !cutable: we can ignore it, redundant
 		//  cutable duplicates prev !cutable: know it's not a relevant loop, ignore it
-		UINFO(8,"    DelDupEdge "<<avertexp<<endl);
+		UINFO(8,"    DelDupEdge "<<avertexp<<" -> "<<edgep->top()<<endl);
 		edgep->unlinkDelete(); edgep = NULL;
 	    } else if (!edgep->cutable()) {
 		// !cutable duplicates prev  cutable: delete the earlier cutable
-		UINFO(8,"    DelDupPrev "<<avertexp<<endl);
+		UINFO(8,"    DelDupPrev "<<avertexp<<" -> "<<prevEdgep->top()<<endl);
 		prevEdgep->unlinkDelete(); prevEdgep = NULL;
 		outVertexp->userp(edgep);
 	    } else {
 		//  cutable duplicates prev  cutable: combine weights
-		UINFO(8,"    DelDupComb "<<avertexp<<endl);
+		UINFO(8,"    DelDupComb "<<avertexp<<" -> "<<edgep->top()<<endl);
 		prevEdgep->weight (prevEdgep->weight() + edgep->weight());
 		addOrigEdgep (prevEdgep, edgep);
 		edgep->unlinkDelete(); edgep = NULL;

src/V3GraphAlg.cpp

@@ -86,7 +86,7 @@ private:
     void vertexIterate(V3GraphVertex* vertexp) {
 	// Clear marks
 	for (V3GraphEdge* edgep = vertexp->outBeginp(); edgep; edgep=edgep->outNextp()) {
-	    edgep->top()->user(false);
+	    edgep->top()->userp(NULL);
 	}
 	// Mark edges and detect duplications
 	for (V3GraphEdge* nextp, *edgep = vertexp->outBeginp(); edgep; edgep=nextp) {

src/V3GraphTest.cpp

@@ -311,6 +311,34 @@ public:
 	gp->dfaReduce();
     }
 };
+
+//======================================================================
+
+class V3GraphTestImport : public V3GraphTest {
+
+    void dotImport();
+
+public:
+    virtual string name() { return "import"; }
+    virtual void runTest() {
+	DfaGraph* gp = &m_graph;
+	if (V3GraphTest::debug()) gp->debug(9);
+	dotImport();
+	dump();
+	gp->acyclic(&V3GraphEdge::followAlwaysTrue);
+	dump();
+	gp->rank(&V3GraphEdge::followAlwaysTrue);
+	dump();
+    }
+};
+
+#if 0
+# include "graph_export.cpp"
+#else 
+void V3GraphTestImport::dotImport() {
+}
+#endif
+
 //======================================================================
 
 void V3Graph::test() {
@@ -320,5 +348,6 @@ void V3Graph::test() {
     { V3GraphTestAcyc test; test.run(); }
     { V3GraphTestVars test; test.run(); }
     { V3GraphTestDfa test; test.run(); }
+    { V3GraphTestImport test; test.run(); }
     if (V3GraphTest::debug()) v3fatalSrc("Exiting due to graph testing enabled");
 }

src/V3Inline.cpp

@@ -235,8 +235,8 @@ private:
     }
     virtual void visit(AstDisplay* nodep, AstNUser*) {
 	// If there's a %m in the display text, we add a special node that will contain the name()
-	if (m_cellp
-	    && nodep->name().find("%m") != string::npos) {
+	// Similar code in V3Begin
+	if (m_cellp && nodep->needScopeTracking()) {
 	    // To keep correct visual order, must add before other Text's
 	    AstNode* afterp = nodep->scopeAttrp();
 	    if (afterp) afterp->unlinkFrBackWithNext();

src/V3Link.cpp

@@ -143,6 +143,13 @@ private:
 	if (!m_curVarsp) nodep->v3fatalSrc("Var not under module??\n");
 	nodep->iterateChildren(*this);
 	if (m_idState==ID_FIND) {
+	    // We used modTrace before leveling, and we may now
+	    // want to turn it off now that we know the levelizations
+	    if (v3Global.opt.traceDepth()
+		&& (m_modp->level()-1) > v3Global.opt.traceDepth()) {
+		m_modp->modTrace(false);
+		nodep->trace(false);
+	    }
 	    // Find under either a task or the module's vars
 	    AstNode* findidp = m_curVarsp->findIdName(nodep->name());
 	    AstVar* findvarp = findidp->castVar();
@@ -213,6 +220,8 @@ private:
 		nodep->userp(m_curVarsp);
 	    }
 	    // Convert the func's range to the output variable
+	    // This should probably be done in the Parser instead, as then we could
+	    // just attact normal signal attributes to it.
 	    if (AstFunc* funcp = nodep->castFunc()) {
 		if (!funcp->fvarp()->castVar()) {
 		    AstRange* rangep = funcp->fvarp()->castRange();
@@ -221,6 +230,7 @@ private:
 		    newvarp->isSigned(funcp->isSigned());
 		    newvarp->funcReturn(true);
 		    newvarp->trace(false);  // Not user visible
+		    newvarp->attrIsolateAssign(funcp->attrIsolateAssign());
 		    funcp->addFvarp(newvarp);
 		    // Explicit insert required, as the var name shadows the upper level's task name
 		    m_curVarsp->insert(newvarp->name(), newvarp);

src/V3LinkLevel.cpp

@@ -92,8 +92,8 @@ void V3LinkLevel::modSortByLevel() {
     AstModule* topp = NULL;
     for (AstModule* nodep = v3Global.rootp()->modulesp(); nodep; nodep=nodep->nextp()->castModule()) {
 	if (nodep->level()<=2) {
-	    if (topp) nodep->v3error("Unsupported: Multiple top level modules: "
-				     <<nodep->prettyName()<<" and "<<topp->prettyName());
+	    if (topp) nodep->v3warn(MULTITOP, "Unsupported: Multiple top level modules: "
+				    <<nodep->prettyName()<<" and "<<topp->prettyName());
 	    topp = nodep;
 	}
 	vec.push_back(nodep);

src/V3LinkResolve.cpp

@@ -54,6 +54,7 @@ private:
     // Below state needs to be preserved between each module call.
     AstModule*	m_modp;		// Current module
     AstNodeFTask* m_ftaskp;	// Function or task we're inside
+    AstVAssert*	m_assertp;	// Current assertion
 
     //int debug() { return 9; }
 
@@ -72,13 +73,23 @@ private:
 	nodep->iterateChildren(*this);
 	m_modp = NULL;
     }
+    virtual void visit(AstVAssert* nodep, AstNUser*) {
+	if (m_assertp) nodep->v3error("Assert not allowed under another assert");
+	m_assertp = nodep;
+	nodep->iterateChildren(*this);
+	m_assertp = NULL;
+    }
+
     virtual void visit(AstVar* nodep, AstNUser*) {
 	nodep->iterateChildren(*this);
 	if (nodep->arraysp() && nodep->isIO()) {
 	    nodep->v3error("Arrayed variables may not be inputs nor outputs");
 	}
 	if (m_ftaskp) nodep->funcLocal(true);
-	if (nodep->isSigPublic()) m_modp->modPublic(true);	// Avoid flattening if signals are exposed
+	if (nodep->isSigModPublic()) {
+	    nodep->sigModPublic(false);  // We're done with this attribute
+	    m_modp->modPublic(true);	// Avoid flattening if signals are exposed
+	}
     }
 
     virtual void visit(AstNodeVarRef* nodep, AstNUser*) {
@@ -317,6 +328,13 @@ private:
     virtual void visit(AstDisplay* nodep, AstNUser*) {
 	nodep->iterateChildren(*this);
 	if (nodep->filep()) expectDescriptor(nodep, nodep->filep()->castNodeVarRef());
+	if (!m_assertp
+	    && (nodep->displayType() == AstDisplayType::INFO
+		|| nodep->displayType() == AstDisplayType::WARNING
+		|| nodep->displayType() == AstDisplayType::ERROR
+		|| nodep->displayType() == AstDisplayType::FATAL)) {
+	    nodep->v3error(nodep->verilogKwd()+" only allowed under a assertion.");
+	}
     }
 
     virtual void visit(AstScCtor* nodep, AstNUser*) {
@@ -345,6 +363,7 @@ public:
     LinkResolveVisitor(AstNetlist* rootp) {
 	m_ftaskp = NULL;
 	m_modp = NULL;
+	m_assertp = NULL;
 	//
 	rootp->accept(*this);
     }

src/V3Number.cpp

@@ -296,6 +296,11 @@ V3Number& V3Number::setAllBitsZ() {
     for (int i=0; i<words(); i++) { m_value[i]=0; m_valueX[i] = ~0; }
     return *this;
 }
+V3Number& V3Number::setMask(int nbits) {
+    setZero();
+    for (int bit=0; bit<nbits; bit++) { setBit(bit,1); }
+    return *this;
+}
 
 //======================================================================
 // ACCESSORS

src/V3Number.h

@@ -108,6 +108,7 @@ public:
     // SETTERS
     V3Number& setAllBitsX();
     V3Number& setAllBitsZ();
+    V3Number& setMask(int nbits);  // IE if nbits=1, then 0b1, if 2->0b11, if 3->0b111 etc
 
     // ACCESSORS
     string ascii(bool prefixed=true, bool cleanVerilog=false) const;

src/V3Options.cpp

@@ -48,7 +48,8 @@ struct V3OptionsImp {
     list<string>	m_allArgs;	// List of every argument encountered
     list<string>	m_incDirs;	// Include directories (ordered)
     set<string>		m_incDirSet;	// Include directories (for removing duplicates)
-    set<string>		m_libExts;	// Library extensions
+    list<string>	m_libExts;	// Library extensions (ordered)
+    set<string>		m_libExtSet;	// Library extensions (for removing duplicates)
     DirMap		m_dirMap;	// Directory listing
 
     // ACCESSOR METHODS
@@ -59,8 +60,9 @@ struct V3OptionsImp {
 	}
     }
     void addLibExt(const string& libext) {
-	if (m_libExts.find(libext) == m_libExts.end()) {
-	    m_libExts.insert(libext);
+	if (m_libExtSet.find(libext) == m_libExtSet.end()) {
+	    m_libExtSet.insert(libext);
+	    m_libExts.push_back(libext);
 	}
     }
     V3OptionsImp() {}
@@ -193,7 +195,7 @@ string V3Options::filePath (FileLine* fl, const string& modname, const string& e
     // using the incdir and libext's.
     // Return "" if not found.
     for (list<string>::iterator dirIter=m_impp->m_incDirs.begin(); dirIter!=m_impp->m_incDirs.end(); ++dirIter) {
-	for (set<string>::iterator extIter=m_impp->m_libExts.begin(); extIter!=m_impp->m_libExts.end(); ++extIter) {
+	for (list<string>::iterator extIter=m_impp->m_libExts.begin(); extIter!=m_impp->m_libExts.end(); ++extIter) {
 	    string fn = filenameFromDirBase(*dirIter,modname+*extIter);
 	    string exists = fileExists(fn);
 	    if (exists!="") {
@@ -214,7 +216,7 @@ string V3Options::filePath (FileLine* fl, const string& modname, const string& e
 	} else {
 	    fl->v3error("Looked in:"<<endl);
 	    for (list<string>::iterator dirIter=m_impp->m_incDirs.begin(); dirIter!=m_impp->m_incDirs.end(); ++dirIter) {
-		for (set<string>::iterator extIter=m_impp->m_libExts.begin(); extIter!=m_impp->m_libExts.end(); ++extIter) {
+		for (list<string>::iterator extIter=m_impp->m_libExts.begin(); extIter!=m_impp->m_libExts.end(); ++extIter) {
 		    string fn = filenameFromDirBase(*dirIter,modname+*extIter);
 		    fl->v3error("      "<<fn<<endl);
 		}
@@ -353,6 +355,10 @@ void V3Options::parseOptsList(FileLine* fl, int argc, char** argv) {
 		shift;
 		m_outputSplitCFuncs = atoi(argv[i]);
 	    }
+	    else if ( !strcmp (sw, "-trace-depth") ) {
+		shift;
+		m_traceDepth = atoi(argv[i]);
+	    }
 	    else if ( !strcmp (sw, "-unroll-count") ) { // Undocumented optimization tweak
 		shift;
 		m_unrollCount = atoi(argv[i]);
@@ -587,6 +593,7 @@ V3Options::V3Options() {
     m_inlineMult = 2000;
     m_outputSplit = 0;
     m_outputSplitCFuncs = 0;
+    m_traceDepth = 0;
     m_unrollCount = 64;
     m_unrollStmts = 20;
 

src/V3Options.h

@@ -72,6 +72,7 @@ class V3Options {
     int		m_inlineMult;	// main switch: --inline-mult
     int		m_outputSplit;	// main switch: --output-split
     int		m_outputSplitCFuncs;// main switch: --output-split-cfuncs
+    int		m_traceDepth;	// main switch: --trace-depth
     int		m_unrollCount;	// main switch: --unroll-count
     int		m_unrollStmts;	// main switch: --unroll-stmts
 
@@ -155,6 +156,7 @@ class V3Options {
     int	   inlineMult() const { return m_inlineMult; }
     int	   outputSplit() const { return m_outputSplit; }
     int	   outputSplitCFuncs() const { return m_outputSplitCFuncs; }
+    int	   traceDepth() const { return m_traceDepth; }
     int	   unrollCount() const { return m_unrollCount; }
     int	   unrollStmts() const { return m_unrollStmts; }
 

src/V3Order.cpp

@@ -382,6 +382,14 @@ private:
 	    //nodep->v3warn(GENCLK,"Signal unoptimizable: Generated clock: "<<nodep->prettyName());
 	} else if (nodep->varp()->isSigPublic()) {
 	    nodep->v3warn(UNOPT,"Signal unoptimizable: Feedback to public clock or circular logic: "<<nodep->prettyName());
+	    if (!nodep->fileline()->warnIsOff(V3ErrorCode::UNOPT)) {
+		nodep->fileline()->warnOff(V3ErrorCode::UNOPT, true);  // Complain just once
+		// Give the user an example.
+		bool tempWeight = (edgep && edgep->weight()==0);
+		if (tempWeight) edgep->weight(1);  // Else the below loop detect can't see the loop
+		m_graph.reportLoops(&OrderEdge::followComboConnected, vertexp); // calls OrderGraph::loopsVertexCb
+		if (tempWeight) edgep->weight(0);
+	    }
 	} else {
 	    // We don't use UNOPT, as there are lots of V2 places where it was needed, that aren't any more
 	    // First v3warn not inside warnIsOff so we can see the suppressions with --debug

src/V3PreProc.cpp

@@ -301,12 +301,12 @@ void V3PreProcImp::comment(const string& text) {
 	    if (commentTokenMatch(cmd/*ref*/, "parallel_case")) {
 		insertUnreadback ("/*verilator parallel_case*/");
 	    }
-	    if (commentTokenMatch(cmd/*ref*/, "one_hot")) {
-		insertUnreadback ("/*verilator one_hot*/ "+cmd+";");
-	    }
-	    if (commentTokenMatch(cmd/*ref*/, "one_cold")) {
-		insertUnreadback ("/*verilator one_cold*/ "+cmd+";");
-	    }
+	    //if (commentTokenMatch(cmd/*ref*/, "one_hot")) {
+	    //	insertUnreadback ("/*verilator one_hot*/ "+cmd+";");
+	    //}
+	    //if (commentTokenMatch(cmd/*ref*/, "one_cold")) {
+	    //	insertUnreadback ("/*verilator one_cold*/ "+cmd+";");
+	    //}
 	    // else ignore the comment we don't recognize
 	} // else no assertions
     } else {

src/V3Premit.cpp

@@ -71,14 +71,18 @@ private:
 	//   ASSIGN(CONST*here*, VARREF(!sc))
 	//   ARRAYSEL(*here*, ...)   (No wides can be in any argument but first, so we don't check which arg is wide)
 	//   ASSIGN(x, SEL*HERE*(ARRAYSEL()...)   (m_assignLhs==true handles this.)
+	//UINFO(9, "   Check: "<<nodep<<endl);
+	//UINFO(9, "     Detail stmtp="<<(m_stmtp?"Y":"N")<<" U="<<(nodep->user()?"Y":"N")<<" IW "<<(nodep->isWide()?"Y":"N")<<endl);
 	if (m_stmtp
 	    && !nodep->user()) {	// Not already done
 	    if (nodep->isWide()) {		// Else might be cell interconnect or something
 		if (m_assignLhs) {
-		} else if (nodep->backp()->castNodeAssign()
-			   && assignNoTemp(nodep->backp()->castNodeAssign())) {
+		} else if (nodep->firstAbovep()
+			   && nodep->firstAbovep()->castNodeAssign()
+			   && assignNoTemp(nodep->firstAbovep()->castNodeAssign())) {
 		    // Not much point if it's just a direct assignment to a constant
-		} else if (nodep->backp()->castArraySel()) {  // ArraySel's are pointer refs, ignore
+		} else if (nodep->firstAbovep()
+			   && nodep->firstAbovep()->castArraySel()) {  // ArraySel's are pointer refs, ignore
 		} else {
 		    UINFO(4,"Cre Temp: "<<nodep<<endl);
 		    createDeepTemp(nodep);
@@ -140,6 +144,7 @@ private:
     virtual void visit(AstCFunc* nodep, AstNUser*) {
 	m_funcp = nodep;
 	nodep->iterateChildren(*this);
+	m_funcp = NULL;
     }
     void startStatement(AstNode* nodep) {
 	m_assignLhs = false;

src/V3Read.cpp

@@ -62,10 +62,10 @@ public:
     // METHODS
     void stateExitPsl() {
 	if (YY_START != PSL) yyerror("Internal error: Exiting PSL state when not in PSL state");
-	BEGIN VLG;
+	yy_pop_state();
     }
     void statePushVlg() {
-	yy_push_state(VLG);
+	yy_push_state(STATE_VERILOG_RECENT);
     }
     void statePop() {
 	yy_pop_state();

src/V3Read.h

@@ -39,6 +39,7 @@ class V3Read {
     static V3Read*	s_readp;	// Current THIS, bison() isn't class based
     FileLine*	m_fileline;	// Filename/linenumber currently active
     bool	m_inLibrary;	// Currently reading a library vs. regular file
+    int		m_inBeginKwd;		// Inside a `begin_keywords
     deque<string*> m_stringps;		// Created strings for later cleanup
     deque<V3Number*> m_numberps;	// Created numbers for later cleanup
     //int debug() { return 9; }
@@ -54,6 +55,8 @@ protected:
     static void incLineno() { s_readp->fileline()->incLineno(); }
     static void verilatorCmtLint(const char* text, bool on);
     static void verilatorCmtBad(const char* text);
+    static void pushBeginKeywords() { s_readp->m_inBeginKwd++; }
+    static bool popBeginKeywords() { if (s_readp->m_inBeginKwd) { s_readp->m_inBeginKwd--; return true; } else return false; }
 
 public: // But for internal use only
     static string* newString(const string& text) {
@@ -94,6 +97,7 @@ public:
     V3Read(AstNetlist* rootp) {
 	m_rootp = rootp; m_lexerp = NULL;
 	m_inLibrary = false;
+	m_inBeginKwd = 0;
     }
     ~V3Read() {
 	for (deque<string*>::iterator it = m_stringps.begin(); it != m_stringps.end(); ++it) {

src/V3Split.cpp

@@ -428,7 +428,7 @@ private:
 	AstNode* firstp = nodep;   // We may reorder, and nodep is no longer first.
 	void* oldBlockUser3 = nodep->user3p();   // May be overloaded in below loop, save it
 	nodep->user3p(NULL);
-	if (nodep->backp()->nextp()==nodep) nodep->v3fatalSrc("Node passed is in next list; should have processed all list at oncen");
+	if (!nodep->firstAbovep()) nodep->v3fatalSrc("Node passed is in next list; should have processed all list at once");
 	// Process it
 	if (!nodep->nextp()) {
 	    // Just one, so can't reorder.  Just look for more blocks/statements.

src/V3SplitAs.cpp

@@ -0,0 +1,215 @@
+// $Id$
+//*************************************************************************
+// DESCRIPTION: Verilator: Break always into separate statements to reduce temps
+//
+// Code available from: http://www.veripool.com/verilator
+//
+// AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
+//
+//*************************************************************************
+//
+// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// redistribute it and/or modify it under the terms of either the GNU
+// General Public License or the Perl Artistic License.
+//
+// Verilator is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+//*************************************************************************
+// V3SplitAs's Transformations:
+//
+//	Search each ALWAYS for a VARREF lvalue with a /*isolate_assignments*/ attribute
+//	If found, color statements with both, assignment to that varref, or other assignments.
+//	Replicate the Always, and remove mis-colored duplicate code.
+//
+//*************************************************************************
+
+#include "config_build.h"
+#include "verilatedos.h"
+#include <stdio.h>
+#include <stdarg.h>
+#include <unistd.h>
+#include <algorithm>
+#include <vector>
+#include <map>
+
+#include "V3Global.h"
+#include "V3SplitAs.h"
+#include "V3Stats.h"
+#include "V3Ast.h"
+
+//######################################################################
+
+class SplitAsBaseVisitor : public AstNVisitor {
+public:
+    // METHODS
+    //int debug() { return 9; }
+};
+
+//######################################################################
+// Find all split variables in a block
+
+class SplitAsFindVisitor : public SplitAsBaseVisitor {
+private:
+    // STATE
+    AstVarScope* m_splitVscp;	// Variable we want to split
+
+    // METHODS
+    virtual void visit(AstVarRef* nodep, AstNUser*) {
+	if (nodep->lvalue() && !m_splitVscp
+	    && nodep->varp()->attrIsolateAssign()) {
+	    m_splitVscp = nodep->varScopep();
+	}
+    }
+    virtual void visit(AstNode* nodep, AstNUser*) {
+	nodep->iterateChildren(*this);
+    }
+public:
+    // CONSTUCTORS
+    SplitAsFindVisitor(AstAlways* nodep) {
+	m_splitVscp = NULL;
+	nodep->accept(*this);
+    }
+    virtual ~SplitAsFindVisitor() {}
+    // METHODS
+    AstVarScope* splitVscp() const { return m_splitVscp; }
+};
+
+//######################################################################
+// Remove nodes not containing proper references
+
+class SplitAsCleanVisitor : public SplitAsBaseVisitor {
+private:
+    // STATE
+    AstVarScope* m_splitVscp;	// Variable we want to split
+    bool	 m_modeMatch;	// Remove matching Vscp, else non-matching
+    bool	 m_keepStmt;	// Current Statement must be preserved
+    bool	 m_matches;	// Statement below has matching lvalue reference
+
+    // METHODS
+    virtual void visit(AstVarRef* nodep, AstNUser*) {
+	if (nodep->lvalue()) {
+	    if (nodep->varScopep()==m_splitVscp) {
+		UINFO(6,"       CL VAR "<<nodep<<endl);
+		m_matches = true;
+	    }
+	}
+    }
+    virtual void visit(AstNodeStmt* nodep, AstNUser*) {
+	UINFO(6,"     CL STMT "<<nodep<<endl);
+	bool oldKeep = m_keepStmt;
+	{
+	    m_matches = false;
+	    m_keepStmt = false;
+
+	    nodep->iterateChildren(*this);
+
+	    if (m_keepStmt
+		|| (m_modeMatch ? m_matches : !m_matches)) {
+		UINFO(6,"     Keep   STMT "<<nodep<<endl);
+		m_keepStmt = true;
+	    } else {
+		UINFO(6,"     Delete STMT "<<nodep<<endl);
+		nodep->unlinkFrBack(); pushDeletep(nodep);
+	    }
+	}
+	// If something below matches, the upper statement remains too.
+	m_keepStmt = oldKeep || m_keepStmt;
+	UINFO(9,"     upKeep="<<m_keepStmt<<" STMT "<<nodep<<endl);
+    }
+    virtual void visit(AstNode* nodep, AstNUser*) {
+	nodep->iterateChildren(*this);
+    }
+public:
+    // CONSTUCTORS
+    SplitAsCleanVisitor(AstAlways* nodep, AstVarScope* vscp, bool modeMatch) {
+	m_splitVscp = vscp;
+	m_modeMatch = modeMatch;
+	nodep->accept(*this);
+    }
+    virtual ~SplitAsCleanVisitor() {}
+};
+
+//######################################################################
+// SplitAs class functions
+
+class SplitAsVisitor : public SplitAsBaseVisitor {
+private:
+    // NODE STATE
+    //  AstAlways::user()	-> bool.  True if already processed
+
+    // STATE
+    V3Double0	m_statSplits;	// Statistic tracking
+    AstVarScope* m_splitVscp;	// Variable we want to split
+
+    // METHODS
+    void splitAlways(AstAlways* nodep) {
+	UINFO(3,"Split  "<<nodep<<endl);
+	UINFO(3,"   For "<<m_splitVscp<<endl);
+	if (debug()>=9) nodep->dumpTree(cout,"-in  : ");
+	// Duplicate it and link in
+	AstAlways* newp = nodep->cloneTree(false)->castAlways();
+	newp->user(true);  // So we don't clone it again
+	nodep->addNextHere(newp);
+	{   // Delete stuff we don't want in old
+	    SplitAsCleanVisitor visitor (nodep, m_splitVscp, false);
+	    if (debug()>=9) nodep->dumpTree(cout,"-out0: ");
+	}
+	{   // Delete stuff we don't want in new
+	    SplitAsCleanVisitor visitor (newp, m_splitVscp, true);
+	    if (debug()>=9) newp->dumpTree(cout,"-out1: ");
+	}
+    }
+
+    virtual void visit(AstAlways* nodep, AstNUser*) {
+	// Are there any lvalue references below this?
+	// There could be more then one.  So, we process the first one found first.
+	AstVarScope* lastSplitVscp = NULL;
+	while (!nodep->user()) {
+	    // Find any splittable variables
+	    SplitAsFindVisitor visitor (nodep);
+	    m_splitVscp = visitor.splitVscp();
+	    if (m_splitVscp && m_splitVscp == lastSplitVscp) {
+		// We did this last time!  Something's stuck!
+		nodep->v3fatalSrc("Infinite loop in isolate_assignments removal for: "<<m_splitVscp->prettyName())
+		m_splitVscp = NULL;
+	    }
+	    lastSplitVscp = m_splitVscp;
+	    // Now isolate the always
+	    if (m_splitVscp) {
+		splitAlways(nodep);
+		m_statSplits++;
+	    } else {
+		nodep->user(true);
+	    }
+	}
+    }
+
+    // Speedup; no always under math
+    virtual void visit(AstNodeMath* nodep, AstNUser*) {}
+
+    virtual void visit(AstNode* nodep, AstNUser*) {
+	nodep->iterateChildren(*this);
+    }
+
+public:
+    // CONSTUCTORS
+    SplitAsVisitor(AstNetlist* nodep) {
+	m_splitVscp = NULL;
+	AstNode::userClearTree();	// userp() used on entire tree
+	nodep->accept(*this);
+    }
+    virtual ~SplitAsVisitor() {
+	V3Stats::addStat("Optimizations, isolate_assignments blocks", m_statSplits);
+    }
+};
+
+//######################################################################
+// SplitAs class functions
+
+void V3SplitAs::splitAsAll(AstNetlist* nodep) {
+    UINFO(2,__FUNCTION__<<": "<<endl);
+    SplitAsVisitor visitor (nodep);
+}

src/V3SplitAs.h

@@ -0,0 +1,36 @@
+// $Id$ //-*- C++ -*-
+//*************************************************************************
+// DESCRIPTION: Verilator: Break always into separate statements to reduce temps
+//
+// Code available from: http://www.veripool.com/verilator
+//
+// AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
+//
+//*************************************************************************
+//
+// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// redistribute it and/or modify it under the terms of either the GNU
+// General Public License or the Perl Artistic License.
+//
+// Verilator is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+//*************************************************************************
+
+#ifndef _V3SPLITAS_H_
+#define _V3SPLITAS_H_ 1
+#include "config_build.h"
+#include "verilatedos.h"
+#include "V3Error.h"
+#include "V3Ast.h"
+
+//============================================================================
+
+class V3SplitAs {
+public:
+    static void splitAsAll(AstNetlist* nodep);
+};
+
+#endif // Guard

src/V3Stats.cpp

@@ -63,9 +63,8 @@ private:
 	m_instrs += nodep->instrCount();
 	if (m_counting) {
 	    ++m_statTypeCount[nodep->type()];
-	    if (nodep->backp() && nodep->backp()->nextp()!=nodep) {
-		// Grab only those above, not those "back"
-		++m_statAbove[nodep->backp()->type()][nodep->type()];
+	    if (nodep->firstAbovep()) { // Grab only those above, not those "back"
+		++m_statAbove[nodep->firstAbovep()->type()][nodep->type()];
 	    }
 	    m_statInstr += nodep->instrCount();
 	    if (m_cfuncp && !m_cfuncp->slow()) m_statInstrFast += nodep->instrCount();

src/V3Task.cpp

@@ -306,6 +306,7 @@ private:
 	AstVar* newvarp = new AstVar (invarp->fileline(), AstVarType::BLOCKTEMP,
 				      name, invarp);
 	newvarp->funcLocal(false);
+	newvarp->propagateAttrFrom(invarp);
 	m_modp->addStmtp(newvarp);
 	AstVarScope* newvscp = new AstVarScope (newvarp->fileline(), m_scopep, newvarp);
 	m_scopep->addVarp(newvscp);
@@ -628,7 +629,7 @@ private:
 	if (!funcp) nodep->v3fatalSrc("unlinked");
 	// Inline func refs in the function
 	iterateIntoFTask(funcp);
-	// Create output variabls
+	// Create output variable
 	string namePrefix = "__Vfunc_"+funcp->shortName()+"__"+cvtToStr(m_modNCalls++);
 	AstVarScope* outvscp = createVarScope (funcp->fvarp()->castVar(),
 					       namePrefix+"__out");

src/V3Unroll.cpp

@@ -252,7 +252,12 @@ private:
 			if (clonedIncsp) {
 			    // Previous iteration of loop set the variable.
 			    // This set is redundant with this next iteration and can be removed.
-			    clonedIncsp->unlinkFrBack()->deleteTree();
+			    if (clonedIncsp == newbodysp) {  // Increment was only thing in list
+				newbodysp = NULL;
+			    } else {
+				clonedIncsp->unlinkFrBack();
+			    }
+			    clonedIncsp->deleteTree();
 			}
 			clonedIncsp = incp->clonep(); if (!clonedIncsp) nodep->v3fatalSrc("inc failed");
 		    }

src/V3Width.cpp

@@ -575,6 +575,13 @@ private:
 	nodep->propp()->iterateAndNext(*this,WidthVP(1,1,BOTH).p());
 	widthCheckReduce(nodep,"Property",nodep->propp(),1,1);	// it's like a if() condition.
     }
+    virtual void visit(AstVAssert* nodep, AstNUser*) {
+	// TOP LEVEL NODE
+	nodep->propp()->iterateAndNext(*this,WidthVP(1,1,BOTH).p());
+	nodep->passsp()->iterateAndNext(*this);
+	nodep->failsp()->iterateAndNext(*this);
+	widthCheckReduce(nodep,"Property",nodep->propp(),1,1);	// it's like a if() condition.
+    }
     virtual void visit(AstPin* nodep, AstNUser*) {
 	//if (debug()) nodep->dumpTree(cout,"-  PinPre: ");
 	// TOP LEVEL NODE

src/Verilator.cpp

@@ -71,6 +71,7 @@
 #include "V3Scope.h"
 #include "V3Signed.h"
 #include "V3Split.h"
+#include "V3SplitAs.h"
 #include "V3Stats.h"
 #include "V3Subst.h"
 #include "V3Table.h"
@@ -158,13 +159,11 @@ void process () {
 
     // Assertion insertion
     //    After we've added block coverage, but before other nasty transforms
-    if (v3Global.opt.assertOn() || v3Global.opt.psl()) {
-	V3AssertPre::assertPreAll(v3Global.rootp());
-	v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("assertpre.tree"));
-	//
-	V3Assert::assertAll(v3Global.rootp());
-	v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("assert.tree"));
-    }
+    V3AssertPre::assertPreAll(v3Global.rootp());
+    v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("assertpre.tree"));
+    //
+    V3Assert::assertAll(v3Global.rootp());
+    v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("assert.tree"));
 
     // Add top level wrapper with instance pointing to old top
     // Must do this after we know the width of any parameters
@@ -284,8 +283,10 @@ void process () {
     // Split single ALWAYS blocks into multiple blocks for better ordering chances
     if (v3Global.opt.oSplit()) {
 	V3Split::splitAlwaysAll(v3Global.rootp());
-	v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("split.tree"));
+	//v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("split.tree"));
     }
+    V3SplitAs::splitAsAll(v3Global.rootp());
+    v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("splitas.tree"));
 
     // Create tracing sample points, before we start eliminating signals
     if (v3Global.opt.trace()) {

src/config_build.h.in

@@ -24,7 +24,7 @@
 //**********************************************************************
 //**** Version and host name
 
-#define DTVERSION	"Verilator 3.631 1/2/2007"
+#define DTVERSION	"Verilator 3.640 3/12/2007"
 
 //**********************************************************************
 //**** Functions

src/verilog.l

@@ -31,6 +31,8 @@
 extern void yyerror(char*);
 extern void yyerrorf(const char* format, ...);
 
+#define STATE_VERILOG_RECENT  S05		// State name for most recent Verilog Version
+
 //======================================================================
 
 #define NEXTLINE() {V3Read::incLineno();}
@@ -88,7 +90,10 @@ void yyerrorf(const char* format, ...) {
 %a 15000
 %o 25000
 
-%s VLG PSL STRING   SYSCHDR SYSCINT SYSCIMP SYSCIMPH SYSCCTOR SYSCDTOR  IGNORE
+%s V95 V01 V05 S05
+%s PSL STRING
+%s SYSCHDR SYSCINT SYSCIMP SYSCIMPH SYSCCTOR SYSCDTOR
+%s IGNORE
 
 ws	[ \t\f\r]+
 	/* identifier */
@@ -98,399 +103,484 @@ escid	\\[^ \t\f\r\n]+
 
 %%
 
-<INITIAL>.|\n 		{BEGIN VLG; yyless(0); }
+<INITIAL>.|\n 		{BEGIN STATE_VERILOG_RECENT; yyless(0); }
 
-<VLG,PSL>{ws}		;			/* ignore white-space */
-<VLG,PSL>\n		{NEXTLINE();}		/* Count line numbers */
-<VLG,PSL>always		{yylval.fileline = CRELINE(); return yALWAYS;}
-<VLG,PSL>always_comb	{yylval.fileline = CRELINE(); return yALWAYS;}
-<VLG,PSL>always_ff	{yylval.fileline = CRELINE(); return yALWAYS;}
-<VLG,PSL>always_latch	{yylval.fileline = CRELINE(); return yALWAYS;}
-<VLG,PSL>and		{yylval.fileline = CRELINE(); return yAND;}
-<VLG,PSL>assign		{yylval.fileline = CRELINE(); return yASSIGN;}
-<VLG,PSL>begin		{yylval.fileline = CRELINE(); return yBBEGIN;}
-<VLG,PSL>buf		{yylval.fileline = CRELINE(); return yBUF;}
-<VLG,PSL>case		{yylval.fileline = CRELINE(); return yCASE;}
-<VLG,PSL>casex		{yylval.fileline = CRELINE(); return yCASEX;}
-<VLG,PSL>casez		{yylval.fileline = CRELINE(); return yCASEZ;}
-<VLG,PSL>default	{yylval.fileline = CRELINE(); return yDEFAULT;}
-<VLG,PSL>defparam	{yylval.fileline = CRELINE(); return yDEFPARAM;}
-<VLG,PSL>else		{yylval.fileline = CRELINE(); return yELSE;}
-<VLG,PSL>end		{yylval.fileline = CRELINE(); return yBEND;}
-<VLG,PSL>endcase	{yylval.fileline = CRELINE(); return yENDCASE;}
-<VLG,PSL>endfunction	{yylval.fileline = CRELINE(); return yENDFUNCTION;}
-<VLG,PSL>endgenerate	{yylval.fileline = CRELINE(); return yENDGENERATE;}
-<VLG,PSL>endmodule	{yylval.fileline = CRELINE(); return yENDMODULE;}
-<VLG,PSL>endspecify	{yylval.fileline = CRELINE(); return yENDSPECIFY;}
-<VLG,PSL>endtask	{yylval.fileline = CRELINE(); return yENDTASK;}
-<VLG,PSL>final		{yylval.fileline = CRELINE(); return yFINAL;}
-<VLG,PSL>for		{yylval.fileline = CRELINE(); return yFOR;}
-<VLG,PSL>function	{yylval.fileline = CRELINE(); return yFUNCTION;}
-<VLG,PSL>generate	{yylval.fileline = CRELINE(); return yGENERATE;}
-<VLG,PSL>genvar		{yylval.fileline = CRELINE(); return yGENVAR;}
-<VLG,PSL>if		{yylval.fileline = CRELINE(); return yIF;}
-<VLG,PSL>initial	{yylval.fileline = CRELINE(); return yINITIAL;}
-<VLG,PSL>inout		{yylval.fileline = CRELINE(); return yINOUT;}
-<VLG,PSL>input		{yylval.fileline = CRELINE(); return yINPUT;}
-<VLG,PSL>integer	{yylval.fileline = CRELINE(); return yINTEGER;}
-<VLG,PSL>localparam	{yylval.fileline = CRELINE(); return yLOCALPARAM;}
-<VLG,PSL>macromodule	{yylval.fileline = CRELINE(); return yMODULE;}
-<VLG,PSL>module		{yylval.fileline = CRELINE(); return yMODULE;}
-<VLG,PSL>nand		{yylval.fileline = CRELINE(); return yNAND;}
-<VLG,PSL>negedge	{yylval.fileline = CRELINE(); return yNEGEDGE;}
-<VLG,PSL>nor		{yylval.fileline = CRELINE(); return yNOR;}
-<VLG,PSL>not		{yylval.fileline = CRELINE(); return yNOT;}
-<VLG,PSL>or		{yylval.fileline = CRELINE(); return yOR;}
-<VLG,PSL>output		{yylval.fileline = CRELINE(); return yOUTPUT;}
-<VLG,PSL>parameter	{yylval.fileline = CRELINE(); return yPARAM;}
-<VLG,PSL>posedge	{yylval.fileline = CRELINE(); return yPOSEDGE;}
-<VLG,PSL>reg		{yylval.fileline = CRELINE(); return yREG;}
-<VLG,PSL>scalared	{yylval.fileline = CRELINE(); return ySCALARED;}
-<VLG,PSL>signed		{yylval.fileline = CRELINE(); return ySIGNED;}
-<VLG,PSL>specify	{yylval.fileline = CRELINE(); return ySPECIFY;}
-<VLG,PSL>specparam	{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-<VLG,PSL>supply0	{yylval.fileline = CRELINE(); return ySUPPLY0;}
-<VLG,PSL>supply1	{yylval.fileline = CRELINE(); return ySUPPLY1;}
-<VLG,PSL>task		{yylval.fileline = CRELINE(); return yTASK;}
-<VLG,PSL>tri		{yylval.fileline = CRELINE(); return yTRI;}
-<VLG,PSL>vectored	{yylval.fileline = CRELINE(); return yVECTORED;}
-<VLG,PSL>wire		{yylval.fileline = CRELINE(); return yWIRE;}
-<VLG,PSL>xnor		{yylval.fileline = CRELINE(); return yXNOR;}
-<VLG,PSL>xor		{yylval.fileline = CRELINE(); return yXOR;}
-<VLG,PSL>"$bits"	{yylval.fileline = CRELINE(); return yD_BITS;}
-<VLG,PSL>"$c"[0-9]*	{yylval.fileline = CRELINE(); return yD_C;}
-<VLG,PSL>"$countones"	{yylval.fileline = CRELINE(); return yD_COUNTONES;}
-<VLG,PSL>"$display"	{yylval.fileline = CRELINE(); return yD_DISPLAY;}
-<VLG,PSL>"$fclose"	{yylval.fileline = CRELINE(); return yD_FCLOSE;}
-<VLG,PSL>"$fdisplay"	{yylval.fileline = CRELINE(); return yD_FDISPLAY;}
-<VLG,PSL>"$finish"	{yylval.fileline = CRELINE(); return yD_FINISH;}
-<VLG,PSL>"$fopen"	{yylval.fileline = CRELINE(); return yD_FOPEN;}
-<VLG,PSL>"$fullskew"	{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-<VLG,PSL>"$fwrite"	{yylval.fileline = CRELINE(); return yD_FWRITE;}
-<VLG,PSL>"$hold"	{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-<VLG,PSL>"$isunknown"	{yylval.fileline = CRELINE(); return yD_ISUNKNOWN;}
-<VLG,PSL>"$nochange"	{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-<VLG,PSL>"$onehot"	{yylval.fileline = CRELINE(); return yD_ONEHOT;}
-<VLG,PSL>"$onehot0"	{yylval.fileline = CRELINE(); return yD_ONEHOT0;}
-<VLG,PSL>"$period"	{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-<VLG,PSL>"$realtime"	{yylval.fileline = CRELINE(); return yD_TIME;}
-<VLG,PSL>"$readmemb"	{yylval.fileline = CRELINE(); return yD_READMEMB;}
-<VLG,PSL>"$readmemh"	{yylval.fileline = CRELINE(); return yD_READMEMH;}
-<VLG,PSL>"$recovery"	{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-<VLG,PSL>"$recrem"	{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-<VLG,PSL>"$removal"	{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-<VLG,PSL>"$setup"	{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-<VLG,PSL>"$setuphold"	{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-<VLG,PSL>"$signed"	{yylval.fileline = CRELINE(); return yD_SIGNED;}
-<VLG,PSL>"$skew"	{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-<VLG,PSL>"$stop"	{yylval.fileline = CRELINE(); return yD_STOP;}
-<VLG,PSL>"$time"	{yylval.fileline = CRELINE(); return yD_TIME;}
-<VLG,PSL>"$timeskew"	{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-<VLG,PSL>"$unsigned"	{yylval.fileline = CRELINE(); return yD_UNSIGNED;}
-<VLG,PSL>"$width"	{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-<VLG,PSL>"$write"	{yylval.fileline = CRELINE(); return yD_WRITE;}
-
-<VLG,PSL>"$displayb"	{yyerrorf("Unsupported: Use $display with %%b format instead: %s",yytext);}
-<VLG,PSL>"$displayh"	{yyerrorf("Unsupported: Use $display with %%x format instead: %s",yytext);}
-<VLG,PSL>"$displayo"	{yyerrorf("Unsupported: Use $display with %%o format instead: %s",yytext);}
-<VLG,PSL>"$fdisplayb"	{yyerrorf("Unsupported: Use $fdisplay with %%b format instead: %s",yytext);}
-<VLG,PSL>"$fdisplayh"	{yyerrorf("Unsupported: Use $fdisplay with %%x format instead: %s",yytext);}
-<VLG,PSL>"$fdisplayo"	{yyerrorf("Unsupported: Use $fdisplay with %%o format instead: %s",yytext);}
-<VLG,PSL>"$fwriteb"	{yyerrorf("Unsupported: Use $fwrite with %%b format instead: %s",yytext);}
-<VLG,PSL>"$fwriteh"	{yyerrorf("Unsupported: Use $fwrite with %%x format instead: %s",yytext);}
-<VLG,PSL>"$fwriteo"	{yyerrorf("Unsupported: Use $fwrite with %%o format instead: %s",yytext);}
-<VLG,PSL>"$writeb"	{yyerrorf("Unsupported: Use $write with %%b format instead: %s",yytext);}
-<VLG,PSL>"$writeh"	{yyerrorf("Unsupported: Use $write with %%x format instead: %s",yytext);}
-<VLG,PSL>"$writeo"	{yyerrorf("Unsupported: Use $write with %%o format instead: %s",yytext);}
-
-<VLG,PSL>"$"[a-zA-Z_$]+ {yyerrorf("Unsupported or unknown PLI call: %s",yytext);}
-
- /*PSL Implemented */
-<VLG>psl		{ BEGIN PSL; yylval.fileline = CRELINE(); return yPSL; }
-<PSL>psl		{ ; }	// 'psl' may occur in middle of statement, so easier just to suppress
-
-<PSL>assert		{yylval.fileline = CRELINE(); return yASSERT;}
-<PSL>assume		{yylval.fileline = CRELINE(); return yASSERT;} //==assert
-<PSL>before_!		{yyerrorf("Illegal syntax, use before!_ instead of %s",yytext);}
-<PSL>clock		{yylval.fileline = CRELINE(); return yCLOCK;}
-<PSL>countones		{yylval.fileline = CRELINE(); return yD_COUNTONES;}
-<PSL>cover		{yylval.fileline = CRELINE(); return yCOVER;}
-<PSL>isunknown		{yylval.fileline = CRELINE(); return yD_ISUNKNOWN;}
-<PSL>onehot		{yylval.fileline = CRELINE(); return yD_ONEHOT; }
-<PSL>onehot0		{yylval.fileline = CRELINE(); return yD_ONEHOT0; }
-<PSL>until_!		{yyerrorf("Illegal syntax, use until!_ instead of %s",yytext);}
-<PSL>report		{yylval.fileline = CRELINE(); return yREPORT; }
-<PSL>true		{yylval.fileline = CRELINE(); return yTRUE; }
-
- /*Verilog Reserved*/
-<VLG,PSL>bufif0		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>bufif1		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>cmos		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>deassign	{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>disable	{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>endprimitive	{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>endtable	{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>event		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>force		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>forever	{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>fork		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>highz0		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>highz1		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>join		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>large		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>medium		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>nmos		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>notif0		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>notif1		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>pmos		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>primitive	{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>pulldown	{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>pullup		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>pull0		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>pull1		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>rcmos		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>real		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>realtime	{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>release	{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>repeat		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>rnmos		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>rpmos		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>rtran		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>rtranif0	{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>rtranif1	{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>small		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>strong0	{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>strong1	{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>table		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>time		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>tran		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>tranif0	{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>tranif1	{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>triand		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>trior		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>trireg		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>tri0		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>tri1		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>wait		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>wand		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>weak0		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>weak1		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>while		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>wor		{yyerrorf("Unsupported: Verilog reserved word not implemented: %s",yytext);}
+  /* Verilog 1995 */
+<V95,V01,V05,S05,PSL>{
+  {ws}			;			/* ignore white-space */
+  \n			{NEXTLINE();}		/* Count line numbers */
+  /*     Extensions to Verilog set, some specified by PSL */
+  "$c"[0-9]*		{yylval.fileline = CRELINE(); return yD_C;}		/*Verilator only*/
+  /*     System Tasks */
+  "$display"		{yylval.fileline = CRELINE(); return yD_DISPLAY;}
+  "$fclose"		{yylval.fileline = CRELINE(); return yD_FCLOSE;}
+  "$fdisplay"		{yylval.fileline = CRELINE(); return yD_FDISPLAY;}
+  "$finish"		{yylval.fileline = CRELINE(); return yD_FINISH;}
+  "$fopen"		{yylval.fileline = CRELINE(); return yD_FOPEN;}
+  "$fullskew"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
+  "$fwrite"		{yylval.fileline = CRELINE(); return yD_FWRITE;}
+  "$hold"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
+  "$nochange"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
+  "$period"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
+  "$readmemb"		{yylval.fileline = CRELINE(); return yD_READMEMB;}
+  "$readmemh"		{yylval.fileline = CRELINE(); return yD_READMEMH;}
+  "$realtime"		{yylval.fileline = CRELINE(); return yD_TIME;}
+  "$recovery"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
+  "$recrem"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
+  "$removal"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
+  "$setup"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
+  "$setuphold"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
+  "$skew"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
+  "$stop"		{yylval.fileline = CRELINE(); return yD_STOP;}
+  "$time"		{yylval.fileline = CRELINE(); return yD_TIME;}
+  "$timeskew"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
+  "$width"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
+  "$write"		{yylval.fileline = CRELINE(); return yD_WRITE;}
+  /*     Keywords */
+  "always"		{yylval.fileline = CRELINE(); return yALWAYS;}
+  "and"			{yylval.fileline = CRELINE(); return yAND;}
+  "assign"		{yylval.fileline = CRELINE(); return yASSIGN;}
+  "begin"		{yylval.fileline = CRELINE(); return yBBEGIN;}
+  "buf"			{yylval.fileline = CRELINE(); return yBUF;}
+  "case"		{yylval.fileline = CRELINE(); return yCASE;}
+  "casex"		{yylval.fileline = CRELINE(); return yCASEX;}
+  "casez"		{yylval.fileline = CRELINE(); return yCASEZ;}
+  "default"		{yylval.fileline = CRELINE(); return yDEFAULT;}
+  "defparam"		{yylval.fileline = CRELINE(); return yDEFPARAM;}
+  "else"		{yylval.fileline = CRELINE(); return yELSE;}
+  "end"			{yylval.fileline = CRELINE(); return yBEND;}
+  "endcase"		{yylval.fileline = CRELINE(); return yENDCASE;}
+  "endfunction"		{yylval.fileline = CRELINE(); return yENDFUNCTION;}
+  "endmodule"		{yylval.fileline = CRELINE(); return yENDMODULE;}
+  "endspecify"		{yylval.fileline = CRELINE(); return yENDSPECIFY;}
+  "endtask"		{yylval.fileline = CRELINE(); return yENDTASK;}
+  "for"			{yylval.fileline = CRELINE(); return yFOR;}
+  "function"		{yylval.fileline = CRELINE(); return yFUNCTION;}
+  "if"			{yylval.fileline = CRELINE(); return yIF;}
+  "initial"		{yylval.fileline = CRELINE(); return yINITIAL;}
+  "inout"		{yylval.fileline = CRELINE(); return yINOUT;}
+  "input"		{yylval.fileline = CRELINE(); return yINPUT;}
+  "integer"		{yylval.fileline = CRELINE(); return yINTEGER;}
+  "macromodule"		{yylval.fileline = CRELINE(); return yMODULE;}
+  "module"		{yylval.fileline = CRELINE(); return yMODULE;}
+  "nand"		{yylval.fileline = CRELINE(); return yNAND;}
+  "negedge"		{yylval.fileline = CRELINE(); return yNEGEDGE;}
+  "nor"			{yylval.fileline = CRELINE(); return yNOR;}
+  "not"			{yylval.fileline = CRELINE(); return yNOT;}
+  "or"			{yylval.fileline = CRELINE(); return yOR;}
+  "output"		{yylval.fileline = CRELINE(); return yOUTPUT;}
+  "parameter"		{yylval.fileline = CRELINE(); return yPARAM;}
+  "posedge"		{yylval.fileline = CRELINE(); return yPOSEDGE;}
+  "reg"			{yylval.fileline = CRELINE(); return yREG;}
+  "scalared"		{yylval.fileline = CRELINE(); return ySCALARED;}
+  "specify"		{yylval.fileline = CRELINE(); return ySPECIFY;}
+  "specparam"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
+  "supply0"		{yylval.fileline = CRELINE(); return ySUPPLY0;}
+  "supply1"		{yylval.fileline = CRELINE(); return ySUPPLY1;}
+  "task"		{yylval.fileline = CRELINE(); return yTASK;}
+  "tri"			{yylval.fileline = CRELINE(); return yTRI;}
+  "vectored"		{yylval.fileline = CRELINE(); return yVECTORED;}
+  "wire"		{yylval.fileline = CRELINE(); return yWIRE;}
+  "xnor"		{yylval.fileline = CRELINE(); return yXNOR;}
+  "xor"			{yylval.fileline = CRELINE(); return yXOR;}
+  /*     Special errors */
+  "$displayb"		{yyerrorf("Unsupported: Use $display with %%b format instead: %s",yytext);}
+  "$displayh"		{yyerrorf("Unsupported: Use $display with %%x format instead: %s",yytext);}
+  "$displayo"		{yyerrorf("Unsupported: Use $display with %%o format instead: %s",yytext);}
+  "$fdisplayb"		{yyerrorf("Unsupported: Use $fdisplay with %%b format instead: %s",yytext);}
+  "$fdisplayh"		{yyerrorf("Unsupported: Use $fdisplay with %%x format instead: %s",yytext);}
+  "$fdisplayo"		{yyerrorf("Unsupported: Use $fdisplay with %%o format instead: %s",yytext);}
+  "$fwriteb"		{yyerrorf("Unsupported: Use $fwrite with %%b format instead: %s",yytext);}
+  "$fwriteh"		{yyerrorf("Unsupported: Use $fwrite with %%x format instead: %s",yytext);}
+  "$fwriteo"		{yyerrorf("Unsupported: Use $fwrite with %%o format instead: %s",yytext);}
+  "$writeb"		{yyerrorf("Unsupported: Use $write with %%b format instead: %s",yytext);}
+  "$writeh"		{yyerrorf("Unsupported: Use $write with %%x format instead: %s",yytext);}
+  "$writeo"		{yyerrorf("Unsupported: Use $write with %%o format instead: %s",yytext);}
+  /*     Generic unsupported warnings */
+  "bufif0"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "bufif1"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "cmos"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "deassign"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "disable"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "edge"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "endprimitive"	{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "endtable"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "event"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "force"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "forever"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "fork"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "highz0"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "highz1"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "join"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "large"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "medium"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "nmos"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "notif0"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "notif1"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "pmos"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "primitive"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "pulldown"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "pullup"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "pull0"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "pull1"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "rcmos"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "real"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "realtime"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "release"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "repeat"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "rnmos"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "rpmos"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "rtran"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "rtranif0"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "rtranif1"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "small"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "strong0"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "strong1"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "table"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "time"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "tran"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "tranif0"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "tranif1"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "triand"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "trior"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "trireg"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "tri0"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "tri1"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "wait"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "wand"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "weak0"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "weak1"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "while"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+  "wor"			{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
+}
 
   /* Verilog 2001 */
-<VLG,PSL>automatic	{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-<VLG,PSL>cell		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-<VLG,PSL>config		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-<VLG,PSL>design		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-<VLG,PSL>edge		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-<VLG,PSL>endconfig	{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-<VLG,PSL>ifnone		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-<VLG,PSL>instance	{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-<VLG,PSL>liblist	{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-<VLG,PSL>noshowcancelled	{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-<VLG,PSL>pulsestyle_ondetect	{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-<VLG,PSL>pulsestyle_onevent	{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-<VLG,PSL>showcancelled	{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-<VLG,PSL>strength	{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-<VLG,PSL>unsigned	{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-<VLG,PSL>use		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
+<V01,V05,S05,PSL>{
+  /*     System Tasks */
+  "$signed"		{yylval.fileline = CRELINE(); return yD_SIGNED;}
+  "$unsigned"		{yylval.fileline = CRELINE(); return yD_UNSIGNED;}
+  /*     Keywords */
+  "endgenerate"		{yylval.fileline = CRELINE(); return yENDGENERATE;}
+  "generate"		{yylval.fileline = CRELINE(); return yGENERATE;}
+  "genvar"		{yylval.fileline = CRELINE(); return yGENVAR;}
+  "localparam"		{yylval.fileline = CRELINE(); return yLOCALPARAM;}
+  "signed"		{yylval.fileline = CRELINE(); return ySIGNED;}
+  /*     Special errors */
+  "include"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented; probably you want `include instead: %s",yytext);}
+  /*     Generic unsupported warnings */
+  "automatic"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
+  "cell"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
+  "config"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
+  "design"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
+  "endconfig"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
+  "ifnone"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
+  "incdir"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
+  "instance"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
+  "liblist"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
+  "library"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
+  "noshowcancelled"	{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
+  "pulsestyle_ondetect"	{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
+  "pulsestyle_onevent"	{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
+  "showcancelled"	{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
+  "unsigned"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
+  "use"			{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
+}
 
-  /* System Verilog */
-<VLG,PSL>alias		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>assert_strobe	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>bind		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>bit		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>break		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>byte		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>chandle	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>class		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>clocking	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>constraint	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>context	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>continue	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>dist		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>do		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>endcass	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>endclocking	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>endinterface	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>endprogram	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>endproperty	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>endsequence	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>enum		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>export		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>extends	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>extern		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>first_match	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>forkjoin	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>iff		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>import		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>inside		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>int		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>interface	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>intersect	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>join_any	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>join_none	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>local		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>logic		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>longint	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>modport	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>new		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>null		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>packed		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>priority	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>program	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>protected	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>pure		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>rand		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>randc		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>ref		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>shortint	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>shortreal	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>solve		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>static		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>string		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>struct		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>super		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>this		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>throughout	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>timeprecision	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>timeunit	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>type		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>typedef	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>unique		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>var		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>virtual	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>void		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>wait_order	{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
-<VLG,PSL>with		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented: %s",yytext);}
+  /* Verilog 2005 */
+<V05,S05,PSL>{
+  /*     Keywords */
+  "uwire"		{yylval.fileline = CRELINE(); return yWIRE;}
+}
 
-  /* Verilog, also as PSL below PSL */
-<VLG>assert		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented in non-PSL context: %s",yytext);}
-<VLG>before		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented in non-PSL context: %s",yytext);}
-<VLG>const		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented in non-PSL context: %s",yytext);}
-<VLG>cover		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented in non-PSL context: %s",yytext);}
-<VLG>property		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented in non-PSL context: %s",yytext);}
-<VLG>sequence		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented in non-PSL context: %s",yytext);}
-<VLG>union		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented in non-PSL context: %s",yytext);}
-<VLG>within		{yyerrorf("Unsupported: SystemVerilog reserved word not implemented in non-PSL context: %s",yytext);}
+  /* System Verilog 2005 */
+<S05,PSL>{
+  /*     System Tasks */
+  "$bits"		{yylval.fileline = CRELINE(); return yD_BITS;}
+  "$countones"		{yylval.fileline = CRELINE(); return yD_COUNTONES;}
+  "$error"		{yylval.fileline = CRELINE(); return yD_ERROR;}
+  "$fatal"		{yylval.fileline = CRELINE(); return yD_FATAL;}
+  "$info"		{yylval.fileline = CRELINE(); return yD_INFO;}
+  "$isunknown"		{yylval.fileline = CRELINE(); return yD_ISUNKNOWN;}
+  "$onehot"		{yylval.fileline = CRELINE(); return yD_ONEHOT;}
+  "$onehot0"		{yylval.fileline = CRELINE(); return yD_ONEHOT0;}
+  "$warning"		{yylval.fileline = CRELINE(); return yD_WARNING;}
+  /*     Keywords */
+  "always_comb"		{yylval.fileline = CRELINE(); return yALWAYS;}
+  "always_ff"		{yylval.fileline = CRELINE(); return yALWAYS;}
+  "always_latch"	{yylval.fileline = CRELINE(); return yALWAYS;}
+  "final"		{yylval.fileline = CRELINE(); return yFINAL;}
+  /*     Generic unsupported warnings */
+  /* Note assert_strobe was in SystemVerilog 3.1, but removed for SystemVerilog 2005 */
+  "alias"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "bind"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "bins"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "binsof"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "bit"			{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "break"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "byte"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "chandle"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "class"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "clocking"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "constraint"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "context"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "continue"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "covergroup"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "coverpoint"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "cross"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "dist"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "do"			{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "endcass"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "endclocking"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "endgroup"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "endinterface"	{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "endpackage"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "endprogram"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "endproperty"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "endsequence"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "enum"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "expect"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "export"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "extends"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "extern"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "first_match"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "foreach"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "forkjoin"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "iff"			{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "ignore_bins"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "illegal_bins"	{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "import"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "inside"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "int"			{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "interface"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "intersect"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "join_any"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "join_none"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "local"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "logic"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "longint"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "matches"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "modport"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "new"			{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "null"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "package"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "packed"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "priority"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "program"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "protected"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "pure"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "rand"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "randc"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "randcase"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "randsequence"	{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "ref"			{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "return"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "shortint"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "shortreal"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "solve"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "static"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "string"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "struct"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "super"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "tagged"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "this"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "throughout"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "timeprecision"	{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "timeunit"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "type"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "typedef"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "unique"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "var"			{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "virtual"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "void"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "wait_order"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "wildcard"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "with"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+}
 
-  /* PSL reserved */
- /*<PSL>A		{yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext);} */
- /*<PSL>AF		{yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext);} */
- /*<PSL>AG		{yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext);} */
- /*<PSL>AX		{yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext);} */
- /*<PSL>E		{yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext);} */
- /*<PSL>EF		{yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext);} */
- /*<PSL>EG		{yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext);} */
- /*<PSL>EX		{yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext);} */
- /*<PSL>F		{yylval.fileline = CRELINE(); return yEVENTUALLYB; } */
- /*<PSL>G		{yylval.fileline = CRELINE(); return yALWAYS; } */
- /*<PSL>U		{yylval.fileline = CRELINE(); return yUNTILB; } */
- /*<PSL>W		{yylval.fileline = CRELINE(); return yUNTIL; } */
- /*<PSL>X		{yylval.fileline = CRELINE(); return yNEXT; } */
- /*<PSL>X!		{yylval.fileline = CRELINE(); return yNEXTB; } */
-<PSL>%for		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>%if		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>abort		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>assume_guarantee	{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} //Unsup in other tools
-<PSL>before		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>before!		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>before!_		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>before_		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>boolean		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>const		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>endpoint		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>eventually!	{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>fairness		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} //Unsup in other tools
-<PSL>fell		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>forall		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} //Unsup in other tools
-<PSL>in			{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>inf		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>inherit		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} //Unsup in other tools
-<PSL>never		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>next		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>next!		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>next_a		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>next_a!		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>next_e		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>next_e!		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>next_event		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>next_event!	{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>next_event_a	{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>next_event_a!	{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>next_event_e	{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>next_event_e!	{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>prev		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>property		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>restrict		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>restrict_guarantee	{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} //Unsup in other tools
-<PSL>rose		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>sequence		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>stable		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>strong		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} //Unsup in other tools
-<PSL>union		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>until		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>until!		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>until!_		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>until_		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>vmode		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} //Unsup in other tools
-<PSL>vprop		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} //Unsup in other tools
-<PSL>vunit		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
-<PSL>within		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  /* SystemVerilog ONLY not PSL; different rules for PSL as specified below */
+<S05>{
+  /*     Keywords */
+  "assert"		{yylval.fileline = CRELINE(); return yASSERT;}
+  /*     Generic unsupported warnings */
+  "assume"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented in non-PSL context: %s",yytext);}
+  "before"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented in non-PSL context: %s",yytext);}
+  "const"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented in non-PSL context: %s",yytext);}
+  "cover"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented in non-PSL context: %s",yytext);}
+  "property"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented in non-PSL context: %s",yytext);}
+  "sequence"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented in non-PSL context: %s",yytext);}
+  "union"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented in non-PSL context: %s",yytext);}
+  "within"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented in non-PSL context: %s",yytext);}
+}
 
-  /* Converted from //{cmt}verilator ...{cmt} by vpp */
-<VLG,PSL>"/*verilator clock_enable*/"		{yylval.fileline = CRELINE(); return yVL_CLOCK_ENABLE;}
-<VLG,PSL>"/*verilator coverage_block_off*/"	{yylval.fileline = CRELINE(); return yVL_COVER_OFF;}
-<VLG,PSL>"/*verilator full_case*/"		{yylval.fileline = CRELINE(); return yVL_FULL_CASE;}
-<VLG,PSL>"/*verilator inline_module*/"		{yylval.fileline = CRELINE(); return yVL_INLINE_MODULE;}
-<VLG,PSL>"/*verilator no_inline_module*/"	{yylval.fileline = CRELINE(); return yVL_NO_INLINE_MODULE;}
-<VLG,PSL>"/*verilator no_inline_task*/"		{yylval.fileline = CRELINE(); return yVL_NO_INLINE_TASK;}
-<VLG,PSL>"/*verilator parallel_case*/"		{yylval.fileline = CRELINE(); return yVL_PARALLEL_CASE;}
-<VLG,PSL>"/*verilator public*/"			{yylval.fileline = CRELINE(); return yVL_PUBLIC;}
-<VLG,PSL>"/*verilator public_module*/"		{yylval.fileline = CRELINE(); return yVL_PUBLIC_MODULE;}
-<VLG,PSL>"/*verilator sc_clock*/"		{yylval.fileline = CRELINE(); return yVL_CLOCK;}
-<VLG,PSL>"/*verilator systemc_clock*/"		{yylval.fileline = CRELINE(); return yVL_CLOCK;}
-<VLG,PSL>"/*verilator tracing_off*/"		{yylval.fileline = CRELINE(); return yVL_TRACING_OFF;}
-<VLG,PSL>"/*verilator tracing_on*/"		{yylval.fileline = CRELINE(); return yVL_TRACING_ON;}
-<VLG,PSL>"/*verilator lint_off"[^*]*"*/"	{V3Read::verilatorCmtLint(yytext, true); }
-<VLG,PSL>"/*verilator lint_on"[^*]*"*/"		{V3Read::verilatorCmtLint(yytext, false); }
-<VLG,PSL>"/*"[^*]*"*/"				{V3Read::verilatorCmtBad(yytext); }
+  /* Default PLI rule */
+<V95,V01,V05,S05,PSL>{
+  "$"[a-zA-Z_$]+	{yyerrorf("Unsupported or unknown PLI call: %s",yytext);}
+}
 
-<VLG,PSL>"&&"		{yylval.fileline = CRELINE(); return yANDAND;}
-<VLG,PSL>"||"		{yylval.fileline = CRELINE(); return yOROR;}
-<VLG,PSL>"<="		{yylval.fileline = CRELINE(); return yLTE;}
-<VLG,PSL>">="		{yylval.fileline = CRELINE(); return yGTE;}
-<VLG,PSL>"<<<"		{yylval.fileline = CRELINE(); return ySLEFT;}
-<VLG,PSL>"<<"		{yylval.fileline = CRELINE(); return ySLEFT;}
-<VLG,PSL>">>>"		{yylval.fileline = CRELINE(); return ySSRIGHT;}
-<VLG,PSL>">>"		{yylval.fileline = CRELINE(); return ySRIGHT;}
-<VLG,PSL>"=="		{yylval.fileline = CRELINE(); return yEQUAL;}
-<VLG,PSL>"!="		{yylval.fileline = CRELINE(); return yNOTEQUAL;}
-<VLG,PSL>"==="		{yylval.fileline = CRELINE(); return yCASEEQUAL;}
-<VLG,PSL>"!=="		{yylval.fileline = CRELINE(); return yCASENOTEQUAL;}
-<VLG,PSL>"^~"		{yylval.fileline = CRELINE(); return yOP_XNOR;}
-<VLG,PSL>"~^"		{yylval.fileline = CRELINE(); return yOP_XNOR;}
-<VLG,PSL>"~&"		{yylval.fileline = CRELINE(); return yOP_NAND;}
-<VLG,PSL>"~|"		{yylval.fileline = CRELINE(); return yOP_NOR;}
-<VLG,PSL>"**"		{yylval.fileline = CRELINE(); return yPOW;}
-<VLG,PSL>"+:"		{yylval.fileline = CRELINE(); return yPLUSCOLON;}
-<VLG,PSL>"-:"		{yylval.fileline = CRELINE(); return yMINUSCOLON;}
+  /************************************************************************/
+  /* PSL */
 
-<PSL>"{"		{yylval.fileline = CRELINE(); return yPSL_BRA;}	// Avoid parser hitting concatenate.
-<PSL>"}"		{yylval.fileline = CRELINE(); return yPSL_KET;}	// Avoid parser hitting concatenate.
-<PSL>"->"		{yylval.fileline = CRELINE(); return yOP_LOGIF;}
-<PSL>"<->"		{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} //Unsup in other tools
-<PSL>"[*"		{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yBRA_STAR
-<PSL>"[*]"		{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yBRA_STAR_KET
-<PSL>"[+]"		{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yBRA_PLUS_KET
-<PSL>"[->"		{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yBRA_MINUS_GT
-<PSL>"[->]"		{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yBRA_MINUS_GT_KET
-<PSL>"[="		{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yBRA_EQ
-<PSL>"|->"		{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yOR_MINUS_GT
-<PSL>"|=>"		{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yOR_EQ_GT
+  /*Entry into PSL; mode change */
+<V95,V01,V05,S05>{
+  "psl"			{ yy_push_state(PSL); yylval.fileline = CRELINE(); return yPSL; }
+}
 
-<VLG,PSL>{escid}	{  int i;
+<PSL>{
+  /*     Special things */
+  "psl"			{ ; }	// 'psl' may occur in middle of statement, so easier just to suppress
+  /*     Keywords */
+  "assert"		{yylval.fileline = CRELINE(); return yPSL_ASSERT;}
+  "assume"		{yylval.fileline = CRELINE(); return yPSL_ASSERT;} //==assert
+  "before_!"		{yyerrorf("Illegal syntax, use before!_ instead of %s",yytext);}
+  "clock"		{yylval.fileline = CRELINE(); return yCLOCK;}
+  "countones"		{yylval.fileline = CRELINE(); return yD_COUNTONES;}
+  "cover"		{yylval.fileline = CRELINE(); return yCOVER;}
+  "isunknown"		{yylval.fileline = CRELINE(); return yD_ISUNKNOWN;}
+  "onehot"		{yylval.fileline = CRELINE(); return yD_ONEHOT; }
+  "onehot0"		{yylval.fileline = CRELINE(); return yD_ONEHOT0; }
+  "until_!"		{yyerrorf("Illegal syntax, use until!_ instead of %s",yytext);}
+  "report"		{yylval.fileline = CRELINE(); return yREPORT; }
+  "true"		{yylval.fileline = CRELINE(); return yTRUE; }
+  /*     Generic unsupported warnings */
+  /*"A"			{yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext);} */
+  /*"AF"		{yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext);} */
+  /*"AG"		{yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext);} */
+  /*"AX"		{yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext);} */
+  /*"E"			{yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext);} */
+  /*"EF"		{yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext);} */
+  /*"EG"		{yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext);} */
+  /*"EX"		{yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext);} */
+  /*"F"			{yylval.fileline = CRELINE(); return yEVENTUALLYB; } */
+  /*"G"			{yylval.fileline = CRELINE(); return yALWAYS; } */
+  /*"U"			{yylval.fileline = CRELINE(); return yUNTILB; } */
+  /*"W"			{yylval.fileline = CRELINE(); return yUNTIL; } */
+  /*"X"			{yylval.fileline = CRELINE(); return yNEXT; } */
+  /*"X!"		{yylval.fileline = CRELINE(); return yNEXTB; } */
+  "%for"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "%if"			{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "abort"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "assume_guarantee"	{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} //Unsup in other tools
+  "before"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "before!"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "before!_"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "before_"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "boolean"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "const"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "endpoint"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "eventually!"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "fairness"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} //Unsup in other tools
+  "fell"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "forall"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} //Unsup in other tools
+  "in"			{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "inf"			{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "inherit"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} //Unsup in other tools
+  "never"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "next"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "next!"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "next_a"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "next_a!"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "next_e"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "next_e!"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "next_event"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "next_event!"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "next_event_a"	{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "next_event_a!"	{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "next_event_e"	{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "next_event_e!"	{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "prev"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "property"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "restrict"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "restrict_guarantee"	{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} //Unsup in other tools
+  "rose"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "sequence"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "stable"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "strong"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} //Unsup in other tools
+  "union"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "until"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "until!"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "until!_"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "until_"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "vmode"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} //Unsup in other tools
+  "vprop"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} //Unsup in other tools
+  "vunit"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+  "within"		{yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
+}
+
+  /************************************************************************/
+  /* Meta comments */
+
+  /* Converted from //{cmt}verilator ...{cmt} by preprocessor */
+<V95,V01,V05,S05,PSL>{
+  "/*verilator clock_enable*/"		{yylval.fileline = CRELINE(); return yVL_CLOCK_ENABLE;}
+  "/*verilator coverage_block_off*/"	{yylval.fileline = CRELINE(); return yVL_COVER_OFF;}
+  "/*verilator full_case*/"		{yylval.fileline = CRELINE(); return yVL_FULL_CASE;}
+  "/*verilator inline_module*/"		{yylval.fileline = CRELINE(); return yVL_INLINE_MODULE;}
+  "/*verilator no_inline_module*/"	{yylval.fileline = CRELINE(); return yVL_NO_INLINE_MODULE;}
+  "/*verilator no_inline_task*/"	{yylval.fileline = CRELINE(); return yVL_NO_INLINE_TASK;}
+  "/*verilator parallel_case*/"		{yylval.fileline = CRELINE(); return yVL_PARALLEL_CASE;}
+  "/*verilator public*/"		{yylval.fileline = CRELINE(); return yVL_PUBLIC;}
+  "/*verilator public_flat*/"		{yylval.fileline = CRELINE(); return yVL_PUBLIC_FLAT;}
+  "/*verilator public_module*/"		{yylval.fileline = CRELINE(); return yVL_PUBLIC_MODULE;}
+  "/*verilator sc_clock*/"		{yylval.fileline = CRELINE(); return yVL_CLOCK;}
+  "/*verilator isolate_assignments*/"	{yylval.fileline = CRELINE(); return yVL_ISOLATE_ASSIGNMENTS;}
+  "/*verilator systemc_clock*/"		{yylval.fileline = CRELINE(); return yVL_CLOCK;}
+  "/*verilator tracing_off*/"		{yylval.fileline = CRELINE(); return yVL_TRACING_OFF;}
+  "/*verilator tracing_on*/"		{yylval.fileline = CRELINE(); return yVL_TRACING_ON;}
+  "/*verilator lint_off"[^*]*"*/"	{V3Read::verilatorCmtLint(yytext, true); }
+  "/*verilator lint_on"[^*]*"*/"	{V3Read::verilatorCmtLint(yytext, false); }
+
+  "/*"[^*]*"*/"				{V3Read::verilatorCmtBad(yytext); }
+}
+
+  /************************************************************************/
+  /* Operators */
+
+  /* Verilog 1995 Operators */
+<V95,V01,V05,S05,PSL>{
+  "&&"			{yylval.fileline = CRELINE(); return yANDAND;}
+  "||"			{yylval.fileline = CRELINE(); return yOROR;}
+  "<="			{yylval.fileline = CRELINE(); return yLTE;}
+  ">="			{yylval.fileline = CRELINE(); return yGTE;}
+  "<<"			{yylval.fileline = CRELINE(); return ySLEFT;}
+  ">>"			{yylval.fileline = CRELINE(); return ySRIGHT;}
+  "=="			{yylval.fileline = CRELINE(); return yEQUAL;}
+  "!="			{yylval.fileline = CRELINE(); return yNOTEQUAL;}
+  "==="			{yylval.fileline = CRELINE(); return yCASEEQUAL;}
+  "!=="			{yylval.fileline = CRELINE(); return yCASENOTEQUAL;}
+  "^~"			{yylval.fileline = CRELINE(); return yOP_XNOR;}
+  "~^"			{yylval.fileline = CRELINE(); return yOP_XNOR;}
+  "~&"			{yylval.fileline = CRELINE(); return yOP_NAND;}
+  "~|"			{yylval.fileline = CRELINE(); return yOP_NOR;}
+}
+
+  /* Verilog 2001 Operators */
+<V01,V05,S05,PSL>{
+  "<<<"			{yylval.fileline = CRELINE(); return ySLEFT;}
+  ">>>"			{yylval.fileline = CRELINE(); return ySSRIGHT;}
+  "**"			{yylval.fileline = CRELINE(); return yPOW;}
+  "+:"			{yylval.fileline = CRELINE(); return yPLUSCOLON;}
+  "-:"			{yylval.fileline = CRELINE(); return yMINUSCOLON;}
+}
+
+  /* PSL Operators */
+<PSL>{
+  "{"			{yylval.fileline = CRELINE(); return yPSL_BRA;}	// Avoid parser hitting concatenate.
+  "}"			{yylval.fileline = CRELINE(); return yPSL_KET;}	// Avoid parser hitting concatenate.
+  "->"			{yylval.fileline = CRELINE(); return yOP_LOGIF;}
+  "<->"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} //Unsup in other tools
+  "[*"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yBRA_STAR
+  "[*]"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yBRA_STAR_KET
+  "[+]"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yBRA_PLUS_KET
+  "[->"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yBRA_MINUS_GT
+  "[->]"		{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yBRA_MINUS_GT_KET
+  "[="			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yBRA_EQ
+  "|->"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yOR_MINUS_GT
+  "|=>"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yOR_EQ_GT
+}
+
+  /* Identifiers and numbers */
+<V95,V01,V05,S05,PSL>{
+  {escid}		{  int i;
 			   for (i=0; yytext[i] != 0; i++)
 			       if (!isalnum(yytext[i]))
 				   yytext[i] = '_';
@@ -502,42 +592,43 @@ escid	\\[^ \t\f\r\n]+
 			   return yID;
 			 }
 
-<VLG,PSL>{id}		{  yylval.strp = V3Read::newString(yytext);
+  {id}			{  yylval.strp = V3Read::newString(yytext);
 			   return yID;
 			 }
 
-<VLG,PSL>\"[^\"\\]*\"	{  yylval.strp = V3Read::newString(yytext+1,yyleng-2);
+  \"[^\"\\]*\"		{  yylval.strp = V3Read::newString(yytext+1,yyleng-2);
 			   return ySTRING;
 			}
-<VLG,PSL>\" 		{ yy_push_state(STRING); yymore(); }
+  \" 			{ yy_push_state(STRING); yymore(); }
 
 
-<VLG,PSL>[0-9]*?['']s?[bcodhBCODH][ \t]*[A-Fa-f0-9xXzZ_?]*	{
+  [0-9]*?['']s?[bcodhBCODH][ \t]*[A-Fa-f0-9xXzZ_?]*	{
 			  yylval.nump = V3Read::newNumber(V3Read::fileline(),(char*)yytext);
                           return yINTNUM;
 			}
-<VLG,PSL>[0-9]*?['']s?[01xXzZ]	{	/* SystemVerilog */
+  [0-9]*?['']s?[01xXzZ]	{	/* SystemVerilog */
 			  yylval.nump = V3Read::newNumber(V3Read::fileline(),(char*)yytext);
                           return yINTNUM;
 			}
-<VLG,PSL>[0-9]+[_0-9]*[ \t]*['']s?[bcodhBCODH]?[ \t]*[A-Fa-f0-9xXzZ_?]*	{
+  [0-9]+[_0-9]*[ \t]*['']s?[bcodhBCODH]?[ \t]*[A-Fa-f0-9xXzZ_?]*	{
 			  yylval.nump = V3Read::newNumber(V3Read::fileline(),(char*)yytext);
                           return yINTNUM;
 			}
-<VLG,PSL>[0-9]*		{ yylval.nump = V3Read::newNumber(V3Read::fileline(),(char*)yytext);
+  [0-9]*		{ yylval.nump = V3Read::newNumber(V3Read::fileline(),(char*)yytext);
                           return yINTNUM;
 			}
-<VLG,PSL>[-+]?[0-9]+(\.[0-9]+)([eE][-+]?[0-9]+)? {
+  [-+]?[0-9]+(\.[0-9]+)([eE][-+]?[0-9]+)? {
     			  yylval.cdouble = 0;  /* Only for delays, not used yet */
                           return yFLOATNUM;
 			}
-<VLG,PSL>[-+]?[0-9]+(\.[0-9]+)?([eE][-+]?[0-9]+) {
+  [-+]?[0-9]+(\.[0-9]+)?([eE][-+]?[0-9]+) {
     			  yylval.cdouble = 0;  /* Only for delays, not used yet */
                           return yFLOATNUM;
 			}
 
-<VLG,PSL>"`timescale"{ws}+[^\n]*	{}
-<VLG,PSL>"`line"{ws}+[^\n]*\n		{V3Read::ppline(yytext);}
+  "`timescale"{ws}+[^\n]*	{}
+  "`line"{ws}+[^\n]*\n		{V3Read::ppline(yytext);}
+}
 
   /************************************************************************/
   /* STRINGS */
@@ -552,8 +643,8 @@ escid	\\[^ \t\f\r\n]+
   /************************************************************************/
   /* Common for all SYSC header states */
   /* OPTIMIZE: we return one per line, make it one for the entire block */
-<VLG,PSL,SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{
-  [ \t]*"`verilog"			{ BEGIN VLG; }
+<V95,V01,V05,S05,PSL,SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{
+  [ \t]*"`verilog"			{ BEGIN V95; }
   [ \t]*"`psl"				{ if (V3Read::optPsl()) { BEGIN PSL; } else { BEGIN IGNORE; } }
   [ \t]*"`systemc_header"		{ BEGIN SYSCHDR; }
   [ \t]*"`systemc_ctor"			{ BEGIN SYSCCTOR; }
@@ -561,6 +652,14 @@ escid	\\[^ \t\f\r\n]+
   [ \t]*"`systemc_interface"		{ BEGIN SYSCINT; }
   [ \t]*"`systemc_implementation"	{ BEGIN SYSCIMP; }
   [ \t]*"`systemc_imp_header"		{ BEGIN SYSCIMPH; }
+
+  [ \t]*"`begin_keywords"[ \t]*\"1364-1995\"		{ yy_push_state(V95); V3Read::pushBeginKeywords();}
+  [ \t]*"`begin_keywords"[ \t]*\"1364-2001\"		{ yy_push_state(V01); V3Read::pushBeginKeywords();}
+  [ \t]*"`begin_keywords"[ \t]*\"1364-2001-noconfig\"	{ yy_push_state(V01); V3Read::pushBeginKeywords();}
+  [ \t]*"`begin_keywords"[ \t]*\"1364-2005\"		{ yy_push_state(V05); V3Read::pushBeginKeywords();}
+  [ \t]*"`begin_keywords"[ \t]*\"1800-2005\"		{ yy_push_state(S05); V3Read::pushBeginKeywords();}
+  [ \t]*"`end_keywords"					{ yy_pop_state(); if (!V3Read::popBeginKeywords()) yyerrorf("`end_keywords when not inside `begin_keywords block"); }
+
   "`line"[ \t][^\n]*\n			{V3Read::ppline(yytext);}
 }
 
@@ -572,18 +671,24 @@ escid	\\[^ \t\f\r\n]+
 <SYSCDTOR>[ \t]*[^` \t\n][^\n]*\n	{ NEXTLINE(); yylval.strp = V3Read::newString(yytext); return ySCDTOR;}
 <IGNORE>[ \t]*[^` \t\n][^\n]*\n		{ NEXTLINE(); }
 
-<SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>[ \t]*\n	{ NEXTLINE(); yymore();}
-<SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>\r		;
+  /* Pick up text-type data */
+<SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{
+  [ \t]*\n		{ NEXTLINE(); yymore();}
+  \r			;
+}
 
   /************************************************************************/
   /* Default rules - leave last */
 
-<VLG,PSL>"`"[a-zA-Z_0-9]+		{ yyerrorf("Define or directive not defined: %s",yytext); }
+<V95,V01,V05,S05,PSL>{
+  "`"[a-zA-Z_0-9]+	{ yyerrorf("Define or directive not defined: %s",yytext); }
 
-<VLG,PSL>"//"[^\n]+	{ }  /* throw away single line comments */
+  "//"[^\n]+		{ }  /* throw away single line comments */
 
-<VLG,PSL>.		{yylval.fileline = CRELINE(); return yytext[0];}	/* return single char ops. */
+  .			{yylval.fileline = CRELINE(); return yytext[0];}	/* return single char ops. */
+}
 
+  /* Catch all - absolutely last */
 <*>.|\n     		{ yyerrorf("Missing verilog.l rule: Default rule invoked in state %d: %s", YY_START, yytext); }
 %%
 

src/verilog.y

@@ -60,6 +60,11 @@ public:
     static AstVar*  createVariable(FileLine* fileline, string name, AstRange* arrayp);
     static AstNode* createSupplyExpr(FileLine* fileline, string name, int value);
     static AstText* createTextQuoted(FileLine* fileline, string text);
+    static AstDisplay* createDisplayError(FileLine* fileline) {
+	AstDisplay* nodep = new AstDisplay(fileline,AstDisplayType::ERROR,  "", NULL,NULL);
+	nodep->addNext(new AstStop(fileline)); 
+	return nodep;
+    }
     static string   deQuote(FileLine* fileline, string text);
 };
 
@@ -104,6 +109,7 @@ class AstSenTree;
     AstCase*	casep;
     AstCaseItem* caseitemp;
     AstConst*	constp;
+    AstFunc*	funcp;
     AstFuncRef*	funcrefp;
     AstModule*	modulep;
     AstPin*	pinp;
@@ -139,15 +145,20 @@ class AstSenTree;
 %token<fileline>	yREPORT		"report"
 %token<fileline>	yTRUE		"true"
 
+%token<fileline>	yPSL_ASSERT	"PSL assert"
+
 %token<fileline>	yD_BITS		"$bits"
 %token<fileline>	yD_C		"$c"
 %token<fileline>	yD_COUNTONES	"$countones"
 %token<fileline>	yD_DISPLAY	"$display"
+%token<fileline>	yD_ERROR	"$error"
+%token<fileline>	yD_FATAL	"$fatal"
 %token<fileline>	yD_FCLOSE	"$fclose"
 %token<fileline>	yD_FDISPLAY	"$fdisplay"
 %token<fileline>	yD_FINISH	"$finish"
 %token<fileline>	yD_FOPEN	"$fopen"
 %token<fileline>	yD_FWRITE	"$fwrite"
+%token<fileline>	yD_INFO		"$info"
 %token<fileline>	yD_ISUNKNOWN	"$isunknown"
 %token<fileline>	yD_ONEHOT	"$onehot"
 %token<fileline>	yD_ONEHOT0	"$onehot0"
@@ -157,6 +168,7 @@ class AstSenTree;
 %token<fileline>	yD_STOP		"$stop"
 %token<fileline>	yD_TIME		"$time"
 %token<fileline>	yD_UNSIGNED	"$unsigned"
+%token<fileline>	yD_WARNING	"$warning"
 %token<fileline>	yD_WRITE	"$write"
 
 %token<fileline>	yVL_CLOCK		"/*verilator sc_clock*/"
@@ -168,7 +180,9 @@ class AstSenTree;
 %token<fileline>	yVL_NO_INLINE_TASK	"/*verilator no_inline_task*/"
 %token<fileline>	yVL_PARALLEL_CASE	"/*verilator parallel_case*/"
 %token<fileline>	yVL_PUBLIC		"/*verilator public*/"
+%token<fileline>	yVL_PUBLIC_FLAT		"/*verilator public_flat*/"
 %token<fileline>	yVL_PUBLIC_MODULE	"/*verilator public_module*/"
+%token<fileline>	yVL_ISOLATE_ASSIGNMENTS	"/*verilator isolate_assignments*/"
 %token<fileline>	yVL_TRACING_OFF		"/*verilator tracing_off*/"
 %token<fileline>	yVL_TRACING_ON		"/*verilator tracing_on*/"
 
@@ -229,7 +243,8 @@ class AstSenTree;
 %type<nodep>	defpList defpOne
 %type<sentreep>	sensitivityE
 %type<senitemp>	senList senitem senitemEdge
-%type<nodep>	stmtBlock stmtList stmt stateCaseForIf
+%type<nodep>	stmtBlock stmtList stmt labeledStmt stateCaseForIf
+%type<nodep>	assertStmt
 %type<beginp>	beginNamed
 %type<casep>	caseStmt
 %type<caseitemp> caseList
@@ -245,13 +260,16 @@ class AstSenTree;
 %type<nodep>	idDotted
 %type<nodep>	strAsInt strAsText concIdList
 %type<nodep>	taskDecl
-%type<nodep>	varDeclList funcDecl funcVarList funcVar
+%type<nodep>	varDeclList
+%type<funcp>	funcDecl
+%type<nodep>	funcBody funcVarList funcVar
 %type<rangep>	funcRange
 %type<nodep>	gateDecl
 %type<nodep>	gateBufList gateNotList gateAndList gateNandList
 %type<nodep>	gateOrList gateNorList gateXorList gateXnorList
 %type<assignwp>	gateBuf gateNot gateAnd gateNand gateOr gateNor gateXor gateXnor
 %type<nodep>	gateAndPinList gateOrPinList gateXorPinList
+%type<nodep>	commaEListE
 
 %type<nodep>	pslStmt pslDir pslDirOne pslProp
 %type<nodep>	pslDecl
@@ -518,7 +536,9 @@ sigAttrList:	sigAttr					{}
 
 sigAttr:	yVL_CLOCK				{ V3Parse::s_varAttrp->attrScClocked(true); }
 	|	yVL_CLOCK_ENABLE			{ V3Parse::s_varAttrp->attrClockEn(true); }
-	|	yVL_PUBLIC				{ V3Parse::s_varAttrp->sigPublic(true); }
+	|	yVL_PUBLIC				{ V3Parse::s_varAttrp->sigPublic(true); V3Parse::s_varAttrp->sigModPublic(true); }
+	|	yVL_PUBLIC_FLAT				{ V3Parse::s_varAttrp->sigPublic(true); }
+	|	yVL_ISOLATE_ASSIGNMENTS			{ V3Parse::s_varAttrp->attrIsolateAssign(true); }
 	;
 
 sigList:	onesig					{ $$ = $1; }
@@ -645,6 +665,9 @@ stmtList:	stmtBlock				{ $$ = $1; }
 	;
 
 stmt:		';'					{ $$ = NULL; }
+	|	labeledStmt				{ $$ = $1; }
+	|	yID ':' labeledStmt			{ $$ = new AstBegin($2, *$1, $3); }  /*S05 block creation rule*/
+
 	|	varRefDotBit yLTE delayE expr ';'	{ $$ = new AstAssignDly($2,$1,$4); }
 	|	varRefDotBit '=' delayE expr ';'	{ $$ = new AstAssign($2,$1,$4); }
 	|	varRefDotBit '=' yD_FOPEN '(' expr ',' expr ')' ';'	{ $$ = new AstFOpen($3,$1,$5,$7); }
@@ -659,21 +682,31 @@ stmt:		';'					{ $$ = NULL; }
 	|	stateCaseForIf				{ $$ = $1; }
 	|	taskRef ';' 				{ $$ = $1; }
 
-	|	yD_DISPLAY  ';'					{ $$ = new AstDisplay($1,'\n',"",NULL,NULL); }
-	|	yD_DISPLAY  '(' ySTRING ')' ';'			{ $$ = new AstDisplay($1,'\n',*$3,NULL,NULL); }
-	|	yD_DISPLAY  '(' ySTRING ',' eList ')' ';'	{ $$ = new AstDisplay($1,'\n',*$3,NULL,$5); }
-	|	yD_WRITE    '(' ySTRING ')' ';'			{ $$ = new AstDisplay($1,'\0',*$3,NULL,NULL); }
-	|	yD_WRITE    '(' ySTRING ',' eList ')' ';' 	{ $$ = new AstDisplay($1,'\0',*$3,NULL,$5); }
-	|	yD_FDISPLAY '(' varRefDotBit ',' ySTRING ')' ';'		{ $$ = new AstDisplay($1,'\n',*$5,$3,NULL); }
-	|	yD_FDISPLAY '(' varRefDotBit ',' ySTRING ',' eList ')' ';' 	{ $$ = new AstDisplay($1,'\n',*$5,$3,$7); }
-	|	yD_FWRITE   '(' varRefDotBit ',' ySTRING ')' ';'		{ $$ = new AstDisplay($1,'\0',*$5,$3,NULL); }
-	|	yD_FWRITE   '(' varRefDotBit ',' ySTRING ',' eList ')' ';'	{ $$ = new AstDisplay($1,'\0',*$5,$3,$7); }
+	|	yD_DISPLAY  ';'							{ $$ = new AstDisplay($1,AstDisplayType::DISPLAY,"", NULL,NULL); }
+	|	yD_DISPLAY  '(' ySTRING commaEListE ')' ';'			{ $$ = new AstDisplay($1,AstDisplayType::DISPLAY,*$3,NULL,$4); }
+	|	yD_WRITE    '(' ySTRING commaEListE ')' ';'			{ $$ = new AstDisplay($1,AstDisplayType::WRITE,  *$3,NULL,$4); }
+	|	yD_FDISPLAY '(' varRefDotBit ',' ySTRING commaEListE ')' ';' 	{ $$ = new AstDisplay($1,AstDisplayType::DISPLAY,*$5,$3,$6); }
+	|	yD_FWRITE   '(' varRefDotBit ',' ySTRING commaEListE ')' ';'	{ $$ = new AstDisplay($1,AstDisplayType::WRITE,  *$5,$3,$6); }
+	|	yD_INFO	    ';'							{ $$ = new AstDisplay($1,AstDisplayType::INFO,   "", NULL,NULL); }
+	|	yD_INFO	    '(' ySTRING commaEListE ')' ';'			{ $$ = new AstDisplay($1,AstDisplayType::INFO,   *$3,NULL,$4); }
+	|	yD_WARNING  ';'							{ $$ = new AstDisplay($1,AstDisplayType::WARNING,"", NULL,NULL); }
+	|	yD_WARNING  '(' ySTRING commaEListE ')' ';'			{ $$ = new AstDisplay($1,AstDisplayType::WARNING,*$3,NULL,$4); }
+	|	yD_ERROR    ';'							{ $$ = V3Parse::createDisplayError($1); }
+	|	yD_ERROR    '(' ySTRING commaEListE ')' ';'			{ $$ = new AstDisplay($1,AstDisplayType::ERROR,  *$3,NULL,$4);   $$->addNext(new AstStop($1)); }
+	|	yD_FATAL    ';'							{ $$ = new AstDisplay($1,AstDisplayType::FATAL,  "", NULL,NULL); $$->addNext(new AstStop($1)); }
+	|	yD_FATAL    '(' expr ')' ';'					{ $$ = new AstDisplay($1,AstDisplayType::FATAL,  "", NULL,NULL); $$->addNext(new AstStop($1)); }
+	|	yD_FATAL    '(' expr ',' ySTRING commaEListE ')' ';'		{ $$ = new AstDisplay($1,AstDisplayType::FATAL,  *$5,NULL,$6);   $$->addNext(new AstStop($1)); }
+
 	|	yD_READMEMB '(' expr ',' varRefMem ')' ';'			{ $$ = new AstReadMem($1,false,$3,$5,NULL,NULL); }
 	|	yD_READMEMB '(' expr ',' varRefMem ',' expr ')' ';'		{ $$ = new AstReadMem($1,false,$3,$5,$7,NULL); }
 	|	yD_READMEMB '(' expr ',' varRefMem ',' expr ',' expr ')' ';'	{ $$ = new AstReadMem($1,false,$3,$5,$7,$9); }
 	|	yD_READMEMH '(' expr ',' varRefMem ')' ';'			{ $$ = new AstReadMem($1,true, $3,$5,NULL,NULL); }
 	|	yD_READMEMH '(' expr ',' varRefMem ',' expr ')' ';'		{ $$ = new AstReadMem($1,true, $3,$5,$7,NULL); }
 	|	yD_READMEMH '(' expr ',' varRefMem ',' expr ',' expr ')' ';'	{ $$ = new AstReadMem($1,true, $3,$5,$7,$9); }
+
+	;
+
+labeledStmt:	assertStmt				{ $$ = $1; }
 	;
 
 stateCaseForIf: caseStmt caseAttrE caseList yENDCASE	{ $$ = $1; $1->addItemsp($3); }
@@ -685,6 +718,11 @@ stateCaseForIf: caseStmt caseAttrE caseList yENDCASE	{ $$ = $1; $1->addItemsp($3
 									  ,$13);}
 	;
 
+assertStmt:	yASSERT '(' expr ')' stmtBlock %prec yLOWER_THAN_ELSE	{ $$ = new AstVAssert($1,$3,$5, V3Parse::createDisplayError($1)); }
+	|	yASSERT '(' expr ')'           yELSE stmtBlock		{ $$ = new AstVAssert($1,$3,NULL,$6); }
+	|	yASSERT '(' expr ')' stmtBlock yELSE stmtBlock		{ $$ = new AstVAssert($1,$3,$5,$7);   }
+	;
+
 caseStmt: 	yCASE  '(' expr ')' 			{ $$ = V3Parse::s_caseAttrp = new AstCase($1,false,$3,NULL); }
 	|	yCASEX '(' expr ')' 			{ $$ = V3Parse::s_caseAttrp = new AstCase($1,true,$3,NULL); $1->v3warn(CASEX,"Suggest casez (with ?'s) in place of casex (with X's)\n"); }
 	|	yCASEZ '(' expr ')'	 		{ $$ = V3Parse::s_caseAttrp = new AstCase($1,true,$3,NULL); }
@@ -711,8 +749,13 @@ taskDecl: 	yTASK yID ';'             stmtBlock yENDTASK	{ $$ = new AstTask ($1,*
 	| 	yTASK yID ';' funcVarList stmtBlock yENDTASK	{ $$ = new AstTask ($1,*$2,$4); $4->addNextNull($5); }
 	;
 
-funcDecl: 	yFUNCTION         funcRange yID ';' funcVarList stmtBlock yENDFUNCTION { $$ = new AstFunc ($1,*$3,$5,$2); $5->addNextNull($6);}
-	|	yFUNCTION ySIGNED funcRange yID ';' funcVarList stmtBlock yENDFUNCTION { $$ = new AstFunc ($1,*$4,$6,$3); $6->addNextNull($7); $$->isSigned(true); }
+funcDecl: 	yFUNCTION         funcRange yID				';' funcBody yENDFUNCTION { $$ = new AstFunc ($1,*$3,$5,$2); }
+	|	yFUNCTION ySIGNED funcRange yID				';' funcBody yENDFUNCTION { $$ = new AstFunc ($1,*$4,$6,$3); $$->isSigned(true); }
+	| 	yFUNCTION         funcRange yID yVL_ISOLATE_ASSIGNMENTS ';' funcBody yENDFUNCTION { $$ = new AstFunc ($1,*$3,$6,$2); $$->attrIsolateAssign(true);}
+	|	yFUNCTION ySIGNED funcRange yID yVL_ISOLATE_ASSIGNMENTS ';' funcBody yENDFUNCTION { $$ = new AstFunc ($1,*$4,$7,$3); $$->attrIsolateAssign(true); $$->isSigned(true); }
+	;
+
+funcBody:	funcVarList stmtBlock			{ $$ = $1;$1->addNextNull($2); }
 	;
 
 funcRange:	'[' constExpr ':' constExpr ']'		{ $$ = new AstRange($1,$2,$4); }
@@ -822,6 +865,11 @@ eList:		expr					{ $$ = $1; }
 	|	eList ',' expr				{ $$ = $1;$1->addNext($3); }
 	;
 
+commaEListE:	/* empty */				{ $$ = NULL; }
+	|	',' eList				{ $$ = $2; }
+	;
+
+
 // Gate declarations
 gateDecl: 	yBUF  gateBufList ';'			{ $$ = $2; }
 	|	yNOT  gateNotList ';'			{ $$ = $2; }
@@ -1001,8 +1049,8 @@ pslDir:		yID ':' pslDirOne			{ $$ = $3; }  // ADD: Create label on $1
 	;
 
 //ADD:	|	yRESTRICT pslSequence ';'		{ $$ = PSLUNSUP(new AstPslRestrict($1,$2)); }
-pslDirOne:	yASSERT pslProp ';'			{ $$ = new AstPslAssert($1,$2); }
-	|	yASSERT pslProp yREPORT ySTRING ';'	{ $$ = new AstPslAssert($1,$2,*$4); }
+pslDirOne:	yPSL_ASSERT pslProp ';'			{ $$ = new AstPslAssert($1,$2); }
+	|	yPSL_ASSERT pslProp yREPORT ySTRING ';'	{ $$ = new AstPslAssert($1,$2,*$4); }
 	|	yCOVER  pslProp ';'			{ $$ = new AstPslCover($1,$2); }
 	|	yCOVER  pslProp yREPORT ySTRING ';'	{ $$ = new AstPslCover($1,$2,*$4); }
 	;

test_regress/driver.pl

@@ -190,20 +190,23 @@ sub new {
 	make_main => 1,		# Make __main.cpp
 	# All compilers
 	v_flags => [split(/\s+/,(" -f input.vc --debug-check"
-				 .($opt_verbose ? " +define+TEST_VERBOSE+1":"")
+				 .($opt_verbose ? " +define+TEST_VERBOSE=1":"")
 				 ))],
 	v_flags2 => [],  # Overridden in some sim files
 	v_other_filenames => [],	# After the filename so we can spec multiple files
 	# VCS
 	vcs => 0,
 	vcs_flags => [split(/\s+/,"+cli -I +define+vcs+1 -q +v2k")],
+	vcs_flags2 => [],  # Overridden in some sim files
 	# NC
 	nc => 0,
-	nc_flags => [split(/\s+/,"+licqueue +nowarn+LIBNOU +define+nc=1 -q +assert +sv31a")],
+	nc_flags => [split(/\s+/,"+licqueue +nowarn+LIBNOU +define+nc=1 -q +assert +sv")],
+	nc_flags2 => [],  # Overridden in some sim files
 	# Verilator
 	'v3' => 0,
 	verilator_flags => [split(/\s+/,"-cc")],
 	verilator_make_gcc => 1,
+	verilated_debug => $Opt_Verilated_Debug,
 	stdout_filename => undef,	# Redirect stdout
 	@_};
     bless $self, $class;
@@ -291,6 +294,7 @@ sub compile {
 		    fails=>$param{fails},
 		    cmd=>["vcs",
 			  @{$param{vcs_flags}},
+			  @{$param{vcs_flags2}},
 			  @{$param{v_flags}},
 			  @{$param{v_flags2}},
 			  $param{top_filename},
@@ -304,6 +308,7 @@ sub compile {
 		    fails=>$param{fails},
 		    cmd=>["ncverilog",
 			  @{$param{nc_flags}},
+			  @{$param{nc_flags2}},
 			  @{$param{v_flags}},
 			  @{$param{v_flags2}},
 			  $param{top_filename},
@@ -541,7 +546,7 @@ sub _make_main {
 	print $fh "int main(int argc, char **argv, char **env) {\n";
 	print $fh "    double sim_time = 1000;\n";
     }
-    print $fh "    Verilated::debug(".($Opt_Verilated_Debug?1:0).");\n";
+    print $fh "    Verilated::debug(".($self->{verilated_debug}?1:0).");\n";
     print $fh "    topp = new $VM_PREFIX (\"TOP\");\n";
     my $set;
     if ($self->sp) {

test_regress/t/t_EXAMPLE.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // Use this file as a template for submitting bugs, etc.
@@ -7,57 +7,96 @@
 //	$finish
 // on success, or $stop.
 //
+// The code as shown applies a random vector to the Test
+// module, then calculates a CRC on the Test module's outputs.
+//
 // **If you do not wish for your code to be released to the public
-// please note it here**
+// please note it here, otherwise:**
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
 
 module t (/*AUTOARG*/
    // Inputs
    clk
    );
-
    input clk;
 
-   // Some inputs we'll set to random values
-   reg [31:0] in_a;
-   reg [31:0] in_b;
+   integer 	cyc=0;
+   reg [63:0] 	crc;
+   reg [63:0] 	sum;
 
-   // Some arbitrary function for testing
-   // We'll test below that for each random in_a and in_b, we get a good out_a.
-   wire [31:0] out_x = (in_a ^ in_b);
+   // Take CRC data and apply to testblock inputs
+   wire [31:0]  in = crc[31:0];
 
-   integer cyc; initial cyc=1;
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [31:0] 		out;			// From test of Test.v
+   // End of automatics
+
+   Test test (/*AUTOINST*/
+	      // Outputs
+	      .out			(out[31:0]),
+	      // Inputs
+	      .clk			(clk),
+	      .in			(in[31:0]));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = {32'h0, out};
+
+   // What checksum will we end up with
+`define EXPECTED_SUM 64'h4afe43fb79d7b71e
+
+   // Test loop
    always @ (posedge clk) begin
-      if (cyc!=0) begin
-	 cyc <= cyc + 1;
-	 $write("%d %x %x %x\n", cyc, in_a, in_b, out_x);
-	 if (cyc==1) begin
-	    // Assign inputs randomly
-	    in_a  <= 32'h89a14fab;
-	    in_b <= 32'h7ab512fa;
-	 end
-	 if (cyc==2) begin
-	    in_a  <= 32'hf4c11a42;
-	    in_b <= 32'h359967c6;
-	    // Verify output is correct
-            if (out_x != 32'hf3145d51) $stop;
-	 end
-	 if (cyc==3) begin
-	    in_a  <= 32'h58dca151;
-	    in_b <= 32'hdc687b27;
-            if (out_x != 32'hc1587d84) $stop;
-	 end
-	 if (cyc==4) begin
-	    in_a  <= 32'h09df0bbb;
-	    in_b <= 32'h0d0e7231;
-            if (out_x != 32'h84b4da76) $stop;
-	 end
-	 if (cyc==5) begin
-            if (out_x != 32'h04d1798a) $stop;
-	 end
-	 if (cyc==9) begin
-	    $write("*-* All Finished *-*\n");
-	    $finish;
-	 end
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+	 // Setup
+	 crc <= 64'h5aef0c8d_d70a4497;
+      end
+      else if (cyc<10) begin
+	 sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 if (sum !== `EXPECTED_SUM) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
       end
    end
+
+endmodule
+
+module Test (/*AUTOARG*/
+   // Outputs
+   out,
+   // Inputs
+   clk, in
+   );
+
+   // Replace this module with the device under test.
+   //
+   // Change the code in the t module to apply values to the inputs and
+   // merge the output values into the result vector.
+
+   input clk;
+   input  [31:0] in;   
+   output [31:0] out;
+
+   /*AUTOREG*/
+   // Beginning of automatic regs (for this module's undeclared outputs)
+   reg [31:0] 		out;
+   // End of automatics
+
+   always @(posedge clk) begin
+      out <= in;
+   end
 endmodule

test_regress/t/t_assert_basic.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 v_flags2 => [$Last_Self->{v3}?'--assert':($Last_Self->{nc}?'+assert':'')],
+	 );
+
+execute (
+	 check_finished=>1,
+	 );
+
+ok(1);
+1;

test_regress/t/t_assert_basic.v

@@ -0,0 +1,48 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   reg 	 toggle;
+
+   integer cyc; initial cyc=1;
+   wire [7:0] cyc_copy = cyc[7:0];
+
+   always @ (negedge clk) begin
+      AssertionFalse1: assert (cyc<100);
+      assert (!(cyc==5) || toggle);
+      // FIX cover  {cyc==3 || cyc==4};
+      // FIX cover {cyc==9} report "DefaultClock,expect=1";
+      // FIX cover  {(cyc==5)->toggle} report "ToggleLogIf,expect=1";
+   end
+   
+   always @ (posedge clk) begin
+      if (cyc!=0) begin
+	 cyc <= cyc + 1;
+	 toggle <= !cyc[0];
+	 if (cyc==9) begin
+`ifdef FAILING_ASSERTIONS
+	    assert (0) else $info;
+	    assert (0) else $info("Info message");
+	    assert (0) else $info("Info message, cyc=%d", cyc);
+	    InWarningBlock: assert (0) else $warning("Warning....");
+	    InErrorBlock: assert (0) else $error("Error....");
+	    assert (0) else $fatal(1,"Fatal....");
+`endif
+	 end
+	 if (cyc==10) begin
+	    $write("*-* All Finished *-*\n");
+	    $finish;
+	 end
+      end
+   end
+
+endmodule

test_regress/t/t_assert_basic_cover.pl

@@ -0,0 +1,27 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+top_filename("t/t_assert_basic.v");
+
+compile (
+	 v_flags2 => [$Last_Self->{v3}?'--assert --sp --coverage-user':''],
+	 );
+
+execute (
+	 check_finished=>1,
+	 );
+
+#Needs work
+print "-Info:  NOT checking for coverage\n";
+#file_grep ($Last_Self->{coverage_filename}, qr/t=>'psl_cover',o=>'cover',c=>2\);/);
+#file_grep ($Last_Self->{coverage_filename}, qr/DefaultClock.*,c=>1\);/);
+#file_grep ($Last_Self->{coverage_filename}, qr/ToggleLogIf.*,c=>9\);/);
+
+ok(1);
+1;

test_regress/t/t_assert_basic_fail.pl

@@ -0,0 +1,23 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+top_filename("t/t_assert_basic.v");
+
+compile (
+	 v_flags2 => ['+define+FAILING_ASSERTIONS',
+	              $Last_Self->{v3}?'--assert':($Last_Self->{nc}?'+assert':'')],
+	 fails => $Last_Self->{nc},
+	 );
+
+execute (
+	 fails => 1,
+	 );
+
+ok(1);
+1;

test_regress/t/t_assert_basic_off.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+top_filename("t/t_assert_basic.v");
+
+compile (
+	 v_flags2 => [],
+	 );
+
+execute (
+	 check_finished=>1,
+	 );
+
+ok(1);
+1;

test_regress/t/t_bitsel_loop.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -31,7 +31,9 @@ module t (/*AUTOARG*/
    always @ (posedge clk) begin
       if (cyc!=0) begin
 	 cyc <= cyc + 1;
+`ifdef TEST_VERBOSE
 	 $write("%x/%x %x\n", q, qq, a);
+`endif
 	 if (cyc==1) begin
 	    a = 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26;
 	 end

test_regress/t/t_blocking.v

@@ -65,7 +65,6 @@ module t (/*AUTOARG*/
 	 end
 	 else if (_mode==4) begin
 	    if (mode_d3r != 8'd1) $stop;
-	    $write("[%0t] t_blocking: Passed\n", $time);
 	    $write("*-* All Finished *-*\n");
 	    $finish;
 	 end

test_regress/t/t_case_nest.v

@@ -19,7 +19,9 @@ module t (/*AUTOARG*/
    sub sub (.in(crc[23:0]), .out1(out1));
 
    always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
       $write("[%0t] cyc==%0d crc=%x sum=%x out=%x\n",$time, cyc, crc, sum, out1);
+`endif
       cyc <= cyc + 1;
       crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
       sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {63'h0,out1};
@@ -29,7 +31,7 @@ module t (/*AUTOARG*/
 	 sum <= 64'h0;
       end
       else if (cyc==90) begin
-	 if (sum != 64'h2e5cb972eb02b8a0) $stop;
+	 if (sum !== 64'h2e5cb972eb02b8a0) $stop;
       end
       else if (cyc==91) begin
       end

test_regress/t/t_case_wild.v

@@ -30,7 +30,7 @@ module t (/*AUTOARG*/
 	 sum <= 64'h0;
       end
       else if (cyc==90) begin
-	 if (sum != 64'hf0afc2bfa78277c5) $stop;
+	 if (sum !== 64'hf0afc2bfa78277c5) $stop;
       end
       else if (cyc==91) begin
       end

test_regress/t/t_display.pl

@@ -15,7 +15,9 @@ execute (
 	 expect=>quotemeta(
 '[0] In TOP.v: Hi
 [0] In TOP.v.sub
+[0] In TOP.v.sub.subblock
 [0] In TOP.v.sub2
+[0] In TOP.v.sub2.subblock2
 [0] %X=0c %D=12 %0X=c %0O=14 %B=001100
 [0] %x=0c %d=12 %0x=c %0o=14 %b=001100
 [0] %x=00abbbbcccc %0x=abbbbcccc %o=00527356746314 %b=00000101010111011101110111100110011001100

test_regress/t/t_display.v

@@ -44,13 +44,23 @@ endmodule
 
 module sub;
    task write_m;
-      $write("[%0t] In %m\n", $time);
+      begin
+	 $write("[%0t] In %m\n", $time);
+	 begin : subblock
+	    $write("[%0t] In %m\n", $time);
+	 end
+      end
    endtask
 endmodule
 
 module sub2;
    // verilator no_inline_module
    task write_m;
-      $write("[%0t] In %m\n", $time);
+      begin
+	 $write("[%0t] In %m\n", $time);
+	 begin : subblock2
+	    $write("[%0t] In %m\n", $time);
+	 end
+      end
    endtask
 endmodule

test_regress/t/t_func_endian.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_func_endian.v

@@ -0,0 +1,110 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer 	cyc=0;
+   reg [63:0] 	crc;
+   reg [63:0] 	sum;
+
+   // Take CRC data and apply to testblock inputs
+   wire [31:0]  in = crc[31:0];
+   wire  	noswap = crc[32];
+   wire 	nibble = crc[33];
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [31:0] 		out;			// From test of Test.v
+   wire [31:0] 		swapped;		// From test of Test.v
+   // End of automatics
+
+   Test test (/*AUTOINST*/
+	      // Outputs
+	      .out			(out[31:0]),
+	      .swapped			(swapped[31:0]),
+	      // Inputs
+	      .clk			(clk),
+	      .noswap			(noswap),
+	      .nibble			(nibble),
+	      .in			(in[31:0]));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = {32'h0, out};
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+	 // Setup
+	 crc <= 64'h5aef0c8d_d70a4497;
+      end
+      else if (cyc<10) begin
+	 sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("*-* All Finished *-*\n");
+	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 if (sum !== 64'h89522c3f5e5ca324) $stop;
+	 $finish;
+      end
+   end
+
+endmodule
+
+module Test (/*AUTOARG*/
+   // Outputs
+   out, swapped,
+   // Inputs
+   clk, noswap, nibble, in
+   );
+   input clk;
+
+   input noswap;
+   input nibble;
+
+   input  [31:0] in;   
+   output [31:0] out;
+   output [31:0] swapped;
+
+   function [7:0] EndianSwap;
+      input Nibble;
+      input [7:0] Data;
+      begin
+         EndianSwap = (Nibble ? { Data[0], Data[1], Data[2], Data[3],
+				  Data[4], Data[5], Data[6], Data[7] }
+                       : { 4'h0, Data[0], Data[1], Data[2], Data[3] });
+      end	
+   endfunction
+   
+   assign out[31:24] = (noswap ? in[31:24]
+			: EndianSwap(nibble, in[31:24]));
+   assign out[23:16] = (noswap ? in[23:16]
+			: EndianSwap(nibble, in[23:16]));
+   assign out[15:8]  = (noswap ? in[15:8]
+			: EndianSwap(nibble, in[15:8]));
+   assign out[7:0]   = (noswap ? in[7:0]
+			: EndianSwap(nibble, in[7:0]));
+   
+   reg [31:0] swapped;
+   always @(posedge clk) begin
+      swapped[31:24] <= EndianSwap(nibble, in[31:24]);
+      swapped[23:16] <= EndianSwap(nibble, in[23:16]);
+      swapped[15:8]  <= EndianSwap(nibble, in[15:8] );
+      swapped[7:0]   <= EndianSwap(nibble, in[7:0]  );
+   end
+endmodule

test_regress/t/t_func_graphcirc.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_func_graphcirc.v

@@ -0,0 +1,49 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2006 by Wilson Snyder.
+
+module t (clk);
+   input clk;
+
+   integer cyc; initial cyc=0;
+
+   always @(posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc == 1) begin
+	 ReadContDisps;
+      end
+      else if (cyc == 5) begin
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+`ifndef verilator
+      DispContDisps;
+`endif
+   end
+
+   task ReadContDisps;
+      begin
+	 $display("%m: Here: %d", cyc);
+      end
+   endtask
+
+   integer dindex;
+
+   task DispContDisps;
+      /* verilator public */
+      begin
+	 if (cyc >= 2) begin
+            if ( cyc >= 4 ) begin
+	       dindex = dindex + 2; //*** Error line
+	       $display("%m: DIndex increment %d", cyc);
+	       $c("cout<<\"Hello1?\"<<endl;");
+            end
+	    $c("cout<<\"Hello2?\"<<endl;");
+	    $c("cout<<\"Hello3?\"<<endl;");
+	 end
+      end
+   endtask
+
+endmodule

test_regress/t/t_gate_elim.v

@@ -31,7 +31,9 @@ module t (/*AUTOARG*/
    te te (.clk(clk), .b(b), .vconst(vconst), .q(qe));
 
    always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
       $display("%b",{qa,qb,qc,qd,qe});
+`endif
       if (cyc!=0) begin
 	 cyc <= cyc + 1;
 	 if (cyc==1) begin

test_regress/t/t_gen_assign.v

@@ -25,7 +25,9 @@ module t (/*AUTOARG*/
 		    .Input		(Input[8:0]));
 
    always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
       $write("[%0t] cyc==%0d crc=%x q=%x\n",$time, cyc, crc, sum);
+`endif
       cyc <= cyc + 1;
       crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
       if (cyc==0) begin
@@ -37,7 +39,7 @@ module t (/*AUTOARG*/
 	 sum <= {sum[30:0],sum[31]} ^ {23'h0, crc[8:0]};
       end
       else if (cyc==99) begin
-	 if (sum != 32'he8bbd130) $stop;
+	 if (sum !== 32'he8bbd130) $stop;
 	 $write("*-* All Finished *-*\n");
 	 $finish;
       end

test_regress/t/t_gen_forif.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 nc_flags2 => ['+access+r'],
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_gen_forif.v

@@ -0,0 +1,111 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer 	cyc=0;
+   reg [63:0] crc;
+   reg [63:0] sum;
+
+   wire [3:0] Value = crc[3:0];
+
+   wire [3:0] Result;
+   wire [3:0] Result2;
+
+   Testit testit (/*AUTOINST*/
+		  // Outputs
+		  .Result		(Result[3:0]),
+		  .Result2		(Result2[3:0]),
+		  // Inputs
+		  .clk			(clk),
+		  .Value		(Value[3:0]));
+
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x %x %x %x\n",$time, cyc, crc, Result, Result2);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= {56'h0, Result, Result2}
+	     ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+	 // Setup
+	 crc <= 64'h5aef0c8d_d70a4497;
+      end
+      else if (cyc<10) begin
+	 sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("*-* All Finished *-*\n");
+	 $write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum);
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 if (sum !== 64'h4af37965592f64f9) $stop;
+	 $finish;
+      end
+   end
+
+endmodule
+
+module Test (clk, Value, Result);
+   input clk;
+   input Value;
+   output Result;
+
+   reg Internal;
+
+   assign Result = Internal ^ clk;
+  
+   always @(posedge clk)
+     Internal <= #1 Value;
+endmodule
+
+module Test_wrap1 (clk, Value, Result);
+   input clk;
+   input Value;
+   output Result;
+
+   Test t (clk, Value, Result);
+endmodule
+	
+module Test_wrap2 (clk, Value, Result);
+   input clk;
+   input Value;
+   output Result;
+
+   Test t (clk, Value, Result);
+endmodule
+
+module Testit (clk, Value, Result, Result2);
+   input clk;
+   input [3:0] Value;
+   output [3:0] Result;
+   output [3:0] Result2;
+
+   genvar i;
+   generate
+      for (i = 0; i < 4; i = i + 1)
+	begin : a
+	   if ((i == 0) || (i == 2)) begin : gblk
+	     Test_wrap1 test (clk, Value[i] , Result[i]);
+	   end
+	   else begin : gblk
+	     Test_wrap2 test (clk, Value[i], Result[i]);
+	   end
+	end
+   endgenerate
+
+   assign Result2[0] = a[0].gblk.test.t.Internal;
+   assign Result2[1] = a[1].gblk.test.t.Internal;
+   assign Result2[2] = a[2].gblk.test.t.Internal;
+   assign Result2[3] = a[3].gblk.test.t.Internal;
+
+endmodule

test_regress/t/t_math_cmp.v

@@ -119,9 +119,11 @@ module prover (
    always @ (posedge clk) begin
       cyc <= cyc + 1;
       if (cyc>2) begin
-	 if (0) $write("results[%d][%d] = 8'b%b_%b_%b_%b_%b_%b_%b_%b;\n",
-      		       index_a, index_b,
-      		       gt, gts, gte, gtes, lt, lts, lte, ltes);
+`ifdef TEST_VERBOSE
+	 $write("results[%d][%d] = 8'b%b_%b_%b_%b_%b_%b_%b_%b;\n",
+      		index_a, index_b,
+      		gt, gts, gte, gtes, lt, lts, lte, ltes);
+`endif
 	 exp = results[index_a][index_b];
 	 got   = {gt, gts, gte, gtes, lt, lts, lte, ltes};
 	 if (exp !== got) begin

test_regress/t/t_math_concat.v

@@ -53,7 +53,9 @@ module t (/*AUTOARG*/
    always @ (posedge clk) begin
       if (cyc!=0) begin
 	 cyc <= cyc + 1;
+`ifdef TEST_VERBOSE
 	 $write("%x %x\n", q, i);
+`endif
 	 if (cyc==1) begin
 	    i <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26;
 	 end

test_regress/t/t_math_concat64.v

@@ -95,7 +95,9 @@ module t (/*AUTOARG*/
    always @ (posedge clk) begin
       if (cyc!=0) begin
 	 cyc <= cyc + 1;
+`ifdef TEST_VERBOSE
 	 $write("%x %x\n", q1, i);
+`endif
 	 if (cyc==1) begin
 	    i <= 128'hed388e646c843d35de489bab2413d770;
 	 end

test_regress/t/t_math_imm.v

@@ -47,9 +47,11 @@ module t (/*AUTOARG*/
    always @ (posedge clk) begin
       cyc <= cyc + 1;
       crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
-      if (0) $write("[%0t] cyc==%0d crc=%b %d.%d,%d.%d -> %x.%x -> %x\n",$time, cyc, crc,
-		    LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot,
-		    LowLogicImm, HighLogicImm, LogicImm);
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%b %d.%d,%d.%d -> %x.%x -> %x\n",$time, cyc, crc,
+	     LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot,
+	     LowLogicImm, HighLogicImm, LogicImm);
+`endif
       if (cyc==0) begin
 	 // Single case
 	 crc <= 8'h0;
@@ -65,8 +67,8 @@ module t (/*AUTOARG*/
       end
       else if (cyc==99) begin
 	 $write("[%0t] cyc==%0d crc=%b %x\n",$time, cyc, crc, sum);
-	 if (crc != 8'b00111000) $stop;
-	 if (sum != 64'h58743ffa61e41075) $stop;
+	 if (crc !== 8'b00111000) $stop;
+	 if (sum !== 64'h58743ffa61e41075) $stop;
 	 $write("*-* All Finished *-*\n");
 	 $finish;
       end

test_regress/t/t_math_mul.v

@@ -29,7 +29,7 @@ module t (/*AUTOARG*/
 	 sum <= 64'h0;
       end
       else if (cyc==90) begin
-	 if (sum != 64'hc1f743ad62c2c04d) $stop;
+	 if (sum !== 64'hc1f743ad62c2c04d) $stop;
       end
       else if (cyc==91) begin
       end

test_regress/t/t_math_pow.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -25,7 +25,9 @@ module t (/*AUTOARG*/
    always @ (posedge clk) begin
       if (cyc!=0) begin
 	 cyc <= cyc + 1;
+`ifdef TEST_VERBOSE
 	 $write("%0x %x %x\n", cyc, p, shifted);
+`endif
 	 // Constant versions
 	 if (61'h1 ** 21'h31 != 61'h1) $stop;
 	 if (61'h2 ** 21'h10 != 61'h10000) $stop;

test_regress/t/t_math_repl.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -53,7 +53,9 @@ module t (/*AUTOARG*/
    always @ (posedge clk) begin
       if (cyc!=0) begin
 	 cyc <= cyc + 1;
+`ifdef TEST_VERBOSE
 	 $write("%x %x %x %x %x\n", rf, rf2, dualasr, sl_mask, sr_mask);
+`endif
 	 if (cyc==1) begin
 	    biu <= 64'h12451282_abadee00;
 	    okidoki <= 1'b0;

test_regress/t/t_math_shift.v

@@ -28,7 +28,9 @@ module t (/*AUTOARG*/
    always @ (posedge clk) begin
       if (cyc!=0) begin
 	 cyc <= cyc + 1;
+`ifdef TEST_VERBOSE
 	 $write("%d %x %x %x %x\n", cyc, left, right, qleft, qright);
+`endif
 	 if (cyc==1) begin
 	    amt <= 32'd0;
 	    if (5'b10110>>2  != 5'b00101) $stop;

test_regress/t/t_math_vliw.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -47,8 +47,8 @@ module t (/*AUTOARG*/
       end
       else if (cyc==99) begin
 	 $write("[%0t] cyc==%0d crc=%b %x\n",$time, cyc, crc, sum);
-	 if (crc != 8'b01110000) $stop;
-	 if (sum != 224'h1fdff998855c3c38d467e28124847831f9ad6d4a09f2801098f032a8) $stop;
+	 if (crc !== 8'b01110000) $stop;
+	 if (sum !== 224'h1fdff998855c3c38d467e28124847831f9ad6d4a09f2801098f032a8) $stop;
 	 $write("*-* All Finished *-*\n");
 	 $finish;
       end

test_regress/t/t_mem_file.v

@@ -66,8 +66,8 @@ module t (/*AUTOARG*/
       else if (cyc==99) begin
 	 $write("*-* All Finished *-*\n");
 	 $write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum);
-	 if (crc != 64'hc77bb9b3784ea091) $stop;
-	 if (sum != 64'h5e9ea8c33a97f81e) $stop;
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 if (sum !== 64'h5e9ea8c33a97f81e) $stop;
 	 $finish;
       end
    end

test_regress/t/t_mem_iforder.v

@@ -48,7 +48,7 @@ module t (/*AUTOARG*/
 	 sum <= {sum[30:0],sum[31]} ^ {out1, out0};
       end
       else if (cyc==99) begin
-	 if (sum != 32'he8bbd130) $stop;
+	 if (sum !== 32'he8bbd130) $stop;
 	 $write("*-* All Finished *-*\n");
 	 $finish;
       end

test_regress/t/t_mem_slot.cpp

@@ -6,7 +6,9 @@ unsigned int Array[3];
 
 unsigned int
 StepSim (Vt_mem_slot *sim, unsigned int slot, unsigned int bit, unsigned int val, unsigned int rslot) {
+#ifdef TEST_VERBOSE
     printf ("StepSim: slot=%d bit=%d val=%d rslot=%d\n", slot, bit, val, rslot);
+#endif
 
     sim->SlotIdx      = slot;
     sim->BitToChange  = bit;

test_regress/t/t_mod_bad_twotop.pl

@@ -1,6 +1,6 @@
 #!/usr/bin/perl
 if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
-# $Id:$
+# $Id$
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can
@@ -11,7 +11,7 @@ compile (
 	 fails=>$Last_Self->{v3},
 	 nc=>0,  # Need to get it not to give the prompt
 	 expect=>
-'%Error: t/t_mod_bad_twotop.v:\d+: Unsupported: Multiple top level modules: t2 and t
+'%Error-MULTITOP: t/t_mod_bad_twotop.v:\d+: Unsupported: Multiple top level modules: t2 and t
 %Error: Exiting due to.*',
 	 );
 

test_regress/t/t_order_doubleloop.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,

test_regress/t/t_preproc_kwd.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_preproc_kwd.v

@@ -0,0 +1,31 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+`begin_keywords "1364-1995"
+  integer signed; initial signed = 1;
+`end_keywords
+`begin_keywords "1364-2001"
+  integer bit; initial bit = 1;
+`end_keywords
+`begin_keywords "1364-2005"
+  integer final; initial final = 1;
+ `begin_keywords "1800-2005"
+  final begin
+     $write("*-* All Finished *-*\n");
+  end
+ `end_keywords
+`end_keywords
+
+   initial begin
+      $finish;
+   end
+endmodule

test_regress/t/t_select_set.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -12,7 +12,9 @@ module t (clk);
 
    integer cyc; initial cyc=1;
    always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
       $write ("%x %x\n", cyc, addr);
+`endif
       if (cyc!=0) begin
 	 cyc <= cyc + 1;
 	 if (cyc==1) begin

test_regress/t/t_unopt_combo.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 v_flags2 => ['+define+ALLOW_UNOPT'],
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_unopt_combo.v

@@ -0,0 +1,135 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2005 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+   integer cyc; initial cyc=0;
+   reg [63:0] crc;
+   reg [63:0] sum;
+
+`ifdef ALLOW_UNOPT
+   /*verilator lint_off UNOPTFLAT*/
+`endif
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [31:0]		b;			// From file of file.v
+   wire [31:0]		c;			// From file of file.v
+   wire [31:0]		d;			// From file of file.v
+   // End of automatics
+
+   file file (/*AUTOINST*/
+	      // Outputs
+	      .b			(b[31:0]),
+	      .c			(c[31:0]),
+	      .d			(d[31:0]),
+	      // Inputs
+	      .crc			(crc[31:0]));
+
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc=%0d crc=%x sum=%x b=%x d=%x\n",$time,cyc,crc,sum, b, d);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= {b, d}
+	     ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+	 // Setup
+	 crc <= 64'h5aef0c8d_d70a4497;
+      end
+      else if (cyc<10) begin
+	 sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("*-* All Finished *-*\n");
+	 $write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum);
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 if (sum !== 64'h649ee1713d624dd9) $stop;
+	 $finish;
+      end
+   end
+
+endmodule
+
+module file (/*AUTOARG*/
+   // Outputs
+   b, c, d,
+   // Inputs
+   crc
+   );
+   
+   input [31:0]        crc;
+`ifdef ISOLATE
+   output reg [31:0]   b /* verilator isolate_assignments*/;
+`else
+   output reg [31:0]   b;
+`endif
+
+   output reg [31:0]   c;
+   output reg [31:0]   d;
+
+   always @* begin
+      // Note that while c and b depend on crc, b doesn't depend on c.
+      casez (crc[3:0])
+	4'b??01: begin
+	   b = {crc[15:0],get_31_16(crc)};
+	   d = c;
+	end
+	4'b??00: begin
+	   b = {crc[15:0],~crc[31:16]};
+	   d = {crc[15:0],~c[31:16]};
+	end
+	default: begin
+	   set_b_d(crc, c);
+	end
+      endcase
+   end
+
+   function [31:16] get_31_16	/* verilator isolate_assignments*/;
+      input [31:0] t_crc	/* verilator isolate_assignments*/;
+      get_31_16 = t_crc[31:16];
+   endfunction
+
+   task set_b_d;
+`ifdef ISOLATE
+      input [31:0] t_crc	/* verilator isolate_assignments*/;
+      input [31:0] t_c		/* verilator isolate_assignments*/;
+`else
+      input [31:0] t_crc;
+      input [31:0] t_c;
+`endif
+      begin
+	 b = {t_crc[31:16],~t_crc[23:8]};
+	 d = {t_crc[31:16],  ~t_c[23:8]};
+      end
+   endtask
+
+   always @* begin
+      // Any complicated equation we can't optimize
+      casez (crc[3:0])
+	4'b00??: begin
+	   c = {b[29:0],2'b11};
+	end
+	4'b01??: begin
+	   c = {b[30:1],2'b01};
+	end
+	4'b10??: begin
+	   c = {b[31:2],2'b10};
+	end
+	4'b11??: begin
+	   c = {b[31:2],2'b00};
+	end
+      endcase
+   end
+
+endmodule

test_regress/t/t_unopt_combo_bad.pl

@@ -0,0 +1,29 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+top_filename("t/t_unopt_combo.v");
+
+compile (
+	 fails=>$Last_Self->{v3},
+	 expect=>
+'%Warning-UNOPTFLAT: t/t_unopt_combo.v:\d+: Signal unoptimizable: Feedback to clock or circular logic: TOP->v.c
+%Warning-UNOPTFLAT: Use "/\* verilator lint_off UNOPTFLAT \*/" and lint_on around source to disable this message.
+%Warning-UNOPTFLAT:      Example path: t/t_unopt_combo.v:\d+:  TOP->v.c
+%Warning-UNOPTFLAT:      Example path: t/t_unopt_combo.v:\d+:  ALWAYS
+%Warning-UNOPTFLAT:      Example path: t/t_unopt_combo.v:\d+:  TOP->v.b
+%Warning-UNOPTFLAT:      Example path: t/t_unopt_combo.v:\d+:  ALWAYS
+%Warning-UNOPTFLAT:      Example path: t/t_unopt_combo.v:\d+:  TOP->v.c
+%Error: Exiting due to '
+	 );
+
+execute (
+     ) if !$Last_Self->{v3};
+
+ok(1);
+1;

test_regress/t/t_unopt_combo_isolate.pl

@@ -0,0 +1,24 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+top_filename("t/t_unopt_combo.v");
+
+compile (
+	 v_flags2 => ['+define+ISOLATE --stats'],
+	 );
+
+if ($Last_Self->{v3}) {
+    file_grep ($Last_Self->{stats}, qr/Optimizations, isolate_assignments blocks\s+5/i);
+}
+
+execute (
+	 );
+
+ok(1);
+1;

test_regress/t/t_unopt_converge.v

@@ -0,0 +1,26 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Outputs
+   x,
+   // Inputs
+   clk
+   );
+
+`ifdef ALLOW_UNOPT
+   /*verilator lint_off UNOPTFLAT*/
+`endif
+
+   input clk;
+   output x;   // Avoid eliminating x
+
+   reg x;
+   always @* begin
+      x = ~x;
+   end
+
+endmodule

test_regress/t/t_unopt_converge_print_bad.pl

@@ -0,0 +1,24 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2007 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+top_filename("t/t_unopt_converge.v");
+#$Last_Self->{verilated_debug} = 1;
+
+compile (
+	 v_flags2 => ['+define+ALLOW_UNOPT'],
+	 make_flags => 'CPPFLAGS_ADD=-DVL_DEBUG',
+	 );
+
+execute (
+	 fails=>1,
+	 expect=> '%Error: \S+:\d+: Verilated model didn\'t converge',
+     ) if $Last_Self->{v3};
+
+ok(1);
+1;

test_regress/t/t_unopt_converge_run_bad.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2007 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+top_filename("t/t_unopt_converge.v");
+
+compile (
+	 v_flags2 => ['+define+ALLOW_UNOPT'],
+	 );
+
+execute (
+	 fails=>1,
+	 expect=> '%Error: \S+:\d+: Verilated model didn\'t converge',
+     ) if $Last_Self->{v3};
+
+ok(1);
+1;

test_regress/t/t_unopt_converge_unopt_bad.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2007 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+top_filename("t/t_unopt_converge.v");
+
+compile (
+	 fails=>1,
+	 expect=> '%Warning-UNOPT: t/t_unopt_converge.v:\d+: Signal unoptimizable: Feedback to public clock or circular logic: TOP->x
+.*
+%Error: Exiting due to '
+     ) if $Last_Self->{v3};
+
+ok(1);
+1;

test_regress/t/t_unroll_signed.v

@@ -11,6 +11,17 @@ module t (/*AUTOARG*/
 
    input clk;
 
+   // Check empty blocks
+   task EmptyFor;
+      /* verilator public */
+      integer i;
+      begin
+         for (i = 0; i < 2; i = i+1)
+           begin
+           end
+      end
+   endtask
+
    // Check look unroller
    reg signed	   signed_tests_only = 1'sb1;
    integer 	   total;