luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
9,226 Commits 2 Branches 168 Tags 264 MiB
Commit Graph

9226 Commits

Author SHA1 Message Date
Nick Brereton be7827488f Fix t_tri_hier_ref_unsup test output. 2026-03-03 08:17:00 -05:00
Nick Brereton 97fd113536 Fix incorrect golden reference 2026-03-02 23:56:17 -05:00
Nick Brereton 3675c9e50e combine tests, fix formatting 2026-03-02 21:31:11 -05:00
Nick Brereton 43f62cd07a Merge remote-tracking branch 'origin/master' into fix-sv-interface-inout 2026-03-02 21:03:43 -05:00
Nick Brereton 61f21f22fc fix struct final, fix formatting 2026-03-02 21:03:25 -05:00
github action 1b414fcc26 Apply 'make format' 2026-03-03 00:08:46 +00:00
Nick Brereton 44ccdbf669 V3Dfg: suppress MULTIDRIVEN for intentional interface tristate lowering while retaining coverage multidrive warnings 2026-03-02 19:07:30 -05:00
github action fb8452c563 Apply 'make format' 2026-02-28 15:45:52 +00:00
Nick Brereton d2f8ac85ad V3Tristate: handle interface tristate signals accessed via VarXRef (#3466) 
Extend the tristate pass to treat side-band enable and output signals as first-class cross-module variables. Previously, these were assumed local to the driving module and only accessed via VarRef. Now they are created in the interface module alongside the original signal and accessed via VarXRef using the same hierarchical path, allowing the rest of Verilator's infrastructure to resolve them normally.

This enables support for interface tristate signals accessed through hierarchical references and modports, including === / !== comparisons, mixed local and external drivers, and deep hierarchy. Modports that expose a tristate signal are automatically extended to include the generated enable signal so that modport-qualified paths resolve correctly.
 2026-02-28 10:42:47 -05:00
Geza Lore 2ceea267e5
Fix eliminating assignments to DPI-read vaiables (#7158) 2026-02-28 10:09:01 -05:00
Pawel Kojma face700f29
Improve assignment-compatibility type check (#2843) (#5666) (#7052) 2026-02-28 09:55:06 -05:00
Geza Lore 139bdc1ae3
Optimize function call return value temporaries (#7152) 2026-02-28 09:54:39 -05:00
Szymon Gizler 1af7fa92c2
Optimize size of trace declaration object code (#7150) 2026-02-28 09:54:08 -05:00
Ryszard Rozak 6f892d58ac
Fix forcing unpacked variables (#7149) 2026-02-28 09:53:41 -05:00
Kamil Danecki df6b808c49
Fix parameters inside std::randomize `with` clause (#7140) 2026-02-28 09:53:05 -05:00
Todd Strader 8705bc56c8
Fix errant integer promotion (#7012) 2026-02-28 09:52:35 -05:00
Nick Brereton 02c1dbc5dc
Fix lambda coroutines (#6106) (#7135) 2026-02-28 09:52:02 -05:00
Geza Lore 1716423d07
Internals: Fix invalid use of user1 in V3Const (#7157) 2026-02-28 09:51:07 -05:00
Wilson Snyder 1e6c1ab106 Add VPI callback support to --main (#7145). 
Fixes #7145.
 2026-02-28 09:42:28 -05:00
Wilson Snyder d40036239b Fix wide conditional short circuiting (#7155). 
Fixes #7155.
 2026-02-28 09:40:10 -05:00
Wilson Snyder 5ae285d268 devel release 2026-02-28 09:37:43 -05:00
Wilson Snyder 24b2ac24c7 Version bump 2026-02-28 09:21:59 -05:00
Wilson Snyder af65a85a1e Fix function locals in display %p 2026-02-26 18:12:12 -05:00
Wilson Snyder 2efcfa567c Commentary: Changes update 2026-02-25 20:28:14 -05:00
Veripool API Bot 3190442f86 Verilog format 2026-02-25 20:28:07 -05:00
Wilson Snyder 6f96ff8df6 Tests: Limit test.build_jobs based on number of tests running 2026-02-25 20:27:07 -05:00
Wilson Snyder 22290a74c2 Fix class initial-automatic insertion order (#7086 repair) 2026-02-25 19:01:19 -05:00
em2machine d658517715
Change type definition error to show type chain with source context (#7151) 2026-02-25 14:47:13 -05:00
AUDIY 8d34bc786a
Commentary: Add coverage type to example (#7148) 2026-02-25 01:26:51 -05:00
Wilson Snyder 7dde11b4c6 Docs: Split control.rst from exe_verilator.rst. 2026-02-24 21:11:39 -05:00
Wilson Snyder ef498255f9 Commentary: Changes update 2026-02-24 21:03:35 -05:00
Veripool API Bot c28200c53a Verilog format 2026-02-24 21:03:32 -05:00
AUDIY 10eafb9b3f Add coverage type information to verilator_coverage annotation output (#7131) (#7133). 
Fixes #7131.
 2026-02-24 20:59:42 -05:00
Wilson Snyder 9bc88ff1bc Fix finding single DPI exports from other scopes 2026-02-24 19:06:05 -05:00
Wilson Snyder e976424efa Internals: Add nodist/verilog_format 2026-02-24 14:45:57 -05:00
Gilberto Abram 826b03c21f
Fix segfault in EmitCSyms::getSymCtorStmts (#7142) (#7143) 2026-02-24 14:08:01 -05:00
Wilson Snyder 7607f0e7fa
Support proper automatic/static initialization, and remove STATICVAR warning (#6405). (#7086) 2026-02-24 14:04:43 -05:00
Wilson Snyder 3992da6027 Tests: Add t_assign_func 2026-02-24 04:17:42 -05:00
Wilson Snyder 1c41f87d67 Verilog format 2026-02-24 04:15:26 -05:00
Wilson Snyder 387cc206b3 Tests: Rename t_always tests 2026-02-24 04:11:39 -05:00
Todd Strader 6a5d3b0b72
Add --max-replication option (#7139) 2026-02-23 16:51:37 -05:00
Geza Lore f7c5454d91
Internals: Strengthen AstNodeExpr operand types (#7138) 2026-02-23 20:55:08 +00:00
Geza Lore 8c7f08dfc3
Fix inlining of CFuncs with reloop locals (#7132) 
The recent V3InlineCFuncs only checks AstCFunc::varsp for locals, but
V3Reloop used to insert them into AstCFunc::stmtsp resulting in multiple
locals with the same name being inlined into the caller if the stars
align. Fix Reloop. Such things will also go away with #6280.
 2026-02-23 17:35:15 +00:00
Nick Brereton 6ba6447483 V3Tristate: handle AstVarXRef as AstVarRef (#3466) 2026-02-23 09:43:04 -05:00
Wilson Snyder 7c923bb330 Internals: Fix hasher message 2026-02-23 03:34:37 -05:00
Wilson Snyder 97fd6a5a13 Support vpiScalarVal 2026-02-22 20:04:06 -05:00
Geza Lore 1e5a6901c8
Internals: Make AstWith explicit in AstCMethodHard (#7129) 
This makes it consistent with other usage in NodeFTaskRef. Also AstWith
is no longer a NodeExpr.
 2026-02-22 15:38:28 -05:00
Wilson Snyder f74a581d97 Tests: Enforce SPDX-FileCopyrightText 2026-02-22 15:23:19 -05:00
Geza Lore da51021b0a
Internals: Simplify AstForeach header handling (#7126) 
Rename AstSelLoopVars to AstForeachHeader, and make it a non-NodeExpr.
Tweak parser to always create an AstForeachHeader, so no need to fix it
up later.
 2026-02-22 18:57:12 +00:00
Wilson Snyder e238a2ca5e Verilog format 2026-02-22 13:50:01 -05:00