Commit Graph

835 Commits

Author SHA1 Message Date
Congcong Cai ca2c40347b
Fix undefined weak link for Apple GCC etc (#6348) 2025-08-30 14:25:20 -04:00
Wilson Snyder ac2859bf24
Internals: Upgrade to clang-format-18 (#6333) 2025-08-25 20:47:48 -04:00
Wilson Snyder 703f0d8c5d Commentary: spelling 2025-08-25 18:47:08 -04:00
Geza Lore 636a6b8cd2
Optimize complex combinational logic in DFG (#6298)
This patch adds DfgLogic, which is a vertex that represents a whole,
arbitrarily complex combinational AstAlways or AstAssignW in the
DfgGraph.

Implementing this requires computing the variables live at entry to the
AstAlways (variables read by the block), so there is a new
ControlFlowGraph data structure and a classical data-flow analysis based
live variable analysis to do that at the variable level (as opposed to
bit/element level).

The actual CFG construction and live variable analysis is best effort,
and might fail for currently unhandled constructs or data types. This
can be extended later.

V3DfgAstToDfg is changed to convert the Ast into an initial DfgGraph
containing only DfgLogic, DfgVertexSplice and DfgVertexVar vertices.

The DfgLogic are then subsequently synthesized into primitive operations
by the new V3DfgSynthesize pass, which is a combination of the old
V3DfgAstToDfg conversion and new code to handle AstAlways blocks with
complex flow control.

V3DfgSynthesize by default will synthesize roughly the same constructs
as V3DfgAstToDfg used to handle before, plus any logic that is part of a
combinational cycle within the DfgGraph. This enables breaking up these
cycles, for which there are extensions to V3DfgBreakCycles in this patch
as well. V3DfgSynthesize will then delete all non synthesized or non
synthesizable DfgLogic vertices and the rest of the Dfg pipeline is
identical, with minor changes to adjust for the changed representation.

Because with this change we can now eliminate many more UNOPTFLAT, DFG
has been disabled in all the tests that specifically target testing the
scheduling and reporting of circular combinational logic.
2025-08-19 15:06:38 +01:00
Geza Lore 0bf9fc270f
Iternals: Remove AstAssignPre/AstAssignPost (#6307)
Replace with AstAlwaysPre/AstAlwaysPost with AstAssign under them.

Step towards #6280
2025-08-19 09:27:59 +01:00
Wilson Snyder c90f9e53b7
Add ALWNEVER warning, for `always @*` that never execute (#6291) (#6303) 2025-08-18 12:00:53 -04:00
Wilson Snyder 48a12fb0f4 Document and test `+verilator+rand+reset+2` usage (#6285 partial) 2025-08-16 11:47:19 -04:00
Wilson Snyder 000d697b51 Commentary: Changes update 2025-08-16 09:08:09 -04:00
Sergey Fedorov ece4469869
Fix PowerPC support (#6292) 2025-08-15 11:25:32 -07:00
Wilson Snyder 75c6745868 Test driver.py: Pass-through +verilator+ arguments to runtime 2025-08-12 19:32:56 -04:00
Wilson Snyder 60cbbf0ec1 Add error on mismatching prototypes (#6207). 2025-08-11 19:50:47 -04:00
Michael Bedford Taylor 218659f4e8
Support parameter resolution of 1D unpacked array slices (#6257) (#6268) 2025-08-06 17:29:40 -04:00
Wilson Snyder 06c570e159 Commentary 2025-08-05 17:56:12 -04:00
Wilson Snyder 4bd17f0a6f Commentary: Changes update 2025-08-05 17:08:09 -04:00
Wilson Snyder 309129ebcf Add PARAMNODEFAULT error, for parameters without defaults. 2025-08-03 15:27:37 -04:00
Rodrigo Batista de Moraes d0f0919830
Fix write of 0 in '%c' (#6248) (#6249) 2025-08-01 07:54:18 +02:00
Wilson Snyder 5faaa7ec58 Commentary (#6246) 2025-07-31 18:09:43 -04:00
Wilson Snyder 833c31b031 Add `-DVERILATOR=1` definition to compiler flags when using verilated.mk. 2025-07-28 18:01:50 -04:00
Wilson Snyder 7c71bdf2d6 Commentary 2025-07-27 15:55:59 -04:00
Wilson Snyder 55b836e25a Commentary: Changes update 2025-07-27 09:44:51 -04:00
George Polack f1826a7c20
Support Verilog real to SystemC double (#6136) (#6158) 2025-07-25 20:05:36 +02:00
Danny Oler 74d4b0c0ea
Fix automatic task variables in unrolled loops with forks (#6194) (#6201). 2025-07-21 19:28:50 -04:00
Max Wipfli a50ea2a1a6
Optimize 2 ** X to 1 << X if base is signed (#6203) 2025-07-20 09:56:34 -04:00
Wilson Snyder 078bb21a89 Add wire data type checking per IEEE. 2025-07-20 07:21:30 -04:00
Wilson Snyder f535a73ea7 Commentary: Changes update 2025-07-19 21:12:23 -04:00
Ibrahim Burak Yorulmaz 9d146eae16
Fix VPI signal range order (#6189) (#6200) 2025-07-19 20:22:02 -04:00
Wilson Snyder 7d43a935bd Add SPECIFYIGN warning for specify constructs that were previously silently ignored. 2025-07-18 19:32:34 -04:00
Wilson Snyder 7a32771c7e Commentary: Changes update 2025-07-16 17:26:01 -04:00
Wilson Snyder 1f0357ba93 Add NOEFFECT warning, replacing previous `foreach` error. 2025-07-16 08:18:57 -04:00
Wilson Snyder 2f199f20cf Add ENUMITEMWIDTH error, and apply to X-extended and ranged values. 2025-07-12 14:14:17 -04:00
Wilson Snyder cefe1845df Commentary: Changes update 2025-07-11 21:53:29 -04:00
Artur Bieniek 4dc6a31276
Fix omitting error when assigning to an input (#6169) 2025-07-10 20:37:55 -04:00
Geza Lore ce77bac99a
Break some combinational cycles in DFG (#6168)
Added an algorithm that can break some combinational cycles in DFG, by
attempting to trace driver logic until we escape the cycle. This can
eliminate a decent portion of UNOPTFLAT warnings. E.g. due to this code:

```systemverilog
assign a[0] = .....;
assign a[1] = ~a[0];
```
2025-07-10 18:46:45 +01:00
Wilson Snyder 1f0e767b61 Commentary: Changes update 2025-07-08 17:37:21 -04:00
Igor Zaworski 5777ab75c7
Fix crash with --dumpi-V3LinkDot without --debug (#6159) 2025-07-08 10:28:17 -04:00
Wilson Snyder f77af4e6f6 Important: Change `--assert` to be the default; use `--no-assert` for legacy behavior and faster runtimes. 2025-07-03 19:36:28 -04:00
Geza Lore 7a3f1f16ca
Optimize DFG before V3Gate (#6141) 2025-07-01 17:55:08 -04:00
Wilson Snyder 73da5e51a6 Commentary: Changes update 2025-07-01 08:07:54 -04:00
Wilson Snyder 916a89761e Add `--work` library-selection option (#5891 partial). 2025-06-29 20:17:27 -04:00
Geza Lore bc892deacc
Safely support non-overlapping blocking/non-blocking assignments (#6137)
The manual for the BLKANDNBLK warning describes that it is safe to
disable that error if the updated ranges are non-overlapping. This
however was not true (see the added t_nba_mixed_update* tests).

In this patch we change V3Delayed to use a new ShadowVarMasked
scheme for variables that have mixed blocking and non-blocking 
updates (or the FlagUnique scheme for unpacked variables), which
is in fact safe to use when the updated parts are non-overlapping.

Furthermore, mixed assignments are safe as far as scheduling is
concerned if either:

- They are to independent parts (bits/members/etc) (with this patch)
- Or if the blocking assignment is in clocked (or suspendable) logic.

The risk in scheduling is a race between the Post scheduled NBA
commit, and blocking assignments in combinational logic, which might
order incorrectly.

The second point highlights that we can handle stuff like this safely,
which is sometimes used in testbenches:

```systemverilog
always @(posedge clk) begin
    if ($time == 0) a = 0;
end

always @(posedge clk) begin
    if ($time > 0) a <= 2;
end
````

The only dangerous case is:

```systemverilog
always @(posedge clk) foo[idx] <= val;
assign foo[0] = bar;
```

Whit this patch, this will still resolve fine at run-time if 'idx' is
never zero, but might resolve incorrectly if 'idx' is zero.

With the above in mind, the BLKANDNBLK warning is now only issued if:

- We can't prove that the assignments are to non-overlapping bits
- And the blocking assignment is in combinational logic

These are the cases that genuinely require user attention to resolve.

With this patch, there are no more BLKANDNBLK warnings in the RTLMeter
designs.

Fixes #6122.
2025-06-28 20:45:45 +01:00
Wilson Snyder 189d094202 Commentary 2025-06-27 22:31:51 -04:00
Wilson Snyder 3defaf8ffb Rename Verilator Config Files to Verilator Control Files.
Avoids conflict with IEEE `config`.  No functional change intended.
2025-06-27 20:38:01 -04:00
Wilson Snyder 68e1ed55f6 Commentary: Changes update 2025-06-26 17:42:10 -04:00
Wilson Snyder 993f65f3b4 Internals/CI: Format cmakefiles using mbake 2025-06-26 17:36:56 -04:00
Wilson Snyder 51545b36ca Internals: Add format-make rule and standardize Makefile indents. No functional change intended. 2025-06-24 17:58:55 -04:00
Wilson Snyder a9e9ab50bd Commentary: Changes update 2025-06-23 18:40:49 -04:00
Geza Lore 2daa09a255
Optimize constify within Expand and Subst (#6111)
These passes blow up the Ast size on some designs, so delaying running V3Const
until after the whole pass can notably increase peak memory usage. In this
patch we apply V3Const per CFunc within these passes, which saves on memory.
Added -fno-const-eager to disable the intra-pass V3Const application, for
debugging.
2025-06-23 17:58:26 -04:00
Peter Birch 75df36bc8f
Add hint of the signed rhsval in oversized replication error (#6098) 2025-06-17 16:59:18 -07:00
Geza Lore de2818c733
Add RTLMeter badge and note in internals docs (#6095) 2025-06-16 16:35:31 +01:00
Wilson Snyder 4c2eb8c0b8 Commentary: Fix broken links 2025-06-15 14:51:56 -04:00
Wilson Snyder 1c357ba508 Commentary 2025-06-10 08:17:45 -04:00
Todd Strader 9fc223d3ee
Commentary: FPGA PROCASSINIT guidance (#6067) 2025-06-06 09:59:05 -04:00
Wilson Snyder 8031ca2616 Add `MODMISSING` error, in place of unnamed error (#6054). 2025-05-29 21:02:00 -04:00
Wilson Snyder 40881d7e79 Commentary: Changes update 2025-05-29 18:59:51 -04:00
Bartłomiej Chmiel 9cc4cc0efd
Add `--hierarchical-threads` (#6037) 2025-05-26 09:37:35 -04:00
Petr Nohavica 22d484d54d
Fix associative arrays with enum keys (#6034) (#6035) 2025-05-24 17:59:23 -04:00
Ryszard Rozak 2491f25da7
Add filtering type option in verilator_coverage (#6030) 2025-05-22 02:42:09 -07:00
Wilson Snyder f8359adcc0 Commentary: Changes update 2025-05-20 22:51:07 -04:00
Joel Bodenmann 80ea173390
Add missing FreeBSD include (#6027) (#6028)
Fixes #6027
2025-05-20 16:46:07 -07:00
Shou-Li Hsu 25cb31c38b
Add aggregate type error checks (#5570) (#5950) 2025-05-20 09:10:22 -04:00
Wilson Snyder 6bb16d6c52 Disable symbol from parser: Support redeclaring type as non-type; major parsing change (#2412). 2025-05-18 07:13:37 -04:00
Wilson Snyder 66667b6172
Support SARIF JSON diagnostic output with `--diagnostics-sarif`. (#6017) 2025-05-17 15:46:15 -04:00
Wilson Snyder 2dbe897e1b Add security policy 2025-05-16 22:08:12 -04:00
Wilson Snyder 1bcd5ee0c1 Fix spelling 2025-05-16 19:02:19 -04:00
Wilson Snyder 9430960b18 Commentary: Changes update 2025-05-16 18:59:35 -04:00
Zhen Yan 6b42d789af
Fix checking for too-wide divide and modulus (#6003) (#6006) 2025-05-15 10:43:45 -04:00
Wilson Snyder 8100bc64a0 Commentary 2025-05-11 22:36:16 -04:00
Dominick Grochowina 295fae0edc
Fix nullptr segfault in VerilatedVcd::emitTimeChange() (#5980) 2025-05-11 08:01:13 -04:00
Wilson Snyder d0424862f9 Commentary: Changes update 2025-05-10 13:22:26 -04:00
Wilson Snyder 69eb76ad66 Fix constant propagation of post-expand stages (#5983). 2025-05-05 07:04:20 -04:00
Wilson Snyder 51616ecf2f Internals: Rename to instances, and other minor cleanups 2025-05-04 14:57:10 -04:00
Wilson Snyder ea65bcd86b Add lib.map information to unsupported message, etc 2025-05-03 05:30:40 -04:00
Wilson Snyder e837f780a2 Commentary 2025-05-03 04:25:01 -04:00
Wilson Snyder 1a1c6e8797 Change cell messages to instance to match IEEE 2025-05-03 04:00:47 -04:00
Wilson Snyder 3b8d10cae5 Commentary 2025-05-02 07:35:38 -04:00
Wilson Snyder 8b52bd817f Add PROCINITASSIGN on initial assignments to process variables (#2481). 2025-04-30 22:00:06 -04:00
Wilson Snyder 38dd9a344e Improve documentation for BADVLTPRAGMA 2025-04-30 20:32:30 -04:00
Wilson Snyder 9b3fccdcb7 Add BADVLTPRAGMA on unknown Verilator pragmas (#5945). 2025-04-29 18:18:54 -04:00
Wilson Snyder c9be36911f Cleanup documentated option sort order, and enforce with test 2025-04-26 17:14:49 -04:00
John Khoo fee839a80e
Update UNOPTFLAT warning to suggest isolate_assignments (#5942) 2025-04-18 18:35:36 +09:00
Wilson Snyder 09d27fa8a7 Commentary: Changes update 2025-04-16 07:34:04 -04:00
Zhouyi Shen 3694d153ae
Fix backward compatibility for `TRACE` option & Fix missing C++ regeneration when Verilog files are updated (#5934) 2025-04-12 17:49:41 -04:00
Robin Heinemann 10c3320c6b
Support soft unions (#5912) (#5932) 2025-04-12 07:35:37 -04:00
Bartłomiej Chmiel 84f26ed3d7
Add visualization of multi-threaded waiting time with verilator_gantt (#5929) 2025-04-10 10:03:58 -04:00
Wilson Snyder fc8e1b5a2e Fix several cmake issues, including TRACE_VCD 2025-04-10 07:49:58 -04:00
Wilson Snyder 0a3de7c74a Commentary: Changes update 2025-04-07 08:32:31 -04:00
Wilson Snyder 0984fd045f Change `--trace` to `--trace-vcd`. 2025-04-05 10:46:39 -04:00
Wilson Snyder d5077a9d35 Commentary (#5919) 2025-04-05 09:45:07 -04:00
Wilson Snyder 14e7b1076e Commentary: Changes update 2025-04-02 23:17:39 -04:00
Wilson Snyder 6d1e82b908
Add numactl-like automatic assignment of processor affinity (#5911) 2025-04-02 08:27:23 -04:00
Krzysztof Sychla cd5997a2e6
Support `$setuphold` (#5884) 2025-04-02 06:08:51 -04:00
Brian Li 559d990e82
Support command-line overriding `define (#5900) (#5908) 2025-04-01 07:33:49 -04:00
Wilson Snyder 6f87443da5 Commentary 2025-03-30 11:02:21 -04:00
Wilson Snyder 0a860f151c Cleanup some missed `make clean` files 2025-03-30 11:02:05 -04:00
Wilson Snyder fd960b5f77 Commentary: Changes update 2025-03-28 23:14:15 -04:00
Wilson Snyder 844448655e Add `systemc_header_post 2025-03-28 22:40:21 -04:00
Wilson Snyder b4ef6ce860 Support `systemc_interface and related inside `class`. 2025-03-28 22:40:21 -04:00
Wilson Snyder d26d62a176 Tests: Add driver.py --driver-clean 2025-03-27 18:33:18 -04:00
Bartłomiej Chmiel cdab9479b8
Commentary: Fix bugpoint link (#5883)
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
2025-03-26 07:05:18 -04:00
Wilson Snyder 4dd49e1244 Commentary: Changes update 2025-03-25 08:24:19 -04:00