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Tests: Rename `inf` to avoid VAMS errors

This commit is contained in:
Wilson Snyder 2026-08-13 18:50:20 -04:00
parent 63478f2946
commit edf43ae76f
51 changed files with 451 additions and 330 deletions
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8
test_regress/t/t_flag_comp_limit_parens.v
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@ -4,11 +4,9 @@
// SPDX-FileCopyrightText: 2021 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
r
);
input real r;
module t (
input real r
);
initial begin
$display("%g", $cos($cos($cos($cos($cos($cos($cos($cos(r + 0.1)))))))));

4
test_regress/t/t_inst_pin_realnreal.v
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@ -5,8 +5,8 @@
// SPDX-License-Identifier: CC0-1.0
module t (
input clk
);
input clk
);
integer cyc; initial cyc=1;

139
test_regress/t/t_interface.v
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@ -5,17 +5,16 @@
// SPDX-License-Identifier: CC0-1.0
module t (
input clk
input clk
);
logic rst = 1'b1; // reset
logic rst = 1'b1; // reset
integer rst_cnt = 0;
// reset is removed after a delay
always @ (posedge clk)
begin
always @(posedge clk) begin
rst_cnt <= rst_cnt + 1;
rst <= rst_cnt <= 3;
rst <= rst_cnt <= 3;
end
// counters
@ -24,41 +23,41 @@ module t (
int cnt_drn;
// add all counters
assign cnt = cnt_src + cnt_drn + inf.cnt;
assign cnt = cnt_src + cnt_drn + ifc.cnt;
// finish report
always @ (posedge clk)
if (cnt == 3*16) begin
$write("*-* All Finished *-*\n");
$finish;
end
always @(posedge clk)
if (cnt == 3 * 16) begin
$write("*-* All Finished *-*\n");
$finish;
end
// interface instance
handshake inf (
.clk (clk),
.rst (rst)
handshake ifc (
.clk(clk),
.rst(rst)
);
// source instance
source #(
.RW (8),
.RP (8'b11100001)
.RW(8),
.RP(8'b11100001)
) source (
.clk (clk),
.rst (rst),
.inf (inf),
.cnt (cnt_src)
.clk(clk),
.rst(rst),
.ifc(ifc),
.cnt(cnt_src)
);
// drain instance
drain #(
.RW (8),
.RP (8'b11010100)
.RW(8),
.RP(8'b11010100)
) drain (
.clk (clk),
.rst (rst),
.inf (inf),
.cnt (cnt_drn)
.clk(clk),
.rst(rst),
.ifc(ifc),
.cnt(cnt_drn)
);
endmodule : t
@ -66,10 +65,10 @@ endmodule : t
// interface definition
interface handshake #(
parameter int unsigned WC = 32
)(
input logic clk,
input logic rst
parameter int unsigned WC = 32
) (
input logic clk,
input logic rst
);
// modport signals
@ -81,87 +80,81 @@ interface handshake #(
integer cnt; // counter
// source
modport src (
output req,
input grt
);
modport src(output req, input grt);
// drain
modport drn (
input req,
output grt
);
modport drn(input req, output grt);
// incremet condition
assign inc = req & grt;
// local logic (counter)
always @ (posedge clk, posedge rst)
if (rst) cnt <= '0;
else cnt <= cnt + {31'h0, inc};
always @(posedge clk, posedge rst)
if (rst) cnt <= '0;
else cnt <= cnt + {31'h0, inc};
endinterface : handshake
// source module
module source #(
// random generator parameters
parameter int unsigned RW=1, // LFSR width
parameter bit [RW-1:0] RP='0, // LFSR polinom
parameter bit [RW-1:0] RR='1 // LFSR reset state
)(
input logic clk,
input logic rst,
handshake.src inf,
output integer cnt
// random generator parameters
parameter int unsigned RW = 1, // LFSR width
parameter bit [RW-1:0] RP = '0, // LFSR polinom
parameter bit [RW-1:0] RR = '1 // LFSR reset state
) (
input logic clk,
input logic rst,
handshake.src ifc,
output integer cnt
);
// LFSR
logic [RW-1:0] rnd;
// LFSR in Galois form
always @ (posedge clk, posedge rst)
if (rst) rnd <= RR;
else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);
always @(posedge clk, posedge rst)
if (rst) rnd <= RR;
else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);
// counter
always @ (posedge clk, posedge rst)
if (rst) cnt <= 32'd0;
else cnt <= cnt + {31'd0, (inf.req & inf.grt)};
always @(posedge clk, posedge rst)
if (rst) cnt <= 32'd0;
else cnt <= cnt + {31'd0, (ifc.req & ifc.grt)};
// request signal
assign inf.req = rnd[0];
assign ifc.req = rnd[0];
endmodule : source
// drain module
module drain #(
// random generator parameters
parameter int unsigned RW=1, // LFSR width
parameter bit [RW-1:0] RP='0, // LFSR polinom
parameter bit [RW-1:0] RR='1 // LFSR reset state
)(
input logic clk,
input logic rst,
handshake.drn inf,
output integer cnt
// random generator parameters
parameter int unsigned RW = 1, // LFSR width
parameter bit [RW-1:0] RP = '0, // LFSR polinom
parameter bit [RW-1:0] RR = '1 // LFSR reset state
) (
input logic clk,
input logic rst,
handshake.drn ifc,
output integer cnt
);
// LFSR
logic [RW-1:0] rnd;
// LFSR in Galois form
always @ (posedge clk, posedge rst)
if (rst) rnd <= RR;
else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);
always @(posedge clk, posedge rst)
if (rst) rnd <= RR;
else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);
// counter
always @ (posedge clk, posedge rst)
if (rst) cnt <= 32'd0;
else cnt <= cnt + {31'd0, (inf.req & inf.grt)};
always @(posedge clk, posedge rst)
if (rst) cnt <= 32'd0;
else cnt <= cnt + {31'd0, (ifc.req & ifc.grt)};
// grant signal
assign inf.grt = rnd[0];
assign ifc.grt = rnd[0];
endmodule : drain

16
test_regress/t/t_interface_generic.v
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@ -4,7 +4,7 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf;
interface ifc;
int v;
endinterface
@ -12,7 +12,10 @@ interface inf2;
int k;
endinterface
module GenericModule (interface a, interface b);
module GenericModule (
interface a,
interface b
);
initial begin
#1;
if (a.v != 7) $stop;
@ -21,9 +24,12 @@ module GenericModule (interface a, interface b);
endmodule
module t;
inf inf_inst();
inf2 inf_inst2();
GenericModule genericModule (inf_inst, inf_inst2);
ifc inf_inst ();
inf2 inf_inst2 ();
GenericModule genericModule (
inf_inst,
inf_inst2
);
initial begin
inf_inst.v = 7;
#2;

20
test_regress/t/t_interface_generic2.v
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@ -4,7 +4,7 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf;
interface ifc;
int v;
endinterface
@ -12,7 +12,12 @@ interface inf2;
int k;
endinterface
module GenericModule (logic[31:0] l1, interface a, logic[31:0] l2, interface b);
module GenericModule (
logic [31:0] l1,
interface a,
logic [31:0] l2,
interface b
);
initial begin
#1;
if (l1 != 87) $stop;
@ -23,9 +28,14 @@ module GenericModule (logic[31:0] l1, interface a, logic[31:0] l2, interface b);
endmodule
module t;
inf inf_inst();
inf2 inf_inst2();
GenericModule genericModule (87, inf_inst, 73, inf_inst2);
ifc inf_inst ();
inf2 inf_inst2 ();
GenericModule genericModule (
87,
inf_inst,
73,
inf_inst2
);
initial begin
inf_inst.v = 7;
inf_inst2.k = 9;

8
test_regress/t/t_interface_generic_array.v
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@ -4,11 +4,13 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf;
interface ifc;
int v;
endinterface
module GenericModule (interface a);
module GenericModule (
interface a
);
initial begin
#1;
if (a.v != 7) $stop;
@ -17,7 +19,7 @@ module GenericModule (interface a);
endmodule
module t;
inf inf_inst[3]();
ifc inf_inst[3] ();
GenericModule genericModule (inf_inst[2]);
initial begin
inf_inst[2].v = 7;

26
test_regress/t/t_interface_generic_array2.v
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@ -4,11 +4,13 @@
// SPDX-FileCopyrightText: 2026 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf;
interface ifc;
int v;
endinterface
module GenericModule1D (interface a[4]);
module GenericModule1D (
interface a[4]
);
initial begin
#1;
if (a[0].v != 'hdead) $stop;
@ -18,7 +20,9 @@ module GenericModule1D (interface a[4]);
end
endmodule
module GenericModule2D (interface a[2][2]);
module GenericModule2D (
interface a[2][2]
);
initial begin
#3;
if (a[0][0].v != 'hdead) $stop;
@ -28,7 +32,9 @@ module GenericModule2D (interface a[2][2]);
end
endmodule
module GenericModuleRng (interface a[5:3]);
module GenericModuleRng (
interface a[5:3]
);
initial begin
#5;
if (a[3].v != 'hdead) $stop;
@ -38,12 +44,12 @@ module GenericModuleRng (interface a[5:3]);
endmodule
module t;
inf inf1d[4]();
inf inf2d[2][2]();
inf infrng[5:3]();
GenericModule1D mod1d(inf1d);
GenericModule2D mod2d(inf2d);
GenericModuleRng modrng(infrng);
ifc inf1d[4] ();
ifc inf2d[2][2] ();
ifc infrng[5:3] ();
GenericModule1D mod1d (inf1d);
GenericModule2D mod2d (inf2d);
GenericModuleRng modrng (infrng);
initial begin
inf1d[0].v = 'hdead;
inf1d[1].v = 'hbeef;

16
test_regress/t/t_interface_generic_bad.out
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@ -1,13 +1,13 @@
%Warning-PINMISSING: t/t_interface_generic_bad.v:26:17: Instance has missing pin: 'b'
26 | GenericModule genericModule (inf_inst);
%Warning-PINMISSING: t/t_interface_generic_bad.v:29:17: Instance has missing pin: 'b'
29 | GenericModule genericModule (inf_inst);
| ^~~~~~~~~~~~~
t/t_interface_generic_bad.v:15:46: ... Location of port declaration
15 | module GenericModule (interface a, interface b);
| ^
t/t_interface_generic_bad.v:17:15: ... Location of port declaration
17 | interface b
| ^
... For warning description see https://verilator.org/warn/PINMISSING?v=latest
... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.
%Error: t/t_interface_generic_bad.v:15:46: Interface port 'b' is not connected to interface/modport pin expression
15 | module GenericModule (interface a, interface b);
| ^
%Error: t/t_interface_generic_bad.v:17:15: Interface port 'b' is not connected to interface/modport pin expression
17 | interface b
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

11
test_regress/t/t_interface_generic_bad.v
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@ -4,7 +4,7 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf;
interface ifc;
int v;
endinterface
@ -12,7 +12,10 @@ interface inf2;
int k;
endinterface
module GenericModule (interface a, interface b);
module GenericModule (
interface a,
interface b
);
initial begin
#1;
if (a.v != 7) $stop;
@ -21,8 +24,8 @@ module GenericModule (interface a, interface b);
endmodule
module t;
inf inf_inst();
inf2 inf_inst2();
ifc inf_inst ();
inf2 inf_inst2 ();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 7;

28
test_regress/t/t_interface_generic_bad2.out
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@ -1,24 +1,24 @@
%Error: t/t_interface_generic_bad2.v:15:9: Can't find definition of scope/variable: 'b'
15 | if (b.k != 9) $stop;
%Error: t/t_interface_generic_bad2.v:17:9: Can't find definition of scope/variable: 'b'
17 | if (b.k != 9) $stop;
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_interface_generic_bad2.v:20:3: Cannot find file containing interface: 'inf'
20 | inf inf_inst();
%Error: t/t_interface_generic_bad2.v:22:3: Cannot find file containing interface: 'ifc'
22 | ifc inf_inst ();
| ^~~
%Error: t/t_interface_generic_bad2.v:21:32: Found definition of 'inf_inst' as a CELL but expected a variable
21 | GenericModule genericModule (inf_inst);
%Error: t/t_interface_generic_bad2.v:23:32: Found definition of 'inf_inst' as a CELL but expected a variable
23 | GenericModule genericModule (inf_inst);
| ^~~~~~~~
%Error: t/t_interface_generic_bad2.v:21:32: Expected an interface but 'inf_inst' is not an interface
21 | GenericModule genericModule (inf_inst);
%Error: t/t_interface_generic_bad2.v:23:32: Expected an interface but 'inf_inst' is not an interface
23 | GenericModule genericModule (inf_inst);
| ^~~~~~~~
%Error: t/t_interface_generic_bad2.v:23:5: Dotted reference to instance that refers to missing module/interface: 'inf'
23 | inf_inst.v = 7;
%Error: t/t_interface_generic_bad2.v:25:5: Dotted reference to instance that refers to missing module/interface: 'ifc'
25 | inf_inst.v = 7;
| ^~~~~~~~
%Error: t/t_interface_generic_bad2.v:23:14: Can't find definition of 'v' in dotted variable/method: 'inf_inst.v'
23 | inf_inst.v = 7;
%Error: t/t_interface_generic_bad2.v:25:14: Can't find definition of 'v' in dotted variable/method: 'inf_inst.v'
25 | inf_inst.v = 7;
| ^
%Error: t/t_interface_generic_bad2.v:24:5: Can't find definition of scope/variable: 'inf_inst2'
%Error: t/t_interface_generic_bad2.v:26:5: Can't find definition of scope/variable: 'inf_inst2'
: ... Suggested alternative: 'inf_inst'
24 | inf_inst2.k = 9;
26 | inf_inst2.k = 9;
| ^~~~~~~~~
%Error: Exiting due to

8
test_regress/t/t_interface_generic_bad2.v
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@ -4,11 +4,13 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
class inf;
class ifc;
int v;
endclass
module GenericModule (interface a);
module GenericModule (
interface a
);
initial begin
#1;
if (a.v != 7) $stop;
@ -17,7 +19,7 @@ module GenericModule (interface a);
endmodule
module t;
inf inf_inst();
ifc inf_inst ();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 7;

14
test_regress/t/t_interface_generic_bad3.out
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@ -1,12 +1,12 @@
%Error: t/t_interface_generic_bad3.v:15:9: Can't find definition of scope/variable: 'b'
15 | if (b.k != 9) $stop;
%Error: t/t_interface_generic_bad3.v:17:9: Can't find definition of scope/variable: 'b'
17 | if (b.k != 9) $stop;
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error-PINNOTFOUND: t/t_interface_generic_bad3.v:21:42: Pin not found: '__pinNumber2'
21 | GenericModule genericModule (inf_inst, inf_inst);
| ^~~~~~~~
: ... Location of instance's module declaration
11 | module GenericModule (interface a);
%Error-PINNOTFOUND: t/t_interface_generic_bad3.v:25:7: Pin not found: '__pinNumber2'
25 | inf_inst
| ^~~~~~~~
: ... Location of instance's module declaration
11 | module GenericModule (
| ^~~~~~~~~~~~~
... For error description see https://verilator.org/warn/PINNOTFOUND?v=latest
%Error: Exiting due to

13
test_regress/t/t_interface_generic_bad3.v
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@ -4,11 +4,13 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf;
interface ifc;
int v;
endinterface
module GenericModule (interface a);
module GenericModule (
interface a
);
initial begin
#1;
if (a.v != 7) $stop;
@ -17,8 +19,11 @@ module GenericModule (interface a);
endmodule
module t;
inf inf_inst();
GenericModule genericModule (inf_inst, inf_inst);
ifc inf_inst ();
GenericModule genericModule (
inf_inst,
inf_inst
);
initial begin
inf_inst.v = 7;
$write("*-* All Finished *-*\n");

6
test_regress/t/t_interface_generic_bad4.out
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@ -1,5 +1,5 @@
%Error: t/t_interface_generic_bad4.v:26:32: Generic interfaces can only connect to an interface and 'inf_inst' is of type 'int'
26 | GenericModule genericModule (inf_inst, inf_inst2);
| ^~~~~~~~
%Error: t/t_interface_generic_bad4.v:30:7: Generic interfaces can only connect to an interface and 'inf_inst' is of type 'int'
30 | inf_inst,
| ^~~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

14
test_regress/t/t_interface_generic_bad4.v
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@ -4,7 +4,7 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf;
interface ifc;
int v;
endinterface
@ -12,7 +12,10 @@ interface inf2;
int k;
endinterface
module GenericModule (interface a, interface b);
module GenericModule (
interface a,
interface b
);
initial begin
#1;
if (a.v != 7) $stop;
@ -22,8 +25,11 @@ endmodule
module t;
int inf_inst;
inf2 inf_inst2();
GenericModule genericModule (inf_inst, inf_inst2);
inf2 inf_inst2 ();
GenericModule genericModule (
inf_inst,
inf_inst2
);
initial begin
inf_inst.v = 7;
inf_inst2.k = 9;

8
test_regress/t/t_interface_generic_function.v
View File

@ -4,7 +4,7 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf;
interface ifc;
int v;
function int get();
return v;
@ -15,7 +15,9 @@ interface inf2;
int k;
endinterface
module GenericModule (interface a);
module GenericModule (
interface a
);
initial begin
#1;
if (a.get() != 4) $stop;
@ -23,7 +25,7 @@ module GenericModule (interface a);
endmodule
module t;
inf inf_inst();
ifc inf_inst ();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 4;

4
test_regress/t/t_interface_generic_function_bad.out
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@ -1,6 +1,6 @@
%Error: t/t_interface_generic_function_bad.v:14:11: Can't find definition of 'get' in dotted task/function: 'a.get'
%Error: t/t_interface_generic_function_bad.v:16:11: Can't find definition of 'get' in dotted task/function: 'a.get'
: ... note: In instance 't.genericModule'
14 | if (a.get() != 4) $stop;
16 | if (a.get() != 4) $stop;
| ^~~
... Known scopes under 'get': <no instances found>
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.

8
test_regress/t/t_interface_generic_function_bad.v
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@ -4,11 +4,13 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf;
interface ifc;
int v;
endinterface
module GenericModule (interface a);
module GenericModule (
interface a
);
initial begin
#1;
if (a.get() != 4) $stop;
@ -16,7 +18,7 @@ module GenericModule (interface a);
endmodule
module t;
inf inf_inst();
ifc inf_inst ();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 4;

24
test_regress/t/t_interface_generic_iface_forward.v
View File

@ -9,11 +9,15 @@
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
interface inf #(parameter int PARAM = 1);
interface ifc #(
parameter int PARAM = 1
);
logic [PARAM-1:0] v;
endinterface
module leaf (interface d);
module leaf (
interface d
);
initial begin
#1;
`checkd(d.v, 13);
@ -21,17 +25,21 @@ module leaf (interface d);
end
endmodule
module mid2 (interface c);
leaf leaf_i(.d(c));
module mid2 (
interface c
);
leaf leaf_i (.d(c));
endmodule
module mid1 (interface b);
mid2 mid2_i(.c(b));
module mid1 (
interface b
);
mid2 mid2_i (.c(b));
endmodule
module t;
inf #(.PARAM(5)) a();
mid1 mid1_i(.b(a));
ifc #(.PARAM(5)) a ();
mid1 mid1_i (.b(a));
initial begin
a.v = 13;
$write("*-* All Finished *-*\n");

24
test_regress/t/t_interface_generic_iface_forward_concrete.v
View File

@ -9,11 +9,15 @@
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
interface inf #(parameter int PARAM = 1);
interface ifc #(
parameter int PARAM = 1
);
logic [PARAM-1:0] v;
endinterface
module leaf (inf d);
module leaf (
ifc d
);
initial begin
#1;
`checkd(d.v, 13);
@ -21,17 +25,21 @@ module leaf (inf d);
end
endmodule
module mid2 (interface c);
leaf leaf_i(.d(c));
module mid2 (
interface c
);
leaf leaf_i (.d(c));
endmodule
module mid1 (interface b);
mid2 mid2_i(.c(b));
module mid1 (
interface b
);
mid2 mid2_i (.c(b));
endmodule
module t;
inf #(.PARAM(5)) a();
mid1 mid1_i(.b(a));
ifc #(.PARAM(5)) a ();
mid1 mid1_i (.b(a));
initial begin
a.v = 13;
$write("*-* All Finished *-*\n");

20
test_regress/t/t_interface_generic_iface_forward_param.v
View File

@ -9,11 +9,15 @@
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
interface inf #(parameter int PARAM = 1);
interface ifc #(
parameter int PARAM = 1
);
logic [PARAM-1:0] v;
endinterface
module leaf (inf c);
module leaf (
ifc c
);
initial begin
#1;
`checkd(c.v, 13)
@ -21,13 +25,17 @@ module leaf (inf c);
end
endmodule
module mid #(int PARAM = 1) (interface b);
leaf leaf_i(.c(b));
initial `checkd(PARAM,7)
module mid #(
int PARAM = 1
) (
interface b
);
leaf leaf_i (.c(b));
initial `checkd(PARAM, 7)
endmodule
module t;
inf #(.PARAM(5)) a();
ifc #(.PARAM(5)) a ();
mid #(.PARAM(7)) mid_i (.b(a));
initial begin
a.v = 13;

12
test_regress/t/t_interface_generic_iface_param.v
View File

@ -4,11 +4,15 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf #(PARAM);
logic[PARAM-1:0] v;
interface ifc #(
PARAM
);
logic [PARAM-1:0] v;
endinterface
module GenericModule (interface a);
module GenericModule (
interface a
);
initial begin
#1;
if (a.v != 7) $stop;
@ -17,7 +21,7 @@ module GenericModule (interface a);
endmodule
module t;
inf #(.PARAM(13)) inf_inst();
ifc #(.PARAM(13)) inf_inst ();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 7;

20
test_regress/t/t_interface_generic_iface_param_cell_ref.v
View File

@ -9,22 +9,30 @@
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
interface inf #(parameter int PARAM = 1);
interface ifc #(
parameter int PARAM = 1
);
logic [PARAM-1:0] v;
modport mp (input v);
modport mp(input v);
endinterface
module Leaf #(parameter int PARAM = 1) (inf.mp leaf_a);
module Leaf #(
parameter int PARAM = 1
) (
ifc.mp leaf_a
);
initial begin
#1;
`checkd(leaf_a.PARAM, PARAM);
end
endmodule
module GenericModule (interface.mp a);
module GenericModule (
interface.mp a
);
localparam LOC_PARAM = a.PARAM;
// A generic interface's parameter, parameterizing a sibling interface cell
inf #(.PARAM(LOC_PARAM)) nested_inst();
ifc #(.PARAM(LOC_PARAM)) nested_inst ();
Leaf #(.PARAM(LOC_PARAM)) leaf (nested_inst);
initial begin
#1;
@ -35,7 +43,7 @@ module GenericModule (interface.mp a);
endmodule
module t;
inf #(.PARAM(13)) inf_inst();
ifc #(.PARAM(13)) inf_inst ();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 7;

14
test_regress/t/t_interface_generic_iface_param_dotchain.v
View File

@ -14,15 +14,19 @@ interface leaf_if;
logic dummy;
endinterface
interface inf #(parameter int PARAM = 1);
interface ifc #(
parameter int PARAM = 1
);
logic [PARAM-1:0] v;
// Makes 'a.nested.LEAF_PARAM' a chained Dot, whose lhsp is itself a Dot
leaf_if nested();
leaf_if nested ();
parameter int ARR[2] = '{PARAM, PARAM + 1};
modport mp (input v);
modport mp(input v);
endinterface
module GenericModule (interface.mp a);
module GenericModule (
interface.mp a
);
localparam int LOC_CHAIN = a.nested.LEAF_PARAM;
// Makes the Dot's rhsp an indexed select, not a plain identifier
localparam int LOC_ARR = a.ARR[0];
@ -35,7 +39,7 @@ module GenericModule (interface.mp a);
endmodule
module t;
inf #(.PARAM(13)) inf_inst();
ifc #(.PARAM(13)) inf_inst ();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 7;

12
test_regress/t/t_interface_generic_iface_param_genblock.v
View File

@ -9,10 +9,12 @@
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
interface inf #(parameter int PARAM = 1);
interface ifc #(
parameter int PARAM = 1
);
logic [PARAM-1:0] v;
// A non-Var/non-GenBlock item the member gather must skip past
modport mp (input v);
modport mp(input v);
if (1) begin : blk_decoy
// Same name as the real parameter below, but not a parameter
logic PARAM_IF;
@ -25,7 +27,9 @@ interface inf #(parameter int PARAM = 1);
end
endinterface
module GenericModule (interface.mp a);
module GenericModule (
interface.mp a
);
// Two references to the same member, so the second reuses the gathered members
localparam int LOC_PARAM1 = a.PARAM;
localparam int LOC_PARAM2 = a.PARAM;
@ -43,7 +47,7 @@ module GenericModule (interface.mp a);
endmodule
module t;
inf #(.PARAM(13)) inf_inst();
ifc #(.PARAM(13)) inf_inst ();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 7;

14
test_regress/t/t_interface_generic_iface_param_modgenblock.v
View File

@ -9,18 +9,22 @@
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
interface inf #(parameter int PARAM = 1);
interface ifc #(
parameter int PARAM = 1
);
logic [PARAM-1:0] v;
modport mp (input v);
modport mp(input v);
endinterface
module GenericModule (interface.mp a);
module GenericModule (
interface.mp a
);
// Dotted localparam inside a generate block, feeding a sibling cell in the same block.
// The interface-ref gather must recurse in here yet still find port 'a' at module level.
// Generate blocks on the interface side are covered by t_interface_generic_iface_param_genblock.
if (1) begin : blk
localparam int LOC_PARAM = a.PARAM;
inf #(.PARAM(LOC_PARAM)) inner();
ifc #(.PARAM(LOC_PARAM)) inner ();
end
initial begin
#1;
@ -31,7 +35,7 @@ module GenericModule (interface.mp a);
endmodule
module t;
inf #(.PARAM(13)) inf_inst();
ifc #(.PARAM(13)) inf_inst ();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 7;

22
test_regress/t/t_interface_generic_iface_param_ref.v
View File

@ -9,18 +9,20 @@
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
interface inf #(int PARAM = 0);
logic[PARAM-1:0] v;
interface ifc #(
int PARAM = 0
);
logic [PARAM-1:0] v;
modport port_in (
input v
);
modport port_out (
output v
);
modport port_in(input v);
modport port_out(output v);
endinterface
module GenericModule #(PARAM=0) (interface.port_in a);
module GenericModule #(
PARAM = 0
) (
interface.port_in a
);
localparam int LOC_PARAM = a.PARAM;
initial begin
#1;
@ -31,7 +33,7 @@ module GenericModule #(PARAM=0) (interface.port_in a);
endmodule
module t;
inf #(.PARAM(13)) inf_inst();
ifc #(.PARAM(13)) inf_inst ();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 7;

4
test_regress/t/t_interface_generic_iface_param_ref_bad.out
View File

@ -1,6 +1,6 @@
%Error: t/t_interface_generic_iface_param_ref_bad.v:19:32: Can't find definition of 'NONEXISTENT_PARAM' in dotted variable/method: 'a.NONEXISTENT_PARAM'
%Error: t/t_interface_generic_iface_param_ref_bad.v:23:32: Can't find definition of 'NONEXISTENT_PARAM' in dotted variable/method: 'a.NONEXISTENT_PARAM'
: ... note: In instance 't.genericModule'
19 | localparam int LOC_PARAM = a.NONEXISTENT_PARAM;
23 | localparam int LOC_PARAM = a.NONEXISTENT_PARAM;
| ^~~~~~~~~~~~~~~~~
... Known scopes under 'a': <no instances found>
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.

12
test_regress/t/t_interface_generic_iface_param_ref_bad.v
View File

@ -9,12 +9,16 @@
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
interface inf #(parameter int PARAM = 1);
interface ifc #(
parameter int PARAM = 1
);
logic [PARAM-1:0] v;
modport mp (input v);
modport mp(input v);
endinterface
module GenericModule (interface.mp a);
module GenericModule (
interface.mp a
);
// A member that does not exist on the (now concrete) interface
localparam int LOC_PARAM = a.NONEXISTENT_PARAM;
initial begin
@ -24,7 +28,7 @@ module GenericModule (interface.mp a);
endmodule
module t;
inf #(.PARAM(13)) inf_inst();
ifc #(.PARAM(13)) inf_inst ();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 7;

11
test_regress/t/t_interface_generic_mod_param.v
View File

@ -4,11 +4,16 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf;
interface ifc;
int v;
endinterface
module GenericModule#(type T, type Y = int) (interface a);
module GenericModule #(
type T,
type Y = int
) (
interface a
);
initial begin
#1;
if (a.v != 7) $stop;
@ -16,7 +21,7 @@ module GenericModule#(type T, type Y = int) (interface a);
endmodule
module t;
inf inf_inst();
ifc inf_inst ();
GenericModule #(string) genericModule (inf_inst);
initial begin
inf_inst.v = 7;

12
test_regress/t/t_interface_generic_modport.v
View File

@ -4,14 +4,14 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf;
interface ifc;
int v;
modport mp (
input v
);
modport mp(input v);
endinterface
module GenericModule (interface.mp a);
module GenericModule (
interface.mp a
);
initial begin
#1;
if (a.v != 7) $stop;
@ -19,7 +19,7 @@ module GenericModule (interface.mp a);
endmodule
module t;
inf inf_inst();
ifc inf_inst ();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 7;

12
test_regress/t/t_interface_generic_modport2.v
View File

@ -4,21 +4,21 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf;
interface ifc;
int v;
modport mp (
output v
);
modport mp(output v);
endinterface
module GenericModule (interface.mp a);
module GenericModule (
interface.mp a
);
initial begin
a.v = 7;
end
endmodule
module t;
inf inf_inst();
ifc inf_inst ();
GenericModule genericModule (inf_inst);
initial begin
#1;

6
test_regress/t/t_interface_generic_modport_bad.out
View File

@ -1,5 +1,5 @@
%Error: t/t_interface_generic_modport_bad.v:11:33: Modport not found under interface 'inf': 'mp'
11 | module GenericModule (interface.mp a);
| ^~
%Error: t/t_interface_generic_modport_bad.v:12:15: Modport not found under interface 'ifc': 'mp'
12 | interface.mp a
| ^~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

8
test_regress/t/t_interface_generic_modport_bad.v
View File

@ -4,11 +4,13 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf;
interface ifc;
int v;
endinterface
module GenericModule (interface.mp a);
module GenericModule (
interface.mp a
);
initial begin
#1;
if (a.v != 7) $stop;
@ -16,7 +18,7 @@ module GenericModule (interface.mp a);
endmodule
module t;
inf inf_inst();
ifc inf_inst ();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 7;

12
test_regress/t/t_interface_generic_modport_bad2.v
View File

@ -4,14 +4,14 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf;
interface ifc;
int v;
modport mp (
input v
);
modport mp(input v);
endinterface
module GenericModule (interface.mp a);
module GenericModule (
interface.mp a
);
initial begin
#1;
a.v = 10;
@ -19,7 +19,7 @@ module GenericModule (interface.mp a);
endmodule
module t;
inf inf_inst();
ifc inf_inst ();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 7;

12
test_regress/t/t_interface_generic_modport_bad3.v
View File

@ -4,15 +4,15 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf;
interface ifc;
int v;
int o;
modport mp (
input o
);
modport mp(input o);
endinterface
module GenericModule (interface.mp a);
module GenericModule (
interface.mp a
);
initial begin
#1;
if (a.v != 7) $stop;
@ -20,7 +20,7 @@ module GenericModule (interface.mp a);
endmodule
module t;
inf inf_inst();
ifc inf_inst ();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 7;

12
test_regress/t/t_interface_generic_modport_function.v
View File

@ -4,21 +4,21 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf;
interface ifc;
int v;
function int get();
return v;
endfunction
modport mp(
import get
);
modport mp(import get);
endinterface
interface inf2;
int k;
endinterface
module GenericModule (interface.mp a);
module GenericModule (
interface.mp a
);
initial begin
#1;
if (a.get() != 4) $stop;
@ -26,7 +26,7 @@ module GenericModule (interface.mp a);
endmodule
module t;
inf inf_inst();
ifc inf_inst ();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 4;

14
test_regress/t/t_interface_generic_modport_function2.v
View File

@ -4,32 +4,32 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf;
interface ifc;
int v;
function int get();
return v;
endfunction
modport mp(
output v
);
modport mp(output v);
endinterface
interface inf2;
int k;
endinterface
module GenericModule (interface.mp a);
module GenericModule (
interface.mp a
);
initial begin
a.v = 5;
end
endmodule
module t;
inf inf_inst();
ifc inf_inst ();
GenericModule genericModule (inf_inst);
initial begin
#1;
if(inf_inst.get() != 5) $stop;
if (inf_inst.get() != 5) $stop;
$write("*-* All Finished *-*\n");
$finish;
end

12
test_regress/t/t_interface_generic_modport_function_bad.v
View File

@ -4,21 +4,21 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf;
interface ifc;
int v;
function int get();
return v;
endfunction
modport mp(
input v
);
modport mp(input v);
endinterface
interface inf2;
int k;
endinterface
module GenericModule (interface.mp a);
module GenericModule (
interface.mp a
);
initial begin
#1;
if (a.get() != 4) $stop;
@ -26,7 +26,7 @@ module GenericModule (interface.mp a);
endmodule
module t;
inf inf_inst();
ifc inf_inst ();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 4;

12
test_regress/t/t_interface_generic_modport_param.v
View File

@ -4,16 +4,16 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf;
interface ifc;
localparam LPARAM = 12;
int v;
modport mp (
input v
);
modport mp(input v);
endinterface
module GenericModule (interface.mp a);
module GenericModule (
interface.mp a
);
initial begin
#1;
if (a.LPARAM != 12) $stop;
@ -22,7 +22,7 @@ module GenericModule (interface.mp a);
endmodule
module t;
inf inf_inst();
ifc inf_inst ();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 7;

13
test_regress/t/t_interface_generic_modport_task.v
View File

@ -4,25 +4,24 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf;
interface ifc;
int v;
task setup();
v = 3;
endtask
modport mp(
input v,
import setup
);
modport mp(input v, import setup);
endinterface
module GenericModule (interface.mp a);
module GenericModule (
interface.mp a
);
initial begin
a.setup();
end
endmodule
module t;
inf inf_inst();
ifc inf_inst ();
GenericModule genericModule (inf_inst);
initial begin
#1;

12
test_regress/t/t_interface_generic_modport_task2.v
View File

@ -4,17 +4,17 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf;
interface ifc;
int v;
task setup();
v = 3;
endtask
modport mp(
input v
);
modport mp(input v);
endinterface
module GenericModule (interface.mp a);
module GenericModule (
interface.mp a
);
initial begin
#1;
if (a.v != 3) $stop;
@ -22,7 +22,7 @@ module GenericModule (interface.mp a);
endmodule
module t;
inf inf_inst();
ifc inf_inst ();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.setup();

12
test_regress/t/t_interface_generic_modport_task_bad.v
View File

@ -4,28 +4,28 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf;
interface ifc;
int v;
task setup();
v = 3;
endtask
modport mp(
input v
);
modport mp(input v);
endinterface
interface inf2;
int k;
endinterface
module GenericModule (interface.mp a);
module GenericModule (
interface.mp a
);
initial begin
a.setup();
end
endmodule
module t;
inf inf_inst();
ifc inf_inst ();
GenericModule genericModule (inf_inst);
initial begin
#1;

16
test_regress/t/t_interface_generic_normal.v
View File

@ -4,11 +4,15 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf;
interface ifc;
int v;
endinterface
module GenericModule (interface a, inf b, interface c);
module GenericModule (
interface a,
ifc b,
interface c
);
initial begin
#1;
if (a.v != 7) $stop;
@ -18,8 +22,12 @@ module GenericModule (interface a, inf b, interface c);
endmodule
module t;
inf inf_inst[3]();
GenericModule genericModule (inf_inst[0], inf_inst[1], inf_inst[2]);
ifc inf_inst[3] ();
GenericModule genericModule (
inf_inst[0],
inf_inst[1],
inf_inst[2]
);
initial begin
inf_inst[0].v = 7;
inf_inst[1].v = 8;

14
test_regress/t/t_interface_generic_positional.v
View File

@ -4,11 +4,14 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf;
interface ifc;
int v;
endinterface
module GenericModule (interface a, interface b);
module GenericModule (
interface a,
interface b
);
initial begin
#1;
if (a.v != 7) $stop;
@ -16,8 +19,11 @@ module GenericModule (interface a, interface b);
endmodule
module t;
inf inf_inst[3]();
GenericModule genericModule (.a(inf_inst[1]), .b(inf_inst[2]));
ifc inf_inst[3] ();
GenericModule genericModule (
.a(inf_inst[1]),
.b(inf_inst[2])
);
initial begin
inf_inst[1].v = 7;
$write("*-* All Finished *-*\n");

16
test_regress/t/t_interface_generic_submod_param.v
View File

@ -4,7 +4,9 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
module sub #(parameter P);
module sub #(
parameter P
);
endmodule
package pkg;
@ -15,21 +17,23 @@ class B;
int x;
endclass
module Gm (interface a);
module Gm (
interface a
);
B b;
sub#(.P(pkg::A + $bits(b.x))) s();
sub #(.P(pkg::A + $bits(b.x))) s ();
initial begin
a.v = s.P;
end
endmodule
interface inf;
interface ifc;
int v;
endinterface
module t;
inf i();
Gm g(.a(i));
ifc i ();
Gm g (.a(i));
initial begin
#1;
if (i.v != 35) $stop;

8
test_regress/t/t_interface_generic_task.v
View File

@ -4,7 +4,7 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf;
interface ifc;
int v;
task setup();
v = 3;
@ -15,14 +15,16 @@ interface inf2;
int k;
endinterface
module GenericModule (interface a);
module GenericModule (
interface a
);
initial begin
a.setup();
end
endmodule
module t;
inf inf_inst();
ifc inf_inst ();
GenericModule genericModule (inf_inst);
initial begin
#1;

8
test_regress/t/t_interface_generic_task2.v
View File

@ -4,7 +4,7 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf;
interface ifc;
int v;
task setup();
v = 3;
@ -15,7 +15,9 @@ interface inf2;
int k;
endinterface
module GenericModule (interface a);
module GenericModule (
interface a
);
initial begin
#1;
if (a.v != 3) $stop;
@ -23,7 +25,7 @@ module GenericModule (interface a);
endmodule
module t;
inf inf_inst();
ifc inf_inst ();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.setup();

4
test_regress/t/t_interface_generic_task_bad.out
View File

@ -1,6 +1,6 @@
%Error: t/t_interface_generic_task_bad.v:17:7: Can't find definition of 'setup' in dotted task/function: 'a.setup'
%Error: t/t_interface_generic_task_bad.v:19:7: Can't find definition of 'setup' in dotted task/function: 'a.setup'
: ... note: In instance 't.genericModule'
17 | a.setup();
19 | a.setup();
| ^~~~~
... Known scopes under 'setup': <no instances found>
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.

8
test_regress/t/t_interface_generic_task_bad.v
View File

@ -4,7 +4,7 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
interface inf;
interface ifc;
int v;
endinterface
@ -12,14 +12,16 @@ interface inf2;
int k;
endinterface
module GenericModule (interface a);
module GenericModule (
interface a
);
initial begin
a.setup();
end
endmodule
module t;
inf inf_inst();
ifc inf_inst ();
GenericModule genericModule (inf_inst);
initial begin
#1;

18
test_regress/t/t_virtual_interface_nba_assign.v
View File

@ -9,7 +9,7 @@ interface clk_if;
bit clk;
endinterface
interface inf;
interface ifc;
bit clk;
bit v;
@ -22,14 +22,15 @@ class Clocker;
virtual clk_if clk;
task clock();
fork forever #1 clk.clk = ~clk.clk;
fork
forever #1 clk.clk = ~clk.clk;
join_none
endtask
endclass
module t;
clk_if c();
inf i();
clk_if c ();
ifc i ();
assign i.clk = c.clk;
Clocker clocker;
initial begin
@ -41,8 +42,9 @@ module t;
#5;
$stop;
end
initial @(posedge i.cb.v) begin
$write("*-* All Finished *-*\n");
$finish;
end
initial
@(posedge i.cb.v) begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule