46 lines
779 B
Systemverilog
46 lines
779 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2025 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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interface ifc;
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int v;
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endinterface
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interface inf2;
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int k;
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endinterface
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module GenericModule (
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logic [31:0] l1,
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interface a,
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logic [31:0] l2,
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interface b
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);
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initial begin
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#1;
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if (l1 != 87) $stop;
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if (a.v != 7) $stop;
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if (l2 != 73) $stop;
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if (b.k != 9) $stop;
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end
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endmodule
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module t;
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ifc inf_inst ();
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inf2 inf_inst2 ();
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GenericModule genericModule (
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87,
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inf_inst,
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73,
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inf_inst2
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);
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initial begin
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inf_inst.v = 7;
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inf_inst2.k = 9;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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