diff --git a/test_regress/t/t_flag_comp_limit_parens.v b/test_regress/t/t_flag_comp_limit_parens.v
index 8eeff374f..e5baa10e9 100644
--- a/test_regress/t/t_flag_comp_limit_parens.v
+++ b/test_regress/t/t_flag_comp_limit_parens.v
@@ -4,11 +4,9 @@
 // SPDX-FileCopyrightText: 2021 Wilson Snyder
 // SPDX-License-Identifier: CC0-1.0
 
-module t (/*AUTOARG*/
-  // Inputs
-  r
-  );
-  input real r;
+module t (
+    input real r
+);
 
   initial begin
     $display("%g", $cos($cos($cos($cos($cos($cos($cos($cos(r + 0.1)))))))));
diff --git a/test_regress/t/t_inst_pin_realnreal.v b/test_regress/t/t_inst_pin_realnreal.v
index 6b551989b..958232528 100644
--- a/test_regress/t/t_inst_pin_realnreal.v
+++ b/test_regress/t/t_inst_pin_realnreal.v
@@ -5,8 +5,8 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t (
-  input clk
-  );
+    input clk
+);
 
   integer cyc; initial cyc=1;
 
diff --git a/test_regress/t/t_interface.v b/test_regress/t/t_interface.v
index 071e007e4..93cd4db12 100644
--- a/test_regress/t/t_interface.v
+++ b/test_regress/t/t_interface.v
@@ -5,17 +5,16 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t (
-   input clk
+    input clk
 );
 
-  logic   rst = 1'b1;  // reset
+  logic rst = 1'b1;  // reset
   integer rst_cnt = 0;
 
   // reset is removed after a delay
-  always @ (posedge clk)
-  begin
+  always @(posedge clk) begin
     rst_cnt <= rst_cnt + 1;
-    rst     <= rst_cnt <= 3;
+    rst <= rst_cnt <= 3;
   end
 
   // counters
@@ -24,41 +23,41 @@ module t (
   int cnt_drn;
 
   // add all counters
-  assign cnt = cnt_src + cnt_drn + inf.cnt;
+  assign cnt = cnt_src + cnt_drn + ifc.cnt;
 
   // finish report
-  always @ (posedge clk)
-  if (cnt == 3*16) begin
-    $write("*-* All Finished *-*\n");
-    $finish;
-  end
+  always @(posedge clk)
+    if (cnt == 3 * 16) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+    end
 
   // interface instance
-  handshake inf (
-    .clk (clk),
-    .rst (rst)
+  handshake ifc (
+      .clk(clk),
+      .rst(rst)
   );
 
   // source instance
   source #(
-    .RW  (8),
-    .RP  (8'b11100001)
+      .RW(8),
+      .RP(8'b11100001)
   ) source (
-    .clk  (clk),
-    .rst  (rst),
-    .inf  (inf),
-    .cnt  (cnt_src)
+      .clk(clk),
+      .rst(rst),
+      .ifc(ifc),
+      .cnt(cnt_src)
   );
 
   // drain instance
   drain #(
-    .RW  (8),
-    .RP  (8'b11010100)
+      .RW(8),
+      .RP(8'b11010100)
   ) drain (
-    .clk  (clk),
-    .rst  (rst),
-    .inf  (inf),
-    .cnt  (cnt_drn)
+      .clk(clk),
+      .rst(rst),
+      .ifc(ifc),
+      .cnt(cnt_drn)
   );
 
 endmodule : t
@@ -66,10 +65,10 @@ endmodule : t
 
 // interface definition
 interface handshake #(
-  parameter int unsigned WC = 32
-)(
-  input logic clk,
-  input logic rst
+    parameter int unsigned WC = 32
+) (
+    input logic clk,
+    input logic rst
 );
 
   // modport signals
@@ -81,87 +80,81 @@ interface handshake #(
   integer cnt;  // counter
 
   // source
-  modport src (
-    output req,
-    input  grt
-  );
+  modport src(output req, input grt);
 
   // drain
-  modport drn (
-    input  req,
-    output grt
-  );
+  modport drn(input req, output grt);
 
   // incremet condition
   assign inc = req & grt;
 
   // local logic (counter)
-  always @ (posedge clk, posedge rst)
-  if (rst) cnt <= '0;
-  else     cnt <= cnt + {31'h0, inc};
+  always @(posedge clk, posedge rst)
+    if (rst) cnt <= '0;
+    else cnt <= cnt + {31'h0, inc};
 
 endinterface : handshake
 
 
 // source module
 module source #(
-  // random generator parameters
-  parameter int unsigned RW=1,   // LFSR width
-  parameter bit [RW-1:0] RP='0,  // LFSR polinom
-  parameter bit [RW-1:0] RR='1   // LFSR reset state
-)(
-  input logic    clk,
-  input logic    rst,
-  handshake.src  inf,
-  output integer cnt
+    // random generator parameters
+    parameter int unsigned RW = 1,  // LFSR width
+    parameter bit [RW-1:0] RP = '0,  // LFSR polinom
+    parameter bit [RW-1:0] RR = '1  // LFSR reset state
+) (
+    input logic clk,
+    input logic rst,
+    handshake.src ifc,
+    output integer cnt
 );
 
   // LFSR
   logic [RW-1:0] rnd;
 
   // LFSR in Galois form
-  always @ (posedge clk, posedge rst)
-  if (rst) rnd <= RR;
-  else     rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);
+  always @(posedge clk, posedge rst)
+    if (rst) rnd <= RR;
+    else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);
 
   // counter
-  always @ (posedge clk, posedge rst)
-  if (rst) cnt <= 32'd0;
-  else     cnt <= cnt + {31'd0, (inf.req & inf.grt)};
+  always @(posedge clk, posedge rst)
+    if (rst) cnt <= 32'd0;
+    else cnt <= cnt + {31'd0, (ifc.req & ifc.grt)};
 
   // request signal
-  assign inf.req = rnd[0];
+  assign ifc.req = rnd[0];
 
 endmodule : source
 
 
 // drain module
 module drain #(
-  // random generator parameters
-  parameter int unsigned RW=1,   // LFSR width
-  parameter bit [RW-1:0] RP='0,  // LFSR polinom
-  parameter bit [RW-1:0] RR='1   // LFSR reset state
-)(
-  input logic    clk,
-  input logic    rst,
-  handshake.drn  inf,
-  output integer cnt
+    // random generator parameters
+    parameter int unsigned RW = 1,  // LFSR width
+    parameter bit [RW-1:0] RP = '0,  // LFSR polinom
+    parameter bit [RW-1:0] RR = '1  // LFSR reset state
+) (
+    input logic clk,
+    input logic rst,
+    handshake.drn ifc,
+    output integer cnt
 );
 
   // LFSR
   logic [RW-1:0] rnd;
 
   // LFSR in Galois form
-  always @ (posedge clk, posedge rst)
-  if (rst) rnd <= RR;
-  else     rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);
+  always @(posedge clk, posedge rst)
+    if (rst) rnd <= RR;
+    else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);
 
   // counter
-  always @ (posedge clk, posedge rst)
-  if (rst) cnt <= 32'd0;
-  else     cnt <= cnt + {31'd0, (inf.req & inf.grt)};
+  always @(posedge clk, posedge rst)
+    if (rst) cnt <= 32'd0;
+    else cnt <= cnt + {31'd0, (ifc.req & ifc.grt)};
 
   // grant signal
-  assign inf.grt = rnd[0];
+  assign ifc.grt = rnd[0];
 
 endmodule : drain
diff --git a/test_regress/t/t_interface_generic.v b/test_regress/t/t_interface_generic.v
index 77d3aa1c6..979292722 100644
--- a/test_regress/t/t_interface_generic.v
+++ b/test_regress/t/t_interface_generic.v
@@ -4,7 +4,7 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf;
+interface ifc;
   int v;
 endinterface
 
@@ -12,7 +12,10 @@ interface inf2;
   int k;
 endinterface
 
-module GenericModule (interface a, interface b);
+module GenericModule (
+    interface a,
+    interface b
+);
   initial begin
     #1;
     if (a.v != 7) $stop;
@@ -21,9 +24,12 @@ module GenericModule (interface a, interface b);
 endmodule
 
 module t;
-  inf inf_inst();
-  inf2 inf_inst2();
-  GenericModule genericModule (inf_inst, inf_inst2);
+  ifc inf_inst ();
+  inf2 inf_inst2 ();
+  GenericModule genericModule (
+      inf_inst,
+      inf_inst2
+  );
   initial begin
     inf_inst.v = 7;
     #2;
diff --git a/test_regress/t/t_interface_generic2.v b/test_regress/t/t_interface_generic2.v
index 15eb2c048..a030885d8 100644
--- a/test_regress/t/t_interface_generic2.v
+++ b/test_regress/t/t_interface_generic2.v
@@ -4,7 +4,7 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf;
+interface ifc;
   int v;
 endinterface
 
@@ -12,7 +12,12 @@ interface inf2;
   int k;
 endinterface
 
-module GenericModule (logic[31:0] l1, interface a, logic[31:0] l2, interface b);
+module GenericModule (
+    logic [31:0] l1,
+    interface a,
+    logic [31:0] l2,
+    interface b
+);
   initial begin
     #1;
     if (l1 != 87) $stop;
@@ -23,9 +28,14 @@ module GenericModule (logic[31:0] l1, interface a, logic[31:0] l2, interface b);
 endmodule
 
 module t;
-  inf inf_inst();
-  inf2 inf_inst2();
-  GenericModule genericModule (87, inf_inst, 73, inf_inst2);
+  ifc inf_inst ();
+  inf2 inf_inst2 ();
+  GenericModule genericModule (
+      87,
+      inf_inst,
+      73,
+      inf_inst2
+  );
   initial begin
     inf_inst.v = 7;
     inf_inst2.k = 9;
diff --git a/test_regress/t/t_interface_generic_array.v b/test_regress/t/t_interface_generic_array.v
index f6380d68d..2d2ac256c 100644
--- a/test_regress/t/t_interface_generic_array.v
+++ b/test_regress/t/t_interface_generic_array.v
@@ -4,11 +4,13 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf;
+interface ifc;
   int v;
 endinterface
 
-module GenericModule (interface a);
+module GenericModule (
+    interface a
+);
   initial begin
     #1;
     if (a.v != 7) $stop;
@@ -17,7 +19,7 @@ module GenericModule (interface a);
 endmodule
 
 module t;
-  inf inf_inst[3]();
+  ifc inf_inst[3] ();
   GenericModule genericModule (inf_inst[2]);
   initial begin
     inf_inst[2].v = 7;
diff --git a/test_regress/t/t_interface_generic_array2.v b/test_regress/t/t_interface_generic_array2.v
index 654923311..94d194441 100644
--- a/test_regress/t/t_interface_generic_array2.v
+++ b/test_regress/t/t_interface_generic_array2.v
@@ -4,11 +4,13 @@
 // SPDX-FileCopyrightText: 2026 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf;
+interface ifc;
   int v;
 endinterface
 
-module GenericModule1D (interface a[4]);
+module GenericModule1D (
+    interface a[4]
+);
   initial begin
     #1;
     if (a[0].v != 'hdead) $stop;
@@ -18,7 +20,9 @@ module GenericModule1D (interface a[4]);
   end
 endmodule
 
-module GenericModule2D (interface a[2][2]);
+module GenericModule2D (
+    interface a[2][2]
+);
   initial begin
     #3;
     if (a[0][0].v != 'hdead) $stop;
@@ -28,7 +32,9 @@ module GenericModule2D (interface a[2][2]);
   end
 endmodule
 
-module GenericModuleRng (interface a[5:3]);
+module GenericModuleRng (
+    interface a[5:3]
+);
   initial begin
     #5;
     if (a[3].v != 'hdead) $stop;
@@ -38,12 +44,12 @@ module GenericModuleRng (interface a[5:3]);
 endmodule
 
 module t;
-  inf inf1d[4]();
-  inf inf2d[2][2]();
-  inf infrng[5:3]();
-  GenericModule1D mod1d(inf1d);
-  GenericModule2D mod2d(inf2d);
-  GenericModuleRng modrng(infrng);
+  ifc inf1d[4] ();
+  ifc inf2d[2][2] ();
+  ifc infrng[5:3] ();
+  GenericModule1D mod1d (inf1d);
+  GenericModule2D mod2d (inf2d);
+  GenericModuleRng modrng (infrng);
   initial begin
     inf1d[0].v = 'hdead;
     inf1d[1].v = 'hbeef;
diff --git a/test_regress/t/t_interface_generic_bad.out b/test_regress/t/t_interface_generic_bad.out
index d4be383fc..113fe5bff 100644
--- a/test_regress/t/t_interface_generic_bad.out
+++ b/test_regress/t/t_interface_generic_bad.out
@@ -1,13 +1,13 @@
-%Warning-PINMISSING: t/t_interface_generic_bad.v:26:17: Instance has missing pin: 'b'
-   26 |   GenericModule genericModule (inf_inst);
+%Warning-PINMISSING: t/t_interface_generic_bad.v:29:17: Instance has missing pin: 'b'
+   29 |   GenericModule genericModule (inf_inst);
       |                 ^~~~~~~~~~~~~
-                     t/t_interface_generic_bad.v:15:46: ... Location of port declaration
-   15 | module GenericModule (interface a, interface b);
-      |                                              ^
+                     t/t_interface_generic_bad.v:17:15: ... Location of port declaration
+   17 |     interface b
+      |               ^
                      ... For warning description see https://verilator.org/warn/PINMISSING?v=latest
                      ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.
-%Error: t/t_interface_generic_bad.v:15:46: Interface port 'b' is not connected to interface/modport pin expression
-   15 | module GenericModule (interface a, interface b);
-      |                                              ^
+%Error: t/t_interface_generic_bad.v:17:15: Interface port 'b' is not connected to interface/modport pin expression
+   17 |     interface b
+      |               ^
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to
diff --git a/test_regress/t/t_interface_generic_bad.v b/test_regress/t/t_interface_generic_bad.v
index e949e8e51..9e2ed9d5c 100644
--- a/test_regress/t/t_interface_generic_bad.v
+++ b/test_regress/t/t_interface_generic_bad.v
@@ -4,7 +4,7 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf;
+interface ifc;
   int v;
 endinterface
 
@@ -12,7 +12,10 @@ interface inf2;
   int k;
 endinterface
 
-module GenericModule (interface a, interface b);
+module GenericModule (
+    interface a,
+    interface b
+);
   initial begin
     #1;
     if (a.v != 7) $stop;
@@ -21,8 +24,8 @@ module GenericModule (interface a, interface b);
 endmodule
 
 module t;
-  inf inf_inst();
-  inf2 inf_inst2();
+  ifc inf_inst ();
+  inf2 inf_inst2 ();
   GenericModule genericModule (inf_inst);
   initial begin
     inf_inst.v = 7;
diff --git a/test_regress/t/t_interface_generic_bad2.out b/test_regress/t/t_interface_generic_bad2.out
index 7a148a4a5..9352b2ba3 100644
--- a/test_regress/t/t_interface_generic_bad2.out
+++ b/test_regress/t/t_interface_generic_bad2.out
@@ -1,24 +1,24 @@
-%Error: t/t_interface_generic_bad2.v:15:9: Can't find definition of scope/variable: 'b'
-   15 |     if (b.k != 9) $stop;
+%Error: t/t_interface_generic_bad2.v:17:9: Can't find definition of scope/variable: 'b'
+   17 |     if (b.k != 9) $stop;
       |         ^
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
-%Error: t/t_interface_generic_bad2.v:20:3: Cannot find file containing interface: 'inf'
-   20 |   inf inf_inst();
+%Error: t/t_interface_generic_bad2.v:22:3: Cannot find file containing interface: 'ifc'
+   22 |   ifc inf_inst ();
       |   ^~~
-%Error: t/t_interface_generic_bad2.v:21:32: Found definition of 'inf_inst' as a CELL but expected a variable
-   21 |   GenericModule genericModule (inf_inst);
+%Error: t/t_interface_generic_bad2.v:23:32: Found definition of 'inf_inst' as a CELL but expected a variable
+   23 |   GenericModule genericModule (inf_inst);
       |                                ^~~~~~~~
-%Error: t/t_interface_generic_bad2.v:21:32: Expected an interface but 'inf_inst' is not an interface
-   21 |   GenericModule genericModule (inf_inst);
+%Error: t/t_interface_generic_bad2.v:23:32: Expected an interface but 'inf_inst' is not an interface
+   23 |   GenericModule genericModule (inf_inst);
       |                                ^~~~~~~~
-%Error: t/t_interface_generic_bad2.v:23:5: Dotted reference to instance that refers to missing module/interface: 'inf'
-   23 |     inf_inst.v = 7;
+%Error: t/t_interface_generic_bad2.v:25:5: Dotted reference to instance that refers to missing module/interface: 'ifc'
+   25 |     inf_inst.v = 7;
       |     ^~~~~~~~
-%Error: t/t_interface_generic_bad2.v:23:14: Can't find definition of 'v' in dotted variable/method: 'inf_inst.v'
-   23 |     inf_inst.v = 7;
+%Error: t/t_interface_generic_bad2.v:25:14: Can't find definition of 'v' in dotted variable/method: 'inf_inst.v'
+   25 |     inf_inst.v = 7;
       |              ^
-%Error: t/t_interface_generic_bad2.v:24:5: Can't find definition of scope/variable: 'inf_inst2'
+%Error: t/t_interface_generic_bad2.v:26:5: Can't find definition of scope/variable: 'inf_inst2'
                                          : ... Suggested alternative: 'inf_inst'
-   24 |     inf_inst2.k = 9;
+   26 |     inf_inst2.k = 9;
       |     ^~~~~~~~~
 %Error: Exiting due to
diff --git a/test_regress/t/t_interface_generic_bad2.v b/test_regress/t/t_interface_generic_bad2.v
index 51d5d339c..377f627b2 100644
--- a/test_regress/t/t_interface_generic_bad2.v
+++ b/test_regress/t/t_interface_generic_bad2.v
@@ -4,11 +4,13 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-class inf;
+class ifc;
   int v;
 endclass
 
-module GenericModule (interface a);
+module GenericModule (
+    interface a
+);
   initial begin
     #1;
     if (a.v != 7) $stop;
@@ -17,7 +19,7 @@ module GenericModule (interface a);
 endmodule
 
 module t;
-  inf inf_inst();
+  ifc inf_inst ();
   GenericModule genericModule (inf_inst);
   initial begin
     inf_inst.v = 7;
diff --git a/test_regress/t/t_interface_generic_bad3.out b/test_regress/t/t_interface_generic_bad3.out
index dd5629397..027325553 100644
--- a/test_regress/t/t_interface_generic_bad3.out
+++ b/test_regress/t/t_interface_generic_bad3.out
@@ -1,12 +1,12 @@
-%Error: t/t_interface_generic_bad3.v:15:9: Can't find definition of scope/variable: 'b'
-   15 |     if (b.k != 9) $stop;
+%Error: t/t_interface_generic_bad3.v:17:9: Can't find definition of scope/variable: 'b'
+   17 |     if (b.k != 9) $stop;
       |         ^
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
-%Error-PINNOTFOUND: t/t_interface_generic_bad3.v:21:42: Pin not found: '__pinNumber2'
-   21 |   GenericModule genericModule (inf_inst, inf_inst);
-      |                                          ^~~~~~~~
-                                                      : ... Location of instance's module declaration
-   11 | module GenericModule (interface a);
+%Error-PINNOTFOUND: t/t_interface_generic_bad3.v:25:7: Pin not found: '__pinNumber2'
+   25 |       inf_inst
+      |       ^~~~~~~~
+                                                     : ... Location of instance's module declaration
+   11 | module GenericModule (
       |        ^~~~~~~~~~~~~
                     ... For error description see https://verilator.org/warn/PINNOTFOUND?v=latest
 %Error: Exiting due to
diff --git a/test_regress/t/t_interface_generic_bad3.v b/test_regress/t/t_interface_generic_bad3.v
index bc5c445b9..579399bba 100644
--- a/test_regress/t/t_interface_generic_bad3.v
+++ b/test_regress/t/t_interface_generic_bad3.v
@@ -4,11 +4,13 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf;
+interface ifc;
   int v;
 endinterface
 
-module GenericModule (interface a);
+module GenericModule (
+    interface a
+);
   initial begin
     #1;
     if (a.v != 7) $stop;
@@ -17,8 +19,11 @@ module GenericModule (interface a);
 endmodule
 
 module t;
-  inf inf_inst();
-  GenericModule genericModule (inf_inst, inf_inst);
+  ifc inf_inst ();
+  GenericModule genericModule (
+      inf_inst,
+      inf_inst
+  );
   initial begin
     inf_inst.v = 7;
     $write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_interface_generic_bad4.out b/test_regress/t/t_interface_generic_bad4.out
index 11266ed5f..5fac04299 100644
--- a/test_regress/t/t_interface_generic_bad4.out
+++ b/test_regress/t/t_interface_generic_bad4.out
@@ -1,5 +1,5 @@
-%Error: t/t_interface_generic_bad4.v:26:32: Generic interfaces can only connect to an interface and 'inf_inst' is of type 'int'
-   26 |   GenericModule genericModule (inf_inst, inf_inst2);
-      |                                ^~~~~~~~
+%Error: t/t_interface_generic_bad4.v:30:7: Generic interfaces can only connect to an interface and 'inf_inst' is of type 'int'
+   30 |       inf_inst,
+      |       ^~~~~~~~
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to
diff --git a/test_regress/t/t_interface_generic_bad4.v b/test_regress/t/t_interface_generic_bad4.v
index f3dcbe934..c0c9c5dbe 100644
--- a/test_regress/t/t_interface_generic_bad4.v
+++ b/test_regress/t/t_interface_generic_bad4.v
@@ -4,7 +4,7 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf;
+interface ifc;
   int v;
 endinterface
 
@@ -12,7 +12,10 @@ interface inf2;
   int k;
 endinterface
 
-module GenericModule (interface a, interface b);
+module GenericModule (
+    interface a,
+    interface b
+);
   initial begin
     #1;
     if (a.v != 7) $stop;
@@ -22,8 +25,11 @@ endmodule
 
 module t;
   int inf_inst;
-  inf2 inf_inst2();
-  GenericModule genericModule (inf_inst, inf_inst2);
+  inf2 inf_inst2 ();
+  GenericModule genericModule (
+      inf_inst,
+      inf_inst2
+  );
   initial begin
     inf_inst.v = 7;
     inf_inst2.k = 9;
diff --git a/test_regress/t/t_interface_generic_function.v b/test_regress/t/t_interface_generic_function.v
index 2d8dbad6b..b187f9bc4 100644
--- a/test_regress/t/t_interface_generic_function.v
+++ b/test_regress/t/t_interface_generic_function.v
@@ -4,7 +4,7 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf;
+interface ifc;
   int v;
   function int get();
     return v;
@@ -15,7 +15,9 @@ interface inf2;
   int k;
 endinterface
 
-module GenericModule (interface a);
+module GenericModule (
+    interface a
+);
   initial begin
     #1;
     if (a.get() != 4) $stop;
@@ -23,7 +25,7 @@ module GenericModule (interface a);
 endmodule
 
 module t;
-  inf inf_inst();
+  ifc inf_inst ();
   GenericModule genericModule (inf_inst);
   initial begin
     inf_inst.v = 4;
diff --git a/test_regress/t/t_interface_generic_function_bad.out b/test_regress/t/t_interface_generic_function_bad.out
index b4f1e6ee3..f03262081 100644
--- a/test_regress/t/t_interface_generic_function_bad.out
+++ b/test_regress/t/t_interface_generic_function_bad.out
@@ -1,6 +1,6 @@
-%Error: t/t_interface_generic_function_bad.v:14:11: Can't find definition of 'get' in dotted task/function: 'a.get'
+%Error: t/t_interface_generic_function_bad.v:16:11: Can't find definition of 'get' in dotted task/function: 'a.get'
                                                   : ... note: In instance 't.genericModule'
-   14 |     if (a.get() != 4) $stop;
+   16 |     if (a.get() != 4) $stop;
       |           ^~~
         ... Known scopes under 'get': <no instances found>
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
diff --git a/test_regress/t/t_interface_generic_function_bad.v b/test_regress/t/t_interface_generic_function_bad.v
index 48592e5f7..07290208a 100644
--- a/test_regress/t/t_interface_generic_function_bad.v
+++ b/test_regress/t/t_interface_generic_function_bad.v
@@ -4,11 +4,13 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf;
+interface ifc;
   int v;
 endinterface
 
-module GenericModule (interface a);
+module GenericModule (
+    interface a
+);
   initial begin
     #1;
     if (a.get() != 4) $stop;
@@ -16,7 +18,7 @@ module GenericModule (interface a);
 endmodule
 
 module t;
-  inf inf_inst();
+  ifc inf_inst ();
   GenericModule genericModule (inf_inst);
   initial begin
     inf_inst.v = 4;
diff --git a/test_regress/t/t_interface_generic_iface_forward.v b/test_regress/t/t_interface_generic_iface_forward.v
index 2608a3ac9..6a17ced4f 100644
--- a/test_regress/t/t_interface_generic_iface_forward.v
+++ b/test_regress/t/t_interface_generic_iface_forward.v
@@ -9,11 +9,15 @@
 `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 // verilog_format: on
 
-interface inf #(parameter int PARAM = 1);
+interface ifc #(
+    parameter int PARAM = 1
+);
   logic [PARAM-1:0] v;
 endinterface
 
-module leaf (interface d);
+module leaf (
+    interface d
+);
   initial begin
     #1;
     `checkd(d.v, 13);
@@ -21,17 +25,21 @@ module leaf (interface d);
   end
 endmodule
 
-module mid2 (interface c);
-  leaf leaf_i(.d(c));
+module mid2 (
+    interface c
+);
+  leaf leaf_i (.d(c));
 endmodule
 
-module mid1 (interface b);
-  mid2 mid2_i(.c(b));
+module mid1 (
+    interface b
+);
+  mid2 mid2_i (.c(b));
 endmodule
 
 module t;
-  inf #(.PARAM(5)) a();
-  mid1 mid1_i(.b(a));
+  ifc #(.PARAM(5)) a ();
+  mid1 mid1_i (.b(a));
   initial begin
     a.v = 13;
     $write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_interface_generic_iface_forward_concrete.v b/test_regress/t/t_interface_generic_iface_forward_concrete.v
index 931251ad0..66615e021 100644
--- a/test_regress/t/t_interface_generic_iface_forward_concrete.v
+++ b/test_regress/t/t_interface_generic_iface_forward_concrete.v
@@ -9,11 +9,15 @@
 `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 // verilog_format: on
 
-interface inf #(parameter int PARAM = 1);
+interface ifc #(
+    parameter int PARAM = 1
+);
   logic [PARAM-1:0] v;
 endinterface
 
-module leaf (inf d);
+module leaf (
+    ifc d
+);
   initial begin
     #1;
     `checkd(d.v, 13);
@@ -21,17 +25,21 @@ module leaf (inf d);
   end
 endmodule
 
-module mid2 (interface c);
-  leaf leaf_i(.d(c));
+module mid2 (
+    interface c
+);
+  leaf leaf_i (.d(c));
 endmodule
 
-module mid1 (interface b);
-  mid2 mid2_i(.c(b));
+module mid1 (
+    interface b
+);
+  mid2 mid2_i (.c(b));
 endmodule
 
 module t;
-  inf #(.PARAM(5)) a();
-  mid1 mid1_i(.b(a));
+  ifc #(.PARAM(5)) a ();
+  mid1 mid1_i (.b(a));
   initial begin
     a.v = 13;
     $write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_interface_generic_iface_forward_param.v b/test_regress/t/t_interface_generic_iface_forward_param.v
index b0b249e68..340f64f6d 100644
--- a/test_regress/t/t_interface_generic_iface_forward_param.v
+++ b/test_regress/t/t_interface_generic_iface_forward_param.v
@@ -9,11 +9,15 @@
 `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 // verilog_format: on
 
-interface inf #(parameter int PARAM = 1);
+interface ifc #(
+    parameter int PARAM = 1
+);
   logic [PARAM-1:0] v;
 endinterface
 
-module leaf (inf c);
+module leaf (
+    ifc c
+);
   initial begin
     #1;
     `checkd(c.v, 13)
@@ -21,13 +25,17 @@ module leaf (inf c);
   end
 endmodule
 
-module mid #(int PARAM = 1)  (interface b);
-  leaf leaf_i(.c(b));
-  initial `checkd(PARAM,7)
+module mid #(
+    int PARAM = 1
+) (
+    interface b
+);
+  leaf leaf_i (.c(b));
+  initial `checkd(PARAM, 7)
 endmodule
 
 module t;
-  inf #(.PARAM(5)) a();
+  ifc #(.PARAM(5)) a ();
   mid #(.PARAM(7)) mid_i (.b(a));
   initial begin
     a.v = 13;
diff --git a/test_regress/t/t_interface_generic_iface_param.v b/test_regress/t/t_interface_generic_iface_param.v
index 9cbe4370a..5755ebda3 100644
--- a/test_regress/t/t_interface_generic_iface_param.v
+++ b/test_regress/t/t_interface_generic_iface_param.v
@@ -4,11 +4,15 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf #(PARAM);
-  logic[PARAM-1:0] v;
+interface ifc #(
+    PARAM
+);
+  logic [PARAM-1:0] v;
 endinterface
 
-module GenericModule (interface a);
+module GenericModule (
+    interface a
+);
   initial begin
     #1;
     if (a.v != 7) $stop;
@@ -17,7 +21,7 @@ module GenericModule (interface a);
 endmodule
 
 module t;
-  inf  #(.PARAM(13)) inf_inst();
+  ifc #(.PARAM(13)) inf_inst ();
   GenericModule genericModule (inf_inst);
   initial begin
     inf_inst.v = 7;
diff --git a/test_regress/t/t_interface_generic_iface_param_cell_ref.v b/test_regress/t/t_interface_generic_iface_param_cell_ref.v
index 26c4fb4bb..3007d4617 100644
--- a/test_regress/t/t_interface_generic_iface_param_cell_ref.v
+++ b/test_regress/t/t_interface_generic_iface_param_cell_ref.v
@@ -9,22 +9,30 @@
 `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 // verilog_format: on
 
-interface inf #(parameter int PARAM = 1);
+interface ifc #(
+    parameter int PARAM = 1
+);
   logic [PARAM-1:0] v;
-  modport mp (input v);
+  modport mp(input v);
 endinterface
 
-module Leaf #(parameter int PARAM = 1) (inf.mp leaf_a);
+module Leaf #(
+    parameter int PARAM = 1
+) (
+    ifc.mp leaf_a
+);
   initial begin
     #1;
     `checkd(leaf_a.PARAM, PARAM);
   end
 endmodule
 
-module GenericModule (interface.mp a);
+module GenericModule (
+    interface.mp a
+);
   localparam LOC_PARAM = a.PARAM;
   // A generic interface's parameter, parameterizing a sibling interface cell
-  inf #(.PARAM(LOC_PARAM)) nested_inst();
+  ifc #(.PARAM(LOC_PARAM)) nested_inst ();
   Leaf #(.PARAM(LOC_PARAM)) leaf (nested_inst);
   initial begin
     #1;
@@ -35,7 +43,7 @@ module GenericModule (interface.mp a);
 endmodule
 
 module t;
-  inf  #(.PARAM(13)) inf_inst();
+  ifc #(.PARAM(13)) inf_inst ();
   GenericModule genericModule (inf_inst);
   initial begin
     inf_inst.v = 7;
diff --git a/test_regress/t/t_interface_generic_iface_param_dotchain.v b/test_regress/t/t_interface_generic_iface_param_dotchain.v
index d1e3baf67..d7ff61ffe 100644
--- a/test_regress/t/t_interface_generic_iface_param_dotchain.v
+++ b/test_regress/t/t_interface_generic_iface_param_dotchain.v
@@ -14,15 +14,19 @@ interface leaf_if;
   logic dummy;
 endinterface
 
-interface inf #(parameter int PARAM = 1);
+interface ifc #(
+    parameter int PARAM = 1
+);
   logic [PARAM-1:0] v;
   // Makes 'a.nested.LEAF_PARAM' a chained Dot, whose lhsp is itself a Dot
-  leaf_if nested();
+  leaf_if nested ();
   parameter int ARR[2] = '{PARAM, PARAM + 1};
-  modport mp (input v);
+  modport mp(input v);
 endinterface
 
-module GenericModule (interface.mp a);
+module GenericModule (
+    interface.mp a
+);
   localparam int LOC_CHAIN = a.nested.LEAF_PARAM;
   // Makes the Dot's rhsp an indexed select, not a plain identifier
   localparam int LOC_ARR = a.ARR[0];
@@ -35,7 +39,7 @@ module GenericModule (interface.mp a);
 endmodule
 
 module t;
-  inf #(.PARAM(13)) inf_inst();
+  ifc #(.PARAM(13)) inf_inst ();
   GenericModule genericModule (inf_inst);
   initial begin
     inf_inst.v = 7;
diff --git a/test_regress/t/t_interface_generic_iface_param_genblock.v b/test_regress/t/t_interface_generic_iface_param_genblock.v
index 4379b7e6f..c9ca05239 100644
--- a/test_regress/t/t_interface_generic_iface_param_genblock.v
+++ b/test_regress/t/t_interface_generic_iface_param_genblock.v
@@ -9,10 +9,12 @@
 `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 // verilog_format: on
 
-interface inf #(parameter int PARAM = 1);
+interface ifc #(
+    parameter int PARAM = 1
+);
   logic [PARAM-1:0] v;
   // A non-Var/non-GenBlock item the member gather must skip past
-  modport mp (input v);
+  modport mp(input v);
   if (1) begin : blk_decoy
     // Same name as the real parameter below, but not a parameter
     logic PARAM_IF;
@@ -25,7 +27,9 @@ interface inf #(parameter int PARAM = 1);
   end
 endinterface
 
-module GenericModule (interface.mp a);
+module GenericModule (
+    interface.mp a
+);
   // Two references to the same member, so the second reuses the gathered members
   localparam int LOC_PARAM1 = a.PARAM;
   localparam int LOC_PARAM2 = a.PARAM;
@@ -43,7 +47,7 @@ module GenericModule (interface.mp a);
 endmodule
 
 module t;
-  inf #(.PARAM(13)) inf_inst();
+  ifc #(.PARAM(13)) inf_inst ();
   GenericModule genericModule (inf_inst);
   initial begin
     inf_inst.v = 7;
diff --git a/test_regress/t/t_interface_generic_iface_param_modgenblock.v b/test_regress/t/t_interface_generic_iface_param_modgenblock.v
index 09815472e..d83a18b89 100644
--- a/test_regress/t/t_interface_generic_iface_param_modgenblock.v
+++ b/test_regress/t/t_interface_generic_iface_param_modgenblock.v
@@ -9,18 +9,22 @@
 `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 // verilog_format: on
 
-interface inf #(parameter int PARAM = 1);
+interface ifc #(
+    parameter int PARAM = 1
+);
   logic [PARAM-1:0] v;
-  modport mp (input v);
+  modport mp(input v);
 endinterface
 
-module GenericModule (interface.mp a);
+module GenericModule (
+    interface.mp a
+);
   // Dotted localparam inside a generate block, feeding a sibling cell in the same block.
   // The interface-ref gather must recurse in here yet still find port 'a' at module level.
   // Generate blocks on the interface side are covered by t_interface_generic_iface_param_genblock.
   if (1) begin : blk
     localparam int LOC_PARAM = a.PARAM;
-    inf #(.PARAM(LOC_PARAM)) inner();
+    ifc #(.PARAM(LOC_PARAM)) inner ();
   end
   initial begin
     #1;
@@ -31,7 +35,7 @@ module GenericModule (interface.mp a);
 endmodule
 
 module t;
-  inf #(.PARAM(13)) inf_inst();
+  ifc #(.PARAM(13)) inf_inst ();
   GenericModule genericModule (inf_inst);
   initial begin
     inf_inst.v = 7;
diff --git a/test_regress/t/t_interface_generic_iface_param_ref.v b/test_regress/t/t_interface_generic_iface_param_ref.v
index dfd3da681..9b784faa2 100644
--- a/test_regress/t/t_interface_generic_iface_param_ref.v
+++ b/test_regress/t/t_interface_generic_iface_param_ref.v
@@ -9,18 +9,20 @@
 `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 // verilog_format: on
 
-interface inf #(int PARAM = 0);
-  logic[PARAM-1:0] v;
+interface ifc #(
+    int PARAM = 0
+);
+  logic [PARAM-1:0] v;
 
-  modport port_in (
-    input v
-  );
-  modport port_out (
-    output v
-  );
+  modport port_in(input v);
+  modport port_out(output v);
 endinterface
 
-module GenericModule #(PARAM=0) (interface.port_in a);
+module GenericModule #(
+    PARAM = 0
+) (
+    interface.port_in a
+);
   localparam int LOC_PARAM = a.PARAM;
   initial begin
     #1;
@@ -31,7 +33,7 @@ module GenericModule #(PARAM=0) (interface.port_in a);
 endmodule
 
 module t;
-  inf  #(.PARAM(13)) inf_inst();
+  ifc #(.PARAM(13)) inf_inst ();
   GenericModule genericModule (inf_inst);
   initial begin
     inf_inst.v = 7;
diff --git a/test_regress/t/t_interface_generic_iface_param_ref_bad.out b/test_regress/t/t_interface_generic_iface_param_ref_bad.out
index 27e3b9ba1..d34e57dcd 100644
--- a/test_regress/t/t_interface_generic_iface_param_ref_bad.out
+++ b/test_regress/t/t_interface_generic_iface_param_ref_bad.out
@@ -1,6 +1,6 @@
-%Error: t/t_interface_generic_iface_param_ref_bad.v:19:32: Can't find definition of 'NONEXISTENT_PARAM' in dotted variable/method: 'a.NONEXISTENT_PARAM'
+%Error: t/t_interface_generic_iface_param_ref_bad.v:23:32: Can't find definition of 'NONEXISTENT_PARAM' in dotted variable/method: 'a.NONEXISTENT_PARAM'
                                                          : ... note: In instance 't.genericModule'
-   19 |   localparam int LOC_PARAM = a.NONEXISTENT_PARAM;
+   23 |   localparam int LOC_PARAM = a.NONEXISTENT_PARAM;
       |                                ^~~~~~~~~~~~~~~~~
         ... Known scopes under 'a': <no instances found>
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
diff --git a/test_regress/t/t_interface_generic_iface_param_ref_bad.v b/test_regress/t/t_interface_generic_iface_param_ref_bad.v
index 5c75d6a16..96581160d 100644
--- a/test_regress/t/t_interface_generic_iface_param_ref_bad.v
+++ b/test_regress/t/t_interface_generic_iface_param_ref_bad.v
@@ -9,12 +9,16 @@
 `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 // verilog_format: on
 
-interface inf #(parameter int PARAM = 1);
+interface ifc #(
+    parameter int PARAM = 1
+);
   logic [PARAM-1:0] v;
-  modport mp (input v);
+  modport mp(input v);
 endinterface
 
-module GenericModule (interface.mp a);
+module GenericModule (
+    interface.mp a
+);
   // A member that does not exist on the (now concrete) interface
   localparam int LOC_PARAM = a.NONEXISTENT_PARAM;
   initial begin
@@ -24,7 +28,7 @@ module GenericModule (interface.mp a);
 endmodule
 
 module t;
-  inf #(.PARAM(13)) inf_inst();
+  ifc #(.PARAM(13)) inf_inst ();
   GenericModule genericModule (inf_inst);
   initial begin
     inf_inst.v = 7;
diff --git a/test_regress/t/t_interface_generic_mod_param.v b/test_regress/t/t_interface_generic_mod_param.v
index 119a394d6..35b127ab6 100644
--- a/test_regress/t/t_interface_generic_mod_param.v
+++ b/test_regress/t/t_interface_generic_mod_param.v
@@ -4,11 +4,16 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf;
+interface ifc;
   int v;
 endinterface
 
-module GenericModule#(type T, type Y = int) (interface a);
+module GenericModule #(
+    type T,
+    type Y = int
+) (
+    interface a
+);
   initial begin
     #1;
     if (a.v != 7) $stop;
@@ -16,7 +21,7 @@ module GenericModule#(type T, type Y = int) (interface a);
 endmodule
 
 module t;
-  inf inf_inst();
+  ifc inf_inst ();
   GenericModule #(string) genericModule (inf_inst);
   initial begin
     inf_inst.v = 7;
diff --git a/test_regress/t/t_interface_generic_modport.v b/test_regress/t/t_interface_generic_modport.v
index 407574f7e..89cea1125 100644
--- a/test_regress/t/t_interface_generic_modport.v
+++ b/test_regress/t/t_interface_generic_modport.v
@@ -4,14 +4,14 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf;
+interface ifc;
   int v;
-  modport mp (
-    input v
-  );
+  modport mp(input v);
 endinterface
 
-module GenericModule (interface.mp a);
+module GenericModule (
+    interface.mp a
+);
   initial begin
     #1;
     if (a.v != 7) $stop;
@@ -19,7 +19,7 @@ module GenericModule (interface.mp a);
 endmodule
 
 module t;
-  inf inf_inst();
+  ifc inf_inst ();
   GenericModule genericModule (inf_inst);
   initial begin
     inf_inst.v = 7;
diff --git a/test_regress/t/t_interface_generic_modport2.v b/test_regress/t/t_interface_generic_modport2.v
index 988520f57..e78982cc8 100644
--- a/test_regress/t/t_interface_generic_modport2.v
+++ b/test_regress/t/t_interface_generic_modport2.v
@@ -4,21 +4,21 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf;
+interface ifc;
   int v;
-  modport mp (
-    output v
-  );
+  modport mp(output v);
 endinterface
 
-module GenericModule (interface.mp a);
+module GenericModule (
+    interface.mp a
+);
   initial begin
     a.v = 7;
   end
 endmodule
 
 module t;
-  inf inf_inst();
+  ifc inf_inst ();
   GenericModule genericModule (inf_inst);
   initial begin
     #1;
diff --git a/test_regress/t/t_interface_generic_modport_bad.out b/test_regress/t/t_interface_generic_modport_bad.out
index c6b0a02ea..099bd5338 100644
--- a/test_regress/t/t_interface_generic_modport_bad.out
+++ b/test_regress/t/t_interface_generic_modport_bad.out
@@ -1,5 +1,5 @@
-%Error: t/t_interface_generic_modport_bad.v:11:33: Modport not found under interface 'inf': 'mp'
-   11 | module GenericModule (interface.mp a);
-      |                                 ^~
+%Error: t/t_interface_generic_modport_bad.v:12:15: Modport not found under interface 'ifc': 'mp'
+   12 |     interface.mp a
+      |               ^~
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to
diff --git a/test_regress/t/t_interface_generic_modport_bad.v b/test_regress/t/t_interface_generic_modport_bad.v
index d6dff8c81..e0e20f768 100644
--- a/test_regress/t/t_interface_generic_modport_bad.v
+++ b/test_regress/t/t_interface_generic_modport_bad.v
@@ -4,11 +4,13 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf;
+interface ifc;
   int v;
 endinterface
 
-module GenericModule (interface.mp a);
+module GenericModule (
+    interface.mp a
+);
   initial begin
     #1;
     if (a.v != 7) $stop;
@@ -16,7 +18,7 @@ module GenericModule (interface.mp a);
 endmodule
 
 module t;
-  inf inf_inst();
+  ifc inf_inst ();
   GenericModule genericModule (inf_inst);
   initial begin
     inf_inst.v = 7;
diff --git a/test_regress/t/t_interface_generic_modport_bad2.v b/test_regress/t/t_interface_generic_modport_bad2.v
index 1a05b15e6..6bc0b9c11 100644
--- a/test_regress/t/t_interface_generic_modport_bad2.v
+++ b/test_regress/t/t_interface_generic_modport_bad2.v
@@ -4,14 +4,14 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf;
+interface ifc;
   int v;
-  modport mp (
-    input v
-  );
+  modport mp(input v);
 endinterface
 
-module GenericModule (interface.mp a);
+module GenericModule (
+    interface.mp a
+);
   initial begin
     #1;
     a.v = 10;
@@ -19,7 +19,7 @@ module GenericModule (interface.mp a);
 endmodule
 
 module t;
-  inf inf_inst();
+  ifc inf_inst ();
   GenericModule genericModule (inf_inst);
   initial begin
     inf_inst.v = 7;
diff --git a/test_regress/t/t_interface_generic_modport_bad3.v b/test_regress/t/t_interface_generic_modport_bad3.v
index f560e9b86..b784a8f68 100644
--- a/test_regress/t/t_interface_generic_modport_bad3.v
+++ b/test_regress/t/t_interface_generic_modport_bad3.v
@@ -4,15 +4,15 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf;
+interface ifc;
   int v;
   int o;
-  modport mp (
-    input o
-  );
+  modport mp(input o);
 endinterface
 
-module GenericModule (interface.mp a);
+module GenericModule (
+    interface.mp a
+);
   initial begin
     #1;
     if (a.v != 7) $stop;
@@ -20,7 +20,7 @@ module GenericModule (interface.mp a);
 endmodule
 
 module t;
-  inf inf_inst();
+  ifc inf_inst ();
   GenericModule genericModule (inf_inst);
   initial begin
     inf_inst.v = 7;
diff --git a/test_regress/t/t_interface_generic_modport_function.v b/test_regress/t/t_interface_generic_modport_function.v
index d1100642f..2faccaa5f 100644
--- a/test_regress/t/t_interface_generic_modport_function.v
+++ b/test_regress/t/t_interface_generic_modport_function.v
@@ -4,21 +4,21 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf;
+interface ifc;
   int v;
   function int get();
     return v;
   endfunction
-  modport mp(
-    import get
-  );
+  modport mp(import get);
 endinterface
 
 interface inf2;
   int k;
 endinterface
 
-module GenericModule (interface.mp a);
+module GenericModule (
+    interface.mp a
+);
   initial begin
     #1;
     if (a.get() != 4) $stop;
@@ -26,7 +26,7 @@ module GenericModule (interface.mp a);
 endmodule
 
 module t;
-  inf inf_inst();
+  ifc inf_inst ();
   GenericModule genericModule (inf_inst);
   initial begin
     inf_inst.v = 4;
diff --git a/test_regress/t/t_interface_generic_modport_function2.v b/test_regress/t/t_interface_generic_modport_function2.v
index e56818082..fe7108d4c 100644
--- a/test_regress/t/t_interface_generic_modport_function2.v
+++ b/test_regress/t/t_interface_generic_modport_function2.v
@@ -4,32 +4,32 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf;
+interface ifc;
   int v;
   function int get();
     return v;
   endfunction
-  modport mp(
-    output v
-  );
+  modport mp(output v);
 endinterface
 
 interface inf2;
   int k;
 endinterface
 
-module GenericModule (interface.mp a);
+module GenericModule (
+    interface.mp a
+);
   initial begin
     a.v = 5;
   end
 endmodule
 
 module t;
-  inf inf_inst();
+  ifc inf_inst ();
   GenericModule genericModule (inf_inst);
   initial begin
     #1;
-    if(inf_inst.get() != 5) $stop;
+    if (inf_inst.get() != 5) $stop;
     $write("*-* All Finished *-*\n");
     $finish;
   end
diff --git a/test_regress/t/t_interface_generic_modport_function_bad.v b/test_regress/t/t_interface_generic_modport_function_bad.v
index 5d38bf185..9b8600137 100644
--- a/test_regress/t/t_interface_generic_modport_function_bad.v
+++ b/test_regress/t/t_interface_generic_modport_function_bad.v
@@ -4,21 +4,21 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf;
+interface ifc;
   int v;
   function int get();
     return v;
   endfunction
-  modport mp(
-    input v
-  );
+  modport mp(input v);
 endinterface
 
 interface inf2;
   int k;
 endinterface
 
-module GenericModule (interface.mp a);
+module GenericModule (
+    interface.mp a
+);
   initial begin
     #1;
     if (a.get() != 4) $stop;
@@ -26,7 +26,7 @@ module GenericModule (interface.mp a);
 endmodule
 
 module t;
-  inf inf_inst();
+  ifc inf_inst ();
   GenericModule genericModule (inf_inst);
   initial begin
     inf_inst.v = 4;
diff --git a/test_regress/t/t_interface_generic_modport_param.v b/test_regress/t/t_interface_generic_modport_param.v
index e43292ec1..c7175f201 100644
--- a/test_regress/t/t_interface_generic_modport_param.v
+++ b/test_regress/t/t_interface_generic_modport_param.v
@@ -4,16 +4,16 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf;
+interface ifc;
   localparam LPARAM = 12;
 
   int v;
-  modport mp (
-    input v
-  );
+  modport mp(input v);
 endinterface
 
-module GenericModule (interface.mp a);
+module GenericModule (
+    interface.mp a
+);
   initial begin
     #1;
     if (a.LPARAM != 12) $stop;
@@ -22,7 +22,7 @@ module GenericModule (interface.mp a);
 endmodule
 
 module t;
-  inf inf_inst();
+  ifc inf_inst ();
   GenericModule genericModule (inf_inst);
   initial begin
     inf_inst.v = 7;
diff --git a/test_regress/t/t_interface_generic_modport_task.v b/test_regress/t/t_interface_generic_modport_task.v
index 132ccbc2f..e482f7035 100644
--- a/test_regress/t/t_interface_generic_modport_task.v
+++ b/test_regress/t/t_interface_generic_modport_task.v
@@ -4,25 +4,24 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf;
+interface ifc;
   int v;
   task setup();
     v = 3;
   endtask
-  modport mp(
-    input v,
-    import setup
-  );
+  modport mp(input v, import setup);
 endinterface
 
-module GenericModule (interface.mp a);
+module GenericModule (
+    interface.mp a
+);
   initial begin
     a.setup();
   end
 endmodule
 
 module t;
-  inf inf_inst();
+  ifc inf_inst ();
   GenericModule genericModule (inf_inst);
   initial begin
     #1;
diff --git a/test_regress/t/t_interface_generic_modport_task2.v b/test_regress/t/t_interface_generic_modport_task2.v
index 3e6da039b..0af87fdb5 100644
--- a/test_regress/t/t_interface_generic_modport_task2.v
+++ b/test_regress/t/t_interface_generic_modport_task2.v
@@ -4,17 +4,17 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf;
+interface ifc;
   int v;
   task setup();
     v = 3;
   endtask
-  modport mp(
-    input v
-  );
+  modport mp(input v);
 endinterface
 
-module GenericModule (interface.mp a);
+module GenericModule (
+    interface.mp a
+);
   initial begin
     #1;
     if (a.v != 3) $stop;
@@ -22,7 +22,7 @@ module GenericModule (interface.mp a);
 endmodule
 
 module t;
-  inf inf_inst();
+  ifc inf_inst ();
   GenericModule genericModule (inf_inst);
   initial begin
     inf_inst.setup();
diff --git a/test_regress/t/t_interface_generic_modport_task_bad.v b/test_regress/t/t_interface_generic_modport_task_bad.v
index aac1d53c5..2f83137b7 100644
--- a/test_regress/t/t_interface_generic_modport_task_bad.v
+++ b/test_regress/t/t_interface_generic_modport_task_bad.v
@@ -4,28 +4,28 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf;
+interface ifc;
   int v;
   task setup();
     v = 3;
   endtask
-  modport mp(
-    input v
-  );
+  modport mp(input v);
 endinterface
 
 interface inf2;
   int k;
 endinterface
 
-module GenericModule (interface.mp a);
+module GenericModule (
+    interface.mp a
+);
   initial begin
     a.setup();
   end
 endmodule
 
 module t;
-  inf inf_inst();
+  ifc inf_inst ();
   GenericModule genericModule (inf_inst);
   initial begin
     #1;
diff --git a/test_regress/t/t_interface_generic_normal.v b/test_regress/t/t_interface_generic_normal.v
index 1678e2074..25492dfa8 100644
--- a/test_regress/t/t_interface_generic_normal.v
+++ b/test_regress/t/t_interface_generic_normal.v
@@ -4,11 +4,15 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf;
+interface ifc;
   int v;
 endinterface
 
-module GenericModule (interface a, inf b, interface c);
+module GenericModule (
+    interface a,
+    ifc b,
+    interface c
+);
   initial begin
     #1;
     if (a.v != 7) $stop;
@@ -18,8 +22,12 @@ module GenericModule (interface a, inf b, interface c);
 endmodule
 
 module t;
-  inf inf_inst[3]();
-  GenericModule genericModule (inf_inst[0], inf_inst[1], inf_inst[2]);
+  ifc inf_inst[3] ();
+  GenericModule genericModule (
+      inf_inst[0],
+      inf_inst[1],
+      inf_inst[2]
+  );
   initial begin
     inf_inst[0].v = 7;
     inf_inst[1].v = 8;
diff --git a/test_regress/t/t_interface_generic_positional.v b/test_regress/t/t_interface_generic_positional.v
index a2726cfb0..c1b0a12b0 100644
--- a/test_regress/t/t_interface_generic_positional.v
+++ b/test_regress/t/t_interface_generic_positional.v
@@ -4,11 +4,14 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf;
+interface ifc;
   int v;
 endinterface
 
-module GenericModule (interface a, interface b);
+module GenericModule (
+    interface a,
+    interface b
+);
   initial begin
     #1;
     if (a.v != 7) $stop;
@@ -16,8 +19,11 @@ module GenericModule (interface a, interface b);
 endmodule
 
 module t;
-  inf inf_inst[3]();
-  GenericModule genericModule (.a(inf_inst[1]), .b(inf_inst[2]));
+  ifc inf_inst[3] ();
+  GenericModule genericModule (
+      .a(inf_inst[1]),
+      .b(inf_inst[2])
+  );
   initial begin
     inf_inst[1].v = 7;
     $write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_interface_generic_submod_param.v b/test_regress/t/t_interface_generic_submod_param.v
index f9614bb10..c4d661f98 100644
--- a/test_regress/t/t_interface_generic_submod_param.v
+++ b/test_regress/t/t_interface_generic_submod_param.v
@@ -4,7 +4,9 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-module sub #(parameter P);
+module sub #(
+    parameter P
+);
 endmodule
 
 package pkg;
@@ -15,21 +17,23 @@ class B;
   int x;
 endclass
 
-module Gm (interface a);
+module Gm (
+    interface a
+);
   B b;
-  sub#(.P(pkg::A + $bits(b.x))) s();
+  sub #(.P(pkg::A + $bits(b.x))) s ();
   initial begin
     a.v = s.P;
   end
 endmodule
 
-interface inf;
+interface ifc;
   int v;
 endinterface
 
 module t;
-  inf i();
-  Gm g(.a(i));
+  ifc i ();
+  Gm g (.a(i));
   initial begin
     #1;
     if (i.v != 35) $stop;
diff --git a/test_regress/t/t_interface_generic_task.v b/test_regress/t/t_interface_generic_task.v
index 7e31fcea3..ee94a4583 100644
--- a/test_regress/t/t_interface_generic_task.v
+++ b/test_regress/t/t_interface_generic_task.v
@@ -4,7 +4,7 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf;
+interface ifc;
   int v;
   task setup();
     v = 3;
@@ -15,14 +15,16 @@ interface inf2;
   int k;
 endinterface
 
-module GenericModule (interface a);
+module GenericModule (
+    interface a
+);
   initial begin
     a.setup();
   end
 endmodule
 
 module t;
-  inf inf_inst();
+  ifc inf_inst ();
   GenericModule genericModule (inf_inst);
   initial begin
     #1;
diff --git a/test_regress/t/t_interface_generic_task2.v b/test_regress/t/t_interface_generic_task2.v
index 3895fa70a..d1e254363 100644
--- a/test_regress/t/t_interface_generic_task2.v
+++ b/test_regress/t/t_interface_generic_task2.v
@@ -4,7 +4,7 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf;
+interface ifc;
   int v;
   task setup();
     v = 3;
@@ -15,7 +15,9 @@ interface inf2;
   int k;
 endinterface
 
-module GenericModule (interface a);
+module GenericModule (
+    interface a
+);
   initial begin
     #1;
     if (a.v != 3) $stop;
@@ -23,7 +25,7 @@ module GenericModule (interface a);
 endmodule
 
 module t;
-  inf inf_inst();
+  ifc inf_inst ();
   GenericModule genericModule (inf_inst);
   initial begin
     inf_inst.setup();
diff --git a/test_regress/t/t_interface_generic_task_bad.out b/test_regress/t/t_interface_generic_task_bad.out
index 80eea455c..f29402583 100644
--- a/test_regress/t/t_interface_generic_task_bad.out
+++ b/test_regress/t/t_interface_generic_task_bad.out
@@ -1,6 +1,6 @@
-%Error: t/t_interface_generic_task_bad.v:17:7: Can't find definition of 'setup' in dotted task/function: 'a.setup'
+%Error: t/t_interface_generic_task_bad.v:19:7: Can't find definition of 'setup' in dotted task/function: 'a.setup'
                                              : ... note: In instance 't.genericModule'
-   17 |     a.setup();
+   19 |     a.setup();
       |       ^~~~~
         ... Known scopes under 'setup': <no instances found>
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
diff --git a/test_regress/t/t_interface_generic_task_bad.v b/test_regress/t/t_interface_generic_task_bad.v
index 8a23ec5b2..aca3b493b 100644
--- a/test_regress/t/t_interface_generic_task_bad.v
+++ b/test_regress/t/t_interface_generic_task_bad.v
@@ -4,7 +4,7 @@
 // SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-interface inf;
+interface ifc;
   int v;
 endinterface
 
@@ -12,14 +12,16 @@ interface inf2;
   int k;
 endinterface
 
-module GenericModule (interface a);
+module GenericModule (
+    interface a
+);
   initial begin
     a.setup();
   end
 endmodule
 
 module t;
-  inf inf_inst();
+  ifc inf_inst ();
   GenericModule genericModule (inf_inst);
   initial begin
     #1;
diff --git a/test_regress/t/t_virtual_interface_nba_assign.v b/test_regress/t/t_virtual_interface_nba_assign.v
index a56a72c08..6464f3ddf 100644
--- a/test_regress/t/t_virtual_interface_nba_assign.v
+++ b/test_regress/t/t_virtual_interface_nba_assign.v
@@ -9,7 +9,7 @@ interface clk_if;
   bit clk;
 endinterface
 
-interface inf;
+interface ifc;
   bit clk;
   bit v;
 
@@ -22,14 +22,15 @@ class Clocker;
   virtual clk_if clk;
 
   task clock();
-    fork forever #1 clk.clk = ~clk.clk;
+    fork
+      forever #1 clk.clk = ~clk.clk;
     join_none
   endtask
 endclass
 
 module t;
-  clk_if c();
-  inf i();
+  clk_if c ();
+  ifc i ();
   assign i.clk = c.clk;
   Clocker clocker;
   initial begin
@@ -41,8 +42,9 @@ module t;
     #5;
     $stop;
   end
-  initial @(posedge i.cb.v) begin
-    $write("*-* All Finished *-*\n");
-    $finish;
-  end
+  initial
+    @(posedge i.cb.v) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+    end
 endmodule