161 lines
3.0 KiB
Systemverilog
161 lines
3.0 KiB
Systemverilog
// DESCRIPTION: Verilator: SystemVerilog interface test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2012 Iztok Jeras
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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logic rst = 1'b1; // reset
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integer rst_cnt = 0;
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// reset is removed after a delay
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always @(posedge clk) begin
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rst_cnt <= rst_cnt + 1;
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rst <= rst_cnt <= 3;
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end
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// counters
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int cnt;
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int cnt_src;
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int cnt_drn;
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// add all counters
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assign cnt = cnt_src + cnt_drn + ifc.cnt;
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// finish report
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always @(posedge clk)
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if (cnt == 3 * 16) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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// interface instance
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handshake ifc (
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.clk(clk),
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.rst(rst)
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);
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// source instance
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source #(
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.RW(8),
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.RP(8'b11100001)
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) source (
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.clk(clk),
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.rst(rst),
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.ifc(ifc),
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.cnt(cnt_src)
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);
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// drain instance
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drain #(
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.RW(8),
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.RP(8'b11010100)
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) drain (
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.clk(clk),
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.rst(rst),
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.ifc(ifc),
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.cnt(cnt_drn)
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);
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endmodule : t
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// interface definition
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interface handshake #(
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parameter int unsigned WC = 32
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) (
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input logic clk,
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input logic rst
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);
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// modport signals
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logic req; // request
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logic grt; // grant
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logic inc; // increment
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// local signals
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integer cnt; // counter
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// source
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modport src(output req, input grt);
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// drain
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modport drn(input req, output grt);
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// incremet condition
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assign inc = req & grt;
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// local logic (counter)
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always @(posedge clk, posedge rst)
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if (rst) cnt <= '0;
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else cnt <= cnt + {31'h0, inc};
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endinterface : handshake
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// source module
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module source #(
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// random generator parameters
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parameter int unsigned RW = 1, // LFSR width
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parameter bit [RW-1:0] RP = '0, // LFSR polinom
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parameter bit [RW-1:0] RR = '1 // LFSR reset state
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) (
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input logic clk,
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input logic rst,
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handshake.src ifc,
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output integer cnt
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);
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// LFSR
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logic [RW-1:0] rnd;
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// LFSR in Galois form
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always @(posedge clk, posedge rst)
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if (rst) rnd <= RR;
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else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);
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// counter
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always @(posedge clk, posedge rst)
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if (rst) cnt <= 32'd0;
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else cnt <= cnt + {31'd0, (ifc.req & ifc.grt)};
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// request signal
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assign ifc.req = rnd[0];
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endmodule : source
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// drain module
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module drain #(
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// random generator parameters
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parameter int unsigned RW = 1, // LFSR width
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parameter bit [RW-1:0] RP = '0, // LFSR polinom
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parameter bit [RW-1:0] RR = '1 // LFSR reset state
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) (
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input logic clk,
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input logic rst,
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handshake.drn ifc,
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output integer cnt
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);
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// LFSR
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logic [RW-1:0] rnd;
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// LFSR in Galois form
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always @(posedge clk, posedge rst)
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if (rst) rnd <= RR;
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else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);
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// counter
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always @(posedge clk, posedge rst)
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if (rst) cnt <= 32'd0;
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else cnt <= cnt + {31'd0, (ifc.req & ifc.grt)};
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// grant signal
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assign ifc.grt = rnd[0];
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endmodule : drain
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