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luke
/
sv2v
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mirror of
https://github.com/zachjs/sv2v.git
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2026-09-02 10:27:21 +02:00
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7
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2
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14
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ebd7ae67b18879e8a23363097b3b2da1599291d5
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Zachary Snow
ebd7ae67b1
hacky, preliminary support for port declarations in module header
2019-02-09 17:35:31 -05:00
Data
Basic build setup!
2019-02-08 01:09:33 -05:00
Language
hacky, preliminary support for port declarations in module header
2019-02-09 17:35:31 -05:00
.gitignore
updated build procedure
2019-02-08 16:51:32 -05:00
LICENSE
updated LICENSE to reflect fork
2019-02-08 16:51:20 -05:00
Makefile
updated build procedure
2019-02-08 16:51:32 -05:00
Setup.hs
Initial commit: fork of
https://github.com/tomahawkins/verilog
2019-02-07 23:49:12 -05:00
sv2v.cabal
updated build procedure
2019-02-08 16:51:32 -05:00
sv2v.hs
hacky, preliminary support for port declarations in module header
2019-02-09 17:35:31 -05:00
S
Description
SystemVerilog to Verilog conversion
conversion
systemverilog
verilog
yosys
BSD-3-Clause
3.3
MiB
Languages
Haskell
48.1%
SystemVerilog
26.3%
Verilog
16.4%
Yacc
6.4%
Shell
2.4%
Other
0.3%
