sv2v/src/Convert
Zachary Snow addc550028 minor code cleanup for struct conversion 2019-04-22 02:48:22 -04:00
..
AlwaysKW.hs added some support for a few key non-synthesizable constructs 2019-03-04 21:04:22 -05:00
AsgnOp.hs propper support for indexed part select addressing 2019-04-05 13:53:52 -04:00
Assertion.hs significantly stronger support, and proper handling of assertions 2019-04-03 19:08:30 -04:00
Bits.hs $bits conversion handles basic expressions 2019-04-19 13:32:25 -04:00
Enum.hs enum conversion only produces localparams for enum items that are used 2019-04-19 02:14:21 -04:00
FuncRet.hs revamped support system with most SystemVerilog types and signed types 2019-03-22 17:45:31 -04:00
HoistPortDecls.hs restore port-decl hoisting for cleaner output 2019-04-09 12:50:56 -04:00
Interface.hs clearer messaging surrounding unsupported interface conversion features 2019-04-17 01:44:03 -04:00
KWArgs.hs added conversion for name task and function arguments 2019-04-01 13:16:21 -04:00
Logic.hs several major fixes surrounding packed arrays 2019-04-08 21:28:33 -04:00
NamedBlock.hs added conversion which adds names to unnamed blocks with decls 2019-04-19 19:08:52 -04:00
NestTF.hs added conversion which moves top-level tasks and functions into modules 2019-04-22 01:18:25 -04:00
PackedArray.hs $bits conversion handles basic expressions 2019-04-19 13:32:25 -04:00
Return.hs support for binary blocking assignment operators in statements 2019-03-07 18:16:28 -05:00
StarPort.hs preliminary support for extern and module/interface lifetimes 2019-03-26 15:10:16 -04:00
StmtBlock.hs added conversion to make functions and tasks use only one statement 2019-03-26 21:43:27 -04:00
Struct.hs minor code cleanup for struct conversion 2019-04-22 02:48:22 -04:00
Traverse.hs struct conversion supports complex shadowing 2019-04-22 02:33:24 -04:00
Typedef.hs several major fixes surrounding packed arrays 2019-04-08 21:28:33 -04:00
UnbasedUnsized.hs simple conversion for unbased unsized literals 2019-03-19 13:40:25 -04:00
Unique.hs additional SystemVerilog language support 2019-03-30 00:47:42 -04:00