20 Commits

Author	SHA1	Message	Date
Zachary Snow	f44e3e808a	add option to skip preprocessing	2020-03-18 20:02:20 -04:00
Zachary Snow	da087cc2c1	release v0.0.2	2020-02-22 19:53:35 -05:00
Zachary Snow	3c08767b63	redesigned preprocessor and lexer	2020-02-06 23:33:13 -05:00
Zachary Snow	58ad1feab1	allow reading from stdin	2019-11-19 23:29:19 -05:00
Zachary Snow	06411d70f1	support converting interfaces with parameters	2019-10-20 15:58:37 -04:00
Zachary Snow	baf95b2729	minor README updates	2019-10-02 23:52:26 -04:00
Zachary Snow	c0e38f793d	updated CLI (backwards compatible)	2019-09-15 10:31:50 -04:00
Zachary Snow	ae239f16b7	updated usage documentation	2019-08-07 22:10:03 -04:00
Zachary Snow	2d003c6ded	conversion for package-scoped tasks, functions, and typenames	2019-04-24 04:01:33 -04:00
Dave Eckhardt	5583eaeca8	README.md: wording tweaks.	2019-04-23 15:48:11 -04:00
Zachary Snow	68cccff2b1	updated README with acknowledgments	2019-04-23 14:07:59 -04:00
Dave Eckhardt	9725ed3992	README.md: wording tweaks.	2019-04-23 13:48:00 -04:00
Zachary Snow	68b6eae484	updated documentation	2019-04-18 19:33:16 -04:00
Zachary Snow	f47446653d	Updated README	2019-04-03 23:40:28 -04:00
Zachary Snow	f59ed11ef5	add support for specifying compile-time defines	2019-04-02 16:19:59 -04:00
Zachary Snow	0d9ed3e1fa	updated CLI to support include dirs and multiple files	2019-03-28 19:55:53 -04:00
Zachary Snow	69a5585a7f	updated IEEE standard references in README	2019-03-27 03:41:41 -04:00
Zachary Snow	d7f641b850	pivoted to general Verilog-2005 targeting	2019-03-08 11:02:40 -05:00
Zachary Snow	cf23267783	split up Yosys and VTR targeting	2019-02-26 15:03:49 -05:00
Zachary Snow	65e288fce8	added initial Readme; tweaked copyright notice	2019-02-24 14:59:00 -05:00