2019-02-18 05:39:01 +01:00
|
|
|
{- sv2v
|
|
|
|
|
- Author: Zachary Snow <zach@zachjs.com>
|
|
|
|
|
-
|
|
|
|
|
- SystemVerilog to Verilog conversion
|
|
|
|
|
-}
|
|
|
|
|
|
|
|
|
|
module Convert (convert) where
|
|
|
|
|
|
|
|
|
|
import Language.SystemVerilog.AST
|
2019-03-08 17:02:40 +01:00
|
|
|
import qualified Job (Exclude(..))
|
2019-02-18 05:39:01 +01:00
|
|
|
|
2019-02-18 07:38:16 +01:00
|
|
|
import qualified Convert.AlwaysKW
|
2019-03-05 01:58:54 +01:00
|
|
|
import qualified Convert.AsgnOp
|
2019-04-04 01:08:30 +02:00
|
|
|
import qualified Convert.Assertion
|
2019-04-02 06:16:06 +02:00
|
|
|
import qualified Convert.Bits
|
2019-03-01 04:44:31 +01:00
|
|
|
import qualified Convert.Enum
|
2019-03-06 20:36:16 +01:00
|
|
|
import qualified Convert.FuncRet
|
2019-03-07 02:30:47 +01:00
|
|
|
import qualified Convert.Interface
|
2019-04-01 19:16:21 +02:00
|
|
|
import qualified Convert.KWArgs
|
2019-02-18 07:38:16 +01:00
|
|
|
import qualified Convert.Logic
|
2019-04-20 01:08:52 +02:00
|
|
|
import qualified Convert.NamedBlock
|
2019-04-22 07:18:25 +02:00
|
|
|
import qualified Convert.NestTF
|
2019-02-28 06:16:53 +01:00
|
|
|
import qualified Convert.PackedArray
|
2019-03-06 06:51:09 +01:00
|
|
|
import qualified Convert.Return
|
2019-02-20 21:22:26 +01:00
|
|
|
import qualified Convert.StarPort
|
2019-03-27 02:43:27 +01:00
|
|
|
import qualified Convert.StmtBlock
|
2019-03-06 06:51:09 +01:00
|
|
|
import qualified Convert.Struct
|
2019-03-05 00:25:14 +01:00
|
|
|
import qualified Convert.Typedef
|
2019-03-19 18:40:25 +01:00
|
|
|
import qualified Convert.UnbasedUnsized
|
2019-03-05 00:25:14 +01:00
|
|
|
import qualified Convert.Unique
|
2019-02-18 05:39:01 +01:00
|
|
|
|
2019-02-18 09:59:17 +01:00
|
|
|
type Phase = AST -> AST
|
2019-02-18 05:39:01 +01:00
|
|
|
|
2019-03-08 17:02:40 +01:00
|
|
|
phases :: [Job.Exclude] -> [Phase]
|
|
|
|
|
phases excludes =
|
2019-03-05 01:58:54 +01:00
|
|
|
[ Convert.AsgnOp.convert
|
2019-04-20 01:08:52 +02:00
|
|
|
, Convert.NamedBlock.convert
|
2019-04-04 01:08:30 +02:00
|
|
|
, Convert.Assertion.convert
|
2019-04-02 06:16:06 +02:00
|
|
|
, Convert.Bits.convert
|
2019-03-31 21:57:28 +02:00
|
|
|
, selectExclude (Job.Logic , Convert.Logic.convert)
|
2019-03-06 20:36:16 +01:00
|
|
|
, Convert.FuncRet.convert
|
2019-03-05 01:58:54 +01:00
|
|
|
, Convert.Enum.convert
|
2019-04-01 19:16:21 +02:00
|
|
|
, Convert.KWArgs.convert
|
2019-02-28 06:16:53 +01:00
|
|
|
, Convert.PackedArray.convert
|
2019-02-26 21:03:49 +01:00
|
|
|
, Convert.StarPort.convert
|
2019-03-27 02:43:27 +01:00
|
|
|
, Convert.StmtBlock.convert
|
2019-03-06 06:51:09 +01:00
|
|
|
, Convert.Struct.convert
|
|
|
|
|
, Convert.Return.convert
|
2019-03-01 04:44:31 +01:00
|
|
|
, Convert.Typedef.convert
|
2019-03-19 18:40:25 +01:00
|
|
|
, Convert.UnbasedUnsized.convert
|
2019-03-05 00:25:14 +01:00
|
|
|
, Convert.Unique.convert
|
2019-03-31 21:57:28 +02:00
|
|
|
, selectExclude (Job.Interface, Convert.Interface.convert)
|
|
|
|
|
, selectExclude (Job.Always , Convert.AlwaysKW.convert)
|
2019-04-22 07:18:25 +02:00
|
|
|
, Convert.NestTF.convert
|
2019-03-31 21:57:28 +02:00
|
|
|
]
|
2019-03-08 17:02:40 +01:00
|
|
|
where
|
|
|
|
|
selectExclude :: (Job.Exclude, Phase) -> Phase
|
|
|
|
|
selectExclude (exclude, phase) =
|
|
|
|
|
if elem exclude excludes
|
|
|
|
|
then id
|
|
|
|
|
else phase
|
2019-02-18 05:39:01 +01:00
|
|
|
|
2019-03-08 17:02:40 +01:00
|
|
|
run :: [Job.Exclude] -> Phase
|
|
|
|
|
run excludes = foldr (.) id $ phases excludes
|
2019-02-18 05:39:01 +01:00
|
|
|
|
2019-03-08 17:02:40 +01:00
|
|
|
convert :: [Job.Exclude] -> Phase
|
|
|
|
|
convert excludes = convert'
|
2019-02-26 21:03:49 +01:00
|
|
|
where
|
|
|
|
|
convert' :: Phase
|
|
|
|
|
convert' descriptions =
|
|
|
|
|
if descriptions == descriptions'
|
|
|
|
|
then descriptions
|
|
|
|
|
else convert' descriptions'
|
2019-03-08 17:02:40 +01:00
|
|
|
where descriptions' = run excludes descriptions
|