1c63972bd2
propagate_IOB_SING and propagate_IOI_SING walk each IO column from a
parent IOB/IOI tile down to the SING half-tiles at the column endpoints
and alias the parent's CLB_IO_CLK bits into both halves (offset=0 for
the bottom SING, offset=99 for the top SING). The parent-type
allowlists were missing the HP-bank L-column types:
propagate_IOB_SING: ["LIOB33", "RIOB33", "RIOB18"] # LIOB18 missing
propagate_IOI_SING: ["LIOI3", "RIOI3", "RIOI"] # LIOI missing
On artix7 / kintex7 the leftmost HP column doesn't exist as a parent
LIOB18 / LIOI in the tilegrid, so the omission was latent. On
virtex7 VX (HP-only) both LIOB18 and RIOB18 columns exist, and the
gap surfaces as half the SING IOB / IOI tiles (the L-column ones)
having empty bits in tilegrid.json:
LIOB18_SING: 0/14 with bits -> 14/14
RIOB18_SING: 14/14 (unchanged)
LIOI_SING: 0/14 with bits -> 14/14
RIOI_SING: 14/14 (unchanged)
Add the missing types. Cross-checked against iob18's own measured
parent bases (e.g. LIOB18_X81Y2 -> 0x00421000 lines up with the
propagated LIOB18_SING_X81Y1 base 0x00421000 offset=0 and Y51 offset=99).
Also de-wire the iob18_sing sub-fuzzer from TILEGRID_TDB_DEPENDENCIES:
SING tiles aren't independently addressed (they share the parent IOB's
base with a word-offset variant), and half of iob18_sing's tdb entries
land at an unaligned frame (offset+1) that add_tdb's frame-alignment
assertion would reject anyway. The build rule stays so the fuzzer can
be invoked manually as a Vivado-measurement guard for the propagation.
Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
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||
|---|---|---|
| .. | ||
| bram | ||
| bram_block | ||
| bram_int | ||
| cfg | ||
| cfg_int | ||
| clb | ||
| clb_int | ||
| clk_bufg | ||
| clk_hrow | ||
| dsp | ||
| dsp_int | ||
| fifo_int | ||
| fuzzaddr | ||
| gtp_channel | ||
| gtp_common | ||
| gtp_int_interface | ||
| gtx_channel | ||
| gtx_common | ||
| gtx_int_interface | ||
| hclk_cmt | ||
| hclk_ioi | ||
| iob | ||
| iob18 | ||
| iob18_int | ||
| iob18_sing | ||
| iob_int | ||
| ioi | ||
| ioi18 | ||
| mmcm | ||
| monitor | ||
| monitor_int | ||
| orphan_int_column | ||
| pcie | ||
| pcie_int_interface | ||
| pll | ||
| ps7_int | ||
| Makefile | ||
| README.md | ||
| add_tdb.py | ||
| generate.py | ||
| generate.sh | ||
| generate_full.py | ||
| generate_tiles.tcl | ||
| top.v | ||
| util.py | ||
| util.tcl | ||
README.md
Tilegrid Fuzzer
This fuzzer creates the tilegrid.json bitstream database. This database contains segment definitions including base frame address and frame offsets.
Example workflow for CLB
generate.tcl LOCs one LUT per segment column towards generating frame base addresses.
A reference bitstream is generated and then:
- a series of bitstreams are generated each with one LUT bit toggled; then
- these are compared to find a toggled bit in the CLB segment column; then
- the resulting address is truncated to get the base frame address.
Finally, generate.py calculates the segment word offsets based on known segment column structure
Environment variables
XRAY_ROI
This environment variable must be set with a valid ROI. See database for example values
XRAY_EXCLUDE_ROI_TILEGRID
This environment variable must be set in case the part selected does not allow some tiles to be locked.
Error example (when using the artix 200T part):
ERROR: [Place 30-25] Component carry4_SLICE_X82Y249 has been locked to a prohibited site SLICE_X82Y249.
To avoid this error, the XRAY_EXCLUDE_ROI_TILEGRID defines an ROI that is not taken into account
when building the tilegrid, therefore excluding the problematic un-lockable sites.
As the resulting output file, tilegrid.json, is going to be checked against the one produced in
the 074-dump_all fuzzer, also the latter one needs to produce a reduced tilegrid, with the excluded
tiles specified with the environment variable.
XRAY_ROI_FRAMES
This can be set to a specific value to speed up processing and reduce disk space If you don't know where your ROI is, just set to to include all values (0x00000000:0xfffffff)
XRAY_ROI_GRID_*
Optionally, use these as a small performance optimization:
- XRAY_ROI_GRID_X1
- XRAY_ROI_GRID_X2
- XRAY_ROI_GRID_Y1
- XRAY_ROI_GRID_Y2
These should, if unused, be set to -1, with this caveat:
WARNING: CLB test generates this based on CLBs but implicitly includes INT
Therefore, if you don't set an explicit XRAY_ROI_GRID_* it may fail if you don't have a CLB*_L at left and a CLB*_R at right.