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Merge remote-tracking branch 'upstream/master'

This commit is contained in:
Hans Baier 2025-02-19 13:33:09 +07:00
parent f0260161db faf9c774a3
commit ce065d470e
38 changed files with 2668 additions and 8 deletions
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4
.github/workflows/Pipeline.yml vendored
View File

@ -79,7 +79,7 @@ jobs:
env:
XRAY_SETTINGS: ${{ matrix.family }}
- uses: actions/upload-artifact@v3
- uses: actions/upload-artifact@v4
if: ${{ always() }}
with:
name: ${{ matrix.family }}
@ -124,7 +124,7 @@ jobs:
- name: Run Test
run: make test --output-sync=target --warn-undefined-variables
- uses: actions/upload-artifact@v3
- uses: actions/upload-artifact@v4
if: ${{ always() }}
with:
path: |

6
.readthedocs.yml
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@ -5,6 +5,11 @@
# Required
version: 2
build:
os: ubuntu-22.04
tools:
python: "3.7"
# Build documentation in the docs/ directory with Sphinx
sphinx:
configuration: docs/conf.py
@ -14,7 +19,6 @@ formats: all
# Optionally set the version of Python and requirements required to build your docs
python:
version: "3.7"
install:
- requirements: docs/requirements.txt

18
fuzzers/005-tilegrid/Makefile
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@ -54,6 +54,9 @@ ifneq (${XRAY_FABRIC}, $(filter ${XRAY_FABRIC}, xc7k480t))
TILEGRID_TDB_DEPENDENCIES += iob18/$(BUILD_FOLDER)/segbits_tilegrid.tdb
TILEGRID_TDB_DEPENDENCIES += iob18_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb
TILEGRID_TDB_DEPENDENCIES += ioi18/$(BUILD_FOLDER)/segbits_tilegrid.tdb
TILEGRID_TDB_DEPENDENCIES += gtx_common/$(BUILD_FOLDER)/segbits_tilegrid.tdb
TILEGRID_TDB_DEPENDENCIES += gtx_channel/$(BUILD_FOLDER)/segbits_tilegrid.tdb
TILEGRID_TDB_DEPENDENCIES += gtx_int_interface/$(BUILD_FOLDER)/segbits_tilegrid.tdb
endif
# These kintex parts give an empty design
@ -173,6 +176,15 @@ gtp_channel/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID}
gtp_int_interface/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID}
cd gtp_int_interface && $(MAKE)
gtx_common/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID}
cd gtx_common && $(MAKE)
gtx_channel/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID}
cd gtx_channel && $(MAKE)
gtx_int_interface/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID}
cd gtx_int_interface && $(MAKE)
$(BUILD_FOLDER)/tilegrid_tdb.json: add_tdb.py $(TILEGRID_TDB_DEPENDENCIES)
python3 add_tdb.py \
--fn-in ${BASICDB_TILEGRID} \
@ -220,6 +232,9 @@ clean:
cd gtp_common && $(MAKE) clean
cd gtp_channel && $(MAKE) clean
cd gtp_int_interface && $(MAKE) clean
cd gtx_common && $(MAKE) clean
cd gtx_channel && $(MAKE) clean
cd gtx_int_interface && $(MAKE) clean
clean_part:
rm -rf $(BUILD_FOLDER) run.${XRAY_PART}.ok
@ -254,6 +269,9 @@ clean_part:
cd gtp_common && $(MAKE) clean_part
cd gtp_channel && $(MAKE) clean_part
cd gtp_int_interface && $(MAKE) clean_part
cd gtx_common && $(MAKE) clean_part
cd gtx_channel && $(MAKE) clean_part
cd gtx_int_interface && $(MAKE) clean_part
.PHONY: database pushdb clean clean_part run

3
fuzzers/005-tilegrid/add_tdb.py
View File

@ -112,6 +112,8 @@ def run(fn_in, fn_out, verbose=False):
("pcie", 36, 101),
("gtp_common", 32, 101),
("gtp_channel", 32, 22),
("gtx_common", 32, 101),
("gtx_channel", 32, 22),
("clb_int", int_frames, int_words),
("iob_int", int_frames, int_words),
("iob18_int", int_frames, int_words),
@ -123,6 +125,7 @@ def run(fn_in, fn_out, verbose=False):
("monitor_int", int_frames, int_words),
("orphan_int_column", int_frames, int_words),
("gtp_int_interface", int_frames, int_words),
("gtx_int_interface", int_frames, int_words),
("pcie_int_interface", int_frames, int_words),
]

2
fuzzers/005-tilegrid/generate_full.py
View File

@ -556,6 +556,8 @@ def run(json_in_fn, json_out_fn, verbose=False):
propagate_INT_bits_in_column(database, tiles_by_grid, tile_frames_map)
propagate_INT_INTERFACE_bits_in_column(
database, tiles_by_grid, "GTP_INT_INTERFACE", tile_frames_map)
propagate_INT_INTERFACE_bits_in_column(
database, tiles_by_grid, "GTX_INT_INTERFACE", tile_frames_map)
propagate_INT_INTERFACE_bits_in_column(
database, tiles_by_grid, "PCIE_INT_INTERFACE", tile_frames_map)
propagate_rebuf(database, tiles_by_grid)

10
fuzzers/005-tilegrid/gtx_channel/Makefile Normal file
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@ -0,0 +1,10 @@
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
N ?= 12
GENERATE_ARGS?="--oneval 1 --design params.csv --dword 16 --dframe 1C"
include ../fuzzaddr/common.mk

37
fuzzers/005-tilegrid/gtx_channel/generate.tcl Normal file
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@ -0,0 +1,37 @@
# Copyright (C) 2017-2020 The Project X-Ray Authors
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
source "$::env(XRAY_DIR)/utils/utils.tcl"
proc run {} {
create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
# Disable MMCM frequency etc sanity checks
set_property IS_ENABLED 0 [get_drc_checks {PDRC-29}]
set_property IS_ENABLED 0 [get_drc_checks {PDRC-30}]
set_property IS_ENABLED 0 [get_drc_checks {AVAL-50}]
set_property IS_ENABLED 0 [get_drc_checks {AVAL-53}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-47}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-51}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-126}]
set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}]
set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}]
place_design
route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit
}
run

61
fuzzers/005-tilegrid/gtx_channel/top.py Normal file
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@ -0,0 +1,61 @@
#!/usr/bin/env python3
# -*- coding: utf-8 -*-
#
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
import os
import random
random.seed(int(os.getenv("SEED"), 16))
from prjxray import util
from prjxray.db import Database
def gen_sites():
db = Database(util.get_db_root(), util.get_part())
grid = db.grid()
for tile_name in sorted(grid.tiles()):
loc = grid.loc_of_tilename(tile_name)
gridinfo = grid.gridinfo_at_loc(loc)
for site_name, site_type in gridinfo.sites.items():
if site_type in ['GTXE2_CHANNEL']:
yield tile_name, site_name
def write_params(params):
pinstr = 'tile,val,site\n'
for tile, (site, val) in sorted(params.items()):
pinstr += '%s,%s,%s\n' % (tile, val, site)
open('params.csv', 'w').write(pinstr)
def run():
print('''
module top(input wire in, output wire out);
''')
params = {}
sites = list(gen_sites())
for (tile_name, site_name), isone in zip(sites,
util.gen_fuzz_states(len(sites))):
params[tile_name] = (site_name, isone)
print(
'''
(* KEEP, DONT_TOUCH, LOC = "{}" *)
GTXE2_CHANNEL #(
.ALIGN_MCOMMA_DET("{}")
) gtxe2_channel_{} ();'''.format(site_name, "TRUE" if isone else "FALSE", site_name))
print("endmodule")
write_params(params)
if __name__ == '__main__':
run()

10
fuzzers/005-tilegrid/gtx_common/Makefile Normal file
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@ -0,0 +1,10 @@
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
N ?= 8
GENERATE_ARGS?="--oneval 0 --design params.csv --dword 45 --dframe 1e"
include ../fuzzaddr/common.mk

36
fuzzers/005-tilegrid/gtx_common/generate.tcl Normal file
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@ -0,0 +1,36 @@
# Copyright (C) 2017-2020 The Project X-Ray Authors
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
source "$::env(XRAY_DIR)/utils/utils.tcl"
proc run {} {
create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
# Disable MMCM frequency etc sanity checks
set_property IS_ENABLED 0 [get_drc_checks {PDRC-29}]
set_property IS_ENABLED 0 [get_drc_checks {PDRC-30}]
set_property IS_ENABLED 0 [get_drc_checks {AVAL-50}]
set_property IS_ENABLED 0 [get_drc_checks {AVAL-53}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-126}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-48}]
set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}]
set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}]
place_design
route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit
}
run

62
fuzzers/005-tilegrid/gtx_common/top.py Normal file
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@ -0,0 +1,62 @@
#!/usr/bin/env python3
# -*- coding: utf-8 -*-
#
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
import os
import random
random.seed(int(os.getenv("SEED"), 16))
from prjxray import util
from prjxray.db import Database
def gen_sites():
db = Database(util.get_db_root(), util.get_part())
grid = db.grid()
for tile_name in sorted(grid.tiles()):
loc = grid.loc_of_tilename(tile_name)
gridinfo = grid.gridinfo_at_loc(loc)
for site_name, site_type in gridinfo.sites.items():
if site_type in ['GTXE2_COMMON']:
yield tile_name, site_name
def write_params(params):
pinstr = 'tile,val,site\n'
for tile, (site, val) in sorted(params.items()):
pinstr += '%s,%s,%s\n' % (tile, val, site)
open('params.csv', 'w').write(pinstr)
def run():
print('''
module top(input wire in, output wire out);
''')
params = {}
sites = list(gen_sites())
for (tile_name, site_name), isone in zip(sites,
util.gen_fuzz_states(len(sites))):
params[tile_name] = (site_name, isone)
attr = 4 if isone else 5
print(
'''
(* KEEP, DONT_TOUCH, LOC="{site}" *)
GTXE2_COMMON #(
.QPLL_FBDIV({attr})
) {site} ();'''.format(attr=attr, site=site_name))
print("endmodule")
write_params(params)
if __name__ == '__main__':
run()

17
fuzzers/005-tilegrid/gtx_int_interface/Makefile Normal file
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@ -0,0 +1,17 @@
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
N ?= 8
GENERATE_ARGS?="--oneval 1 --design params.csv --dframe 1b --dword 0 --dbit 4"
include ../fuzzaddr/common.mk
SEGBITS=$(BUILD_DIR)/segbits_tilegrid.tdb
$(SEGBITS): $(SPECIMENS_OK)
# multiple bits match for the changes, but all of those except the ones with addresses ending with 0x9b are known
# and not related to GTX_INT_INTERFACE
${XRAY_SEGMATCH} -c 6 -o $(BUILD_DIR)/segbits_tilegrid.tdb $$(find $(BUILD_DIR) -name "segdata_tilegrid.txt")
tr ' ' '\n' < $(SEGBITS) | grep -E 'GTX|9B' | paste -d " " - - > $(SEGBITS).tmp
mv -fv $(SEGBITS).tmp $(SEGBITS)

86
fuzzers/005-tilegrid/gtx_int_interface/generate.tcl Normal file
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@ -0,0 +1,86 @@
# Copyright (C) 2017-2020 The Project X-Ray Authors
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
source "$::env(XRAY_DIR)/utils/utils.tcl"
proc parse_csv {} {
set fp [open "params.csv"]
set file_data [read $fp]
close $fp
set file_data [split $file_data "\n"]
set params_map [dict create]
set is_first_line true
foreach line $file_data {
if { $is_first_line } {
set is_first_line false
continue
}
# Skip empty lines
if { $line == "" } {
continue
}
set parts [split $line ","]
dict lappend params_map [lindex $parts 2] [lindex $parts 1]
}
return $params_map
}
proc route_through_delay {} {
set params_map [parse_csv]
dict for { key value } $params_map {
if { $value == 0 } {
continue
}
set net_name "QPLLLOCKEN_$key"
set net [get_nets $net_name]
set wire [get_wires -of_objects $net -filter {TILE_NAME =~ "*GTX_INT_INTERFACE*" && NAME =~ "*IMUX_OUT24*"}]
set wire_parts [split $wire "/"]
set gtx_int_tile [lindex $wire_parts 0]
set node [get_nodes -of_object [get_tiles $gtx_int_tile] -filter { NAME =~ "*DELAY24" }]
route_design -unroute -nets $net
puts "Attempting to route net $net through $node."
route_via $net [list $node]
}
}
proc run {} {
create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
# Disable MMCM frequency etc sanity checks
set_property IS_ENABLED 0 [get_drc_checks {REQP-47}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-48}]
place_design
route_design
route_through_delay
write_checkpoint -force design.dcp
write_bitstream -force design.bit
}
run

104
fuzzers/005-tilegrid/gtx_int_interface/top.py Normal file
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@ -0,0 +1,104 @@
#!/usr/bin/env python3
# -*- coding: utf-8 -*-
#
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
import os
import re
import random
random.seed(int(os.getenv("SEED"), 16))
from prjxray import util
from prjxray.db import Database
from prjxray.grid_types import GridLoc
GTX_INT_Y_RE = re.compile("GTX_INT_INTERFACE.*X[0-9]+Y([0-9]+)")
def get_gtx_int_tile(clock_region, grid):
for tile_name in sorted(grid.tiles()):
if not tile_name.startswith("GTX_INT_INTERFACE"):
continue
loc = grid.loc_of_tilename(tile_name)
left_gridinfo = grid.gridinfo_at_loc(
GridLoc(loc.grid_x - 1, loc.grid_y))
right_gridinfo = grid.gridinfo_at_loc(
GridLoc(loc.grid_x + 1, loc.grid_y))
if left_gridinfo.tile_type in ["INT_L", "INT_R"]:
cmt = left_gridinfo.clock_region
elif right_gridinfo.tile_type in ["INT_L", "INT_R"]:
cmt = right_gridinfo.clock_region
else:
assert False
gridinfo = grid.gridinfo_at_loc(loc)
m = GTX_INT_Y_RE.match(tile_name)
assert m
int_y = int(m.group(1))
if clock_region == cmt and int_y % 50 == 26:
return tile_name
def gen_sites():
db = Database(util.get_db_root(), util.get_part())
grid = db.grid()
for tile_name in sorted(grid.tiles()):
loc = grid.loc_of_tilename(tile_name)
gridinfo = grid.gridinfo_at_loc(loc)
for site_name, site_type in gridinfo.sites.items():
if site_type in ['GTXE2_COMMON']:
gtx_int_tile = get_gtx_int_tile(gridinfo.clock_region, grid)
yield gtx_int_tile, site_name
def write_params(params):
pinstr = 'tile,val,site\n'
for tile, (site, val) in sorted(params.items()):
pinstr += '%s,%s,%s\n' % (tile, val, site)
open('params.csv', 'w').write(pinstr)
def run():
print('''
module top();
''')
params = {}
sites = list(gen_sites())
for gtx_int_tile, site_name in sites:
isone = random.randint(0, 1)
params[gtx_int_tile] = (site_name, isone)
print(
'''
wire QPLLLOCKEN_{site};
(* KEEP, DONT_TOUCH *)
LUT1 lut_{site} (.O(QPLLLOCKEN_{site}));
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
GTXE2_COMMON gtxe2_common_{site} (
.QPLLLOCKEN(QPLLLOCKEN_{site})
);'''.format(site=site_name))
print("endmodule")
write_params(params)
if __name__ == '__main__':
run()

4
fuzzers/005-tilegrid/pcie_int_interface/top.py
View File

@ -16,7 +16,7 @@ from prjxray import util
from prjxray.db import Database
from prjxray.grid_types import GridLoc
GTP_INT_Y_RE = re.compile("PCIE_INT_INTERFACE.*X[0-9]+Y([0-9]+)")
PCIE_INT_Y_RE = re.compile("PCIE_INT_INTERFACE.*X[0-9]+Y([0-9]+)")
def get_pcie_int_tiles(grid, pcie_loc):
@ -36,7 +36,7 @@ def get_pcie_int_tiles(grid, pcie_loc):
if not tile_name.startswith("PCIE_INT_INTERFACE"):
continue
m = GTP_INT_Y_RE.match(tile_name)
m = PCIE_INT_Y_RE.match(tile_name)
assert m

2
fuzzers/005-tilegrid/util.py
View File

@ -105,7 +105,7 @@ def add_tile_bits(
assert offset <= 100, (tile_name, offset)
# Few rare cases at X=0 for double width tiles split in half => small negative offset
assert offset >= 0 or "IOB" in tile_name, (
assert offset >= 0 or "IOB" in tile_name or "GTX_INT_INTERFACE" in tile_name, (
tile_name, hex(baseaddr), offset)
assert 1 <= words <= 101, words
assert offset + words <= 101, (

67
fuzzers/063-gtx-common-conf/Makefile Normal file
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@ -0,0 +1,67 @@
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
SHELL = bash
N ?= 20
BUILD_DIR = build_${XRAY_PART}
SPECIMENS := $(addprefix ${BUILD_DIR}/specimen_,$(shell seq -f '%03.0f' $(N)))
SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
FUZDIR ?= ${PWD}
CELLS_DATA_DIR = ${XRAY_FAMILY_DIR}/cells_data
all: database
# generate.sh / top_generate.sh call make, hence the command must
# have a + before it.
$(SPECIMENS_OK): $(SPECIMENS_DEPS)
mkdir -p ${BUILD_DIR}
bash ${XRAY_DIR}/utils/top_generate.sh $(subst /OK,,$@)
run:
$(MAKE) clean
$(MAKE) database
$(MAKE) pushdb
touch run.${XRAY_PART}.ok
clean:
rm -rf ${BUILD_DIR} run.${XRAY_PART}.ok
.PHONY: all run clean
# These are pins that are hard to parse as a regexp given that the port name ends with a number, which is misinterpreted
# as the index in the port bus
SPECIAL_PINS = PLLRSVD1,PLLRSVD2,GTREFCLK0,GTREFCLK1,GTGREFCLK0,GTGREFCLK1,GTEASTREFCLK0,GTEASTREFCLK1,GTWESTREFCLK0,GTWESTREFCLK1,REFCLKOUTMONITOR0,REFCLKOUTMONITOR1
$(BUILD_DIR)/gtxe2_common_ports.csv: generate_ports.tcl
env FILE_NAME=$(BUILD_DIR)/gtxe2_common_pins.csv ${XRAY_VIVADO} -mode batch -source generate_ports.tcl
$(BUILD_DIR)/gtxe2_common_ports.json: $(BUILD_DIR)/gtxe2_common_ports.csv
python3 ${XRAY_UTILS_DIR}/make_ports.py $(BUILD_DIR)/gtxe2_common_pins.csv $(BUILD_DIR)/gtxe2_common_ports.json --special-pins $(SPECIAL_PINS)
database: ${BUILD_DIR}/segbits_gtx_common.db $(BUILD_DIR)/gtxe2_common_ports.json
${BUILD_DIR}/segbits_gtx_common.rdb: $(SPECIMENS_OK)
${XRAY_SEGMATCH} -o ${BUILD_DIR}/segbits_gtx_common.rdb $$(find $(SPECIMENS) -name "segdata_gtx_common*")
${BUILD_DIR}/segbits_gtx_common.db: ${BUILD_DIR}/segbits_gtx_common.rdb
${XRAY_DBFIXUP} --db-root ${BUILD_DIR} --zero-db bits.dbf \
--seg-fn-in ${BUILD_DIR}/segbits_gtx_common.rdb \
--seg-fn-out ${BUILD_DIR}/segbits_gtx_common.db
${XRAY_MASKMERGE} ${BUILD_DIR}/mask_gtx_common.db $$(find $(SPECIMENS) -name "segdata_gtx_common*")
pushdb:
mkdir -p $(CELLS_DATA_DIR)
cp attrs.json $(CELLS_DATA_DIR)/gtxe2_common_attrs.json
cp $(BUILD_DIR)/gtxe2_common_ports.json $(CELLS_DATA_DIR)/gtxe2_common_ports.json
BUILD_DIR=$(BUILD_DIR) source pushdb.sh
.PHONY: database pushdb

33
fuzzers/063-gtx-common-conf/README.md Normal file
View File

@ -0,0 +1,33 @@
GTXE2\_COMMON Primitive Configuration fuzzer
============================================
This fuzzer is used to document the parameters corresponding to the GTXE2\_COMMON primitive.
It uses pre-built JSON containing a dictionary of parameters, each one with four attributes:
- Type: one of Binary, Integer, String, Boolean.
- Values: all possible values that this parameter can assume. In case of `BIN` types, the values list contains only the maximum value reachable.
- Digits: number of digits (or bits) required to use a parameter.
- Encoding: This is present only for `INT` types of parameters. These reflect the actual encoding of the parameter value in the bit array.
E.g.:
```json
{
"PLL0_REFCLK_DIV": {
"type": "INT",
"values": [1, 2],
"encoding": [16, 0],
"digits": 5
}
}
```
In addition, there exist wires and PIPs that allow the connections of the `GTREFCLK` ports to clocks coming from the device fabric instead of the `IBUFDS_GTE2` primitive.
In fact, if the clock comes from the device fabric, the physical `GTGREFCLK[01]` port is used instead of the `GTREFCLK[01]` one (even though the design's primitive port is always `GTREFCLK`).
In the [User Guide (pg 27)](https://docs.amd.com/v/u/en-US/ug476_7Series_Transceivers), it is stated that the `GTGREFCLK[01]` port is used for "internal testing purposes".
Using this port is highly discouraged to get the reference clock from the fabric, as the recommended way is to get the clock from an external source using the `IBUFDS_GTE2` primitive.
Therefore, in addition to the parameters, `IN_USE` and `ZINV\INV` features, this fuzzer documents also the `GTREFCLK[01]_USED` and `BOTH_GTREFCLK[01]_USED` features.

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{
"QPLL_CFG": {
"type": "BIN",
"values": [134150145],
"digits": 27
},
"QPLL_CP": {
"type": "BIN",
"values": [1023],
"digits": 10
},
"QPLL_CP_MONITOR_EN": {
"type": "BIN",
"values": [1],
"digits": 1
},
"QPLL_DMONITOR_SEL": {
"type": "BIN",
"values": [1],
"digits": 1
},
"QPLL_REFCLK_DIV": {
"type": "INT",
"values": [1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 20],
"encoding": [16, 0, 1, 2, 3, 5, 6, 7, 13, 14, 15],
"digits": 5
},
"QPLL_FBDIV": {
"type": "BIN",
"values": [496],
"digits": 10
},
"QPLL_FBDIV_MONITOR_EN": {
"type": "BIN",
"values": [1],
"digits": 1
},
"QPLL_FBDIV_RATIO": {
"type": "BIN",
"values": [1],
"digits": 1
},
"QPLL_LOCK_CFG": {
"type": "BIN",
"values": [65535],
"digits": 16
},
"QPLL_INIT_CFG": {
"type": "BIN",
"values": [16777215],
"digits": 24
},
"QPLL_LPF": {
"type": "BIN",
"values": [15],
"digits": 4
},
"COMMON_CFG": {
"type": "BIN",
"values": [4294836225],
"digits": 32
},
"QPLL_CLKOUT_CFG": {
"type": "BIN",
"values": [15],
"digits": 4
},
"QPLL_COARSE_FREQ_OVRD": {
"type": "BIN",
"values": [63],
"digits": 5
},
"QPLL_COARSE_FREQ_OVRD_EN": {
"type": "BIN",
"values": [1],
"digits": 1
},
"BIAS_CFG": {
"type": "BIN",
"values": [18445618199572250625],
"digits": 64
}
}

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#!/usr/bin/env python3
# -*- coding: utf-8 -*-
#
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
import json
import os
from enum import Enum
from prjxray.segmaker import Segmaker
#from icecream import ic
INT = "INT"
BIN = "BIN"
def bitfilter_gtx_common_mid(frame, bit):
# Filter out non interesting bits.
word = int(bit / 32)
if word < 44 or word > 56:
return False
if frame not in [0, 1]:
return False
return True
def bitfilter_gtx_common(frame, bit):
# Filter out non interesting bits.
word = int(bit / 32)
if word < 44 or word > 56:
return False
# let ENABLE_DRP come through
if (frame == 24 or frame or frame == 25) and bit == 1613:
return True
if frame < 30 or frame > 31:
return False
return True
def main():
segmk = Segmaker("design.bits")
fuz_dir = os.getenv("FUZDIR", None)
assert fuz_dir
with open(os.path.join(fuz_dir, "attrs.json"), "r") as attr_file:
attrs = json.load(attr_file)
print("Loading tags")
with open("params.json") as f:
params_dict = json.load(f)
tile_type = params_dict["tile_type"]
params_list = params_dict["params"]
sites_in_tile = dict()
for params in params_list:
site = params["site"]
tile = params["tile"]
if "GTXE2_COMMON" not in site:
continue
sites_in_tile[tile] = site
in_use = params["IN_USE"]
segmk.add_site_tag(site, "IN_USE", in_use)
if in_use:
for param, param_info in attrs.items():
value = params[param]
param_type = param_info["type"]
param_digits = param_info["digits"]
param_values = param_info["values"]
if param_type == INT:
param_encodings = param_info["encoding"]
param_encoding = param_encodings[param_values.index(value)]
bitstr = [
int(x) for x in "{value:0{digits}b}".format(
value=param_encoding, digits=param_digits)[::-1]
]
for i in range(param_digits):
segmk.add_site_tag(
site, '%s[%u]' % (param, i), bitstr[i])
else:
assert param_type == BIN
bitstr = [
int(x) for x in "{value:0{digits}b}".format(
value=value, digits=param_digits)[::-1]
]
for i in range(param_digits):
segmk.add_site_tag(
site, "%s[%u]" % (param, i), bitstr[i])
for param in ["QPLLLOCKDETCLK", "DRPCLK"]:
segmk.add_site_tag(site, "INV_" + param, params[param])
for param in ["GTREFCLK0_USED", "GTREFCLK1_USED",
"BOTH_GTREFCLK_USED"]:
segmk.add_site_tag(site, param, params[param])
segmk.add_site_tag(site, "ENABLE_DRP", params["ENABLE_DRP"])
for params in params_list:
site = params["site"]
if "IBUFDS_GTE2" not in site:
continue
in_use = params["IN_USE"]
segmk.add_site_tag(site, "IN_USE", in_use)
if in_use:
tile = params["tile"]
for param in ["CLKRCV_TRST", "CLKCM_CFG"]:
value = params[param]
segmk.add_site_tag(site, param, "TRUE" in value)
bitstr = [
int(x) for x in "{value:0{digits}b}".format(
value=params["CLKSWING_CFG"], digits=2)[::-1]
]
gtx_common_site = sites_in_tile[tile]
for i in range(2):
segmk.add_site_tag(
gtx_common_site, "IBUFDS_GTE2.CLKSWING_CFG[%u]" % (i),
bitstr[i])
if tile_type.startswith("GTX_COMMON_MID"):
bitfilter = bitfilter_gtx_common_mid
elif tile_type == "GTX_COMMON":
bitfilter = bitfilter_gtx_common
else:
assert False, tile_type
segmk.compile(bitfilter=bitfilter)
segmk.write()
if __name__ == '__main__':
main()

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# Copyright (C) 2017-2020 The Project X-Ray Authors
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
proc run {} {
create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}]
set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-48}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-47}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-51}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-1619}]
place_design
route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit
}
run

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# Copyright (C) 2017-2020 The Project X-Ray Authors
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
source "$::env(XRAY_DIR)/utils/utils.tcl"
create_project -force -name design -part $::env(XRAY_PART)
set_property design_mode PinPlanning [current_fileset]
open_io_design -name io_1
dump_pins $::env(FILE_NAME) GTXE2_COMMON

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#!/bin/bash
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
if ! test $(find ${BUILD_DIR} -name "segdata_gtx_common_mid_right.txt" | wc -c) -eq 0
then
${XRAY_MERGEDB} gtx_common_mid_right ${BUILD_DIR}/segbits_gtx_common.db
${XRAY_MERGEDB} mask_gtx_common_mid_right ${BUILD_DIR}/mask_gtx_common.db
${XRAY_MERGEDB} gtx_common_mid_left ${BUILD_DIR}/segbits_gtx_common.db
${XRAY_MERGEDB} mask_gtx_common_mid_left ${BUILD_DIR}/mask_gtx_common.db
fi
if ! test $(find ${BUILD_DIR} -name "segdata_gtx_common.txt" | wc -c) -eq 0
then
${XRAY_MERGEDB} gtx_common ${BUILD_DIR}/segbits_gtx_common.db
${XRAY_MERGEDB} mask_gtx_common ${BUILD_DIR}/mask_gtx_common.db
fi

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#!/usr/bin/env python3
# -*- coding: utf-8 -*-
#
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
import json
import os
import random
from collections import namedtuple
random.seed(int(os.getenv("SEED"), 16))
from prjxray import util
from prjxray import verilog
from prjxray.lut_maker import LutMaker
from prjxray.db import Database
INT = "INT"
BIN = "BIN"
def gen_sites(tile, site, filter_cmt=None):
db = Database(util.get_db_root(), util.get_part())
grid = db.grid()
for tile_name in sorted(grid.tiles()):
loc = grid.loc_of_tilename(tile_name)
gridinfo = grid.gridinfo_at_loc(loc)
if tile not in gridinfo.tile_type:
continue
else:
tile_type = gridinfo.tile_type
for site_name, site_type in gridinfo.sites.items():
if site_type != site:
continue
cmt = gridinfo.clock_region
if filter_cmt is not None and cmt != filter_cmt:
continue
yield tile_name, tile_type, site_name, cmt
def main():
print(
'''
module top(
input wire in,
output wire out
);
assign out = in;
''')
luts = LutMaker()
params_dict = {"tile_type": None}
params_list = list()
clkswing_cfg_tiles = dict()
ibufds_out_wires = dict()
for tile_name, _, site_name, _ in gen_sites("GTX_COMMON", "IBUFDS_GTE2"):
# Both the IBUFDS_GTE2 in the same tile need to have
# the same CLKSWING_CFG parameter
if tile_name not in clkswing_cfg_tiles:
clkswing_cfg = random.randint(0, 3)
clkswing_cfg_tiles[tile_name] = clkswing_cfg
else:
clkswing_cfg = clkswing_cfg_tiles[tile_name]
in_use = bool(random.randint(0, 9))
params = {
"site":
site_name,
"tile":
tile_name,
"IN_USE":
in_use,
"CLKRCV_TRST":
verilog.quote("TRUE" if random.randint(0, 1) else "FALSE"),
"CLKCM_CFG":
verilog.quote("TRUE" if random.randint(0, 1) else "FALSE"),
"CLKSWING_CFG":
clkswing_cfg,
}
if in_use:
ibufds_out_wire = "{}_O".format(site_name)
if tile_name not in ibufds_out_wires:
ibufds_out_wires[tile_name] = list()
ibufds_out_wires[tile_name].append(
(ibufds_out_wire, int(site_name[-1]) % 2))
print("wire {};".format(ibufds_out_wire))
print("(* KEEP, DONT_TOUCH, LOC=\"{}\" *)".format(site_name))
print(
"""
IBUFDS_GTE2 #(
.CLKRCV_TRST({CLKRCV_TRST}),
.CLKCM_CFG({CLKCM_CFG}),
.CLKSWING_CFG({CLKSWING_CFG})
) {site} (
.O({out})
);""".format(**params, out=ibufds_out_wire))
params_list.append(params)
DRP_PORTS = [
("DRPCLK", "clk"), ("DRPEN", "in"), ("DRPWE", "in"), ("DRPRDY", "out")
]
for tile_name, tile_type, site_name, cmt in gen_sites("GTX_COMMON",
"GTXE2_COMMON"):
params_dict["tile_type"] = tile_type
params = dict()
params['site'] = site_name
params['tile'] = tile_name
verilog_attr = ""
verilog_attr = "#("
fuz_dir = os.getenv("FUZDIR", None)
assert fuz_dir
with open(os.path.join(fuz_dir, "attrs.json"), "r") as attrs_file:
attrs = json.load(attrs_file)
in_use = bool(random.randint(0, 9))
params["IN_USE"] = in_use
if in_use:
for param, param_info in attrs.items():
param_type = param_info["type"]
param_values = param_info["values"]
param_digits = param_info["digits"]
if param_type == INT:
value = random.choice(param_values)
value_str = value
else:
assert param_type == BIN
value = random.randint(0, param_values[0])
value_str = "{digits}'b{value:0{digits}b}".format(
value=value, digits=param_digits)
params[param] = value
verilog_attr += """
.{}({}),""".format(param, value_str)
verilog_ports = ""
for param in ["QPLLLOCKDETCLK", "DRPCLK"]:
is_inverted = random.randint(0, 1)
params[param] = is_inverted
verilog_attr += """
.IS_{}_INVERTED({}),""".format(param, is_inverted)
verilog_ports += """
.{}({}),""".format(param, luts.get_next_output_net())
verilog_attr = verilog_attr.rstrip(",")
verilog_attr += "\n)"
for param in ["GTREFCLK0_USED", "GTREFCLK1_USED",
"BOTH_GTREFCLK_USED"]:
params[param] = 0
if tile_name in ibufds_out_wires:
gtrefclk_ports_used = 0
for wire, location in ibufds_out_wires[tile_name]:
if random.random() < 0.5:
continue
verilog_ports += """
.GTREFCLK{}({}),""".format(location, wire)
gtrefclk_ports_used += 1
params["GTREFCLK{}_USED".format(location)] = 1
if gtrefclk_ports_used == 2:
params["BOTH_GTREFCLK_USED"] = 1
enable_drp = random.randint(0, 1)
params["ENABLE_DRP"] = enable_drp
for _, _, channel_site_name, _ in gen_sites("GTX_CHANNEL",
"GTXE2_CHANNEL", cmt):
if not enable_drp:
break
verilog_ports_channel = ""
for port, direction in DRP_PORTS:
if direction == "in":
verilog_ports_channel += """
.{}({}),""".format(port, luts.get_next_output_net())
elif direction == "clk":
# DRPCLK needs to come from a clock source
print(
"""
wire clk_bufg_{site};
(* KEEP, DONT_TOUCH *)
BUFG bufg_{site} (.O(clk_bufg_{site}));""".format(site=channel_site_name))
verilog_ports_channel += """
.{}(clk_bufg_{}),""".format(port, channel_site_name)
elif direction == "out":
verilog_ports_channel += """
.{}({}),""".format(port, luts.get_next_input_net())
print(
"""
(* KEEP, DONT_TOUCH, LOC=\"{site}\" *)
GTXE2_CHANNEL {site} (
{ports}
);""".format(ports=verilog_ports_channel.rstrip(","), site=channel_site_name))
print(
"""
(* KEEP, DONT_TOUCH, LOC=\"{site}\" *)
GTXE2_COMMON {attrs} {site} (
{ports}
);""".format(
attrs=verilog_attr,
ports=verilog_ports.rstrip(","),
site=site_name))
params_list.append(params)
for l in luts.create_wires_and_luts():
print(l)
print("endmodule")
params_dict["params"] = params_list
with open('params.json', 'w') as f:
json.dump(params_dict, f, indent=2)
if __name__ == '__main__':
main()

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# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
SHELL = bash
N ?= 40
BUILD_DIR = build_${XRAY_PART}
SPECIMENS := $(addprefix ${BUILD_DIR}/specimen_,$(shell seq -f '%03.0f' $(N)))
SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
FUZDIR ?= ${PWD}
CELLS_DATA_DIR = ${XRAY_FAMILY_DIR}/cells_data
all: database
$(SPECIMENS_OK): $(SPECIMENS_DEPS)
mkdir -p ${BUILD_DIR}
bash ${XRAY_DIR}/utils/top_generate.sh $(subst /OK,,$@)
run:
$(MAKE) clean
$(MAKE) database
$(MAKE) pushdb
touch run.${XRAY_PART}.ok
clean:
rm -rf ${BUILD_DIR} run.${XRAY_PART}.ok
.PHONY: all run clean
# These are pins that are hard to parse as a regexp given that the port name ends with a number, which is misinterpreted
# as the index in the port bus
SPECIAL_PINS = CLKRSVD0,CLKRSVD1,GTREFCLK0,GTREFCLK1,GTNORTHREFCLK0,GTNORTHREFCLK1,GTSOUTHREFCLK0,GTSOUTHREFCLK1,RXUSRCLK,RXUSRCLK2,TXUSRCLK,TXUSRCLK2,RXOSINTID0,PMARSVDIN0,PMARSVDIN1,PMARSVDIN2,PMARSVDIN3,PMARSVDIN4,PMARSVDOUT0,PMARSVDOUT1
$(BUILD_DIR)/gtxe2_channel_ports.csv:
env FILE_NAME=$(BUILD_DIR)/gtxe2_channel_pins.csv ${XRAY_VIVADO} -mode batch -source generate_ports.tcl
$(BUILD_DIR)/gtxe2_channel_ports.json: $(BUILD_DIR)/gtxe2_channel_ports.csv
python3 ${XRAY_UTILS_DIR}/make_ports.py $(BUILD_DIR)/gtxe2_channel_pins.csv $(BUILD_DIR)/gtxe2_channel_ports.json --special-pins $(SPECIAL_PINS)
database: ${BUILD_DIR}/segbits_gtx_channelx.db $(BUILD_DIR)/gtxe2_channel_ports.json
${BUILD_DIR}/segbits_gtx_channelx.rdb: $(SPECIMENS_OK)
find ${BUILD_DIR} -name segdata_gtx_channel_\*.txt | xargs sed -i -e 's/CHANNEL_[0-3]/CHANNEL/g'
${XRAY_SEGMATCH} -c 10 -o ${BUILD_DIR}/segbits_gtx_channelx.rdb $$(find $(SPECIMENS) -name "segdata_gtx_channel_[0123]*")
${BUILD_DIR}/segbits_gtx_channelx.db: ${BUILD_DIR}/segbits_gtx_channelx.rdb
${XRAY_DBFIXUP} --db-root ${BUILD_DIR} --zero-db bits.dbf \
--seg-fn-in ${BUILD_DIR}/segbits_gtx_channelx.rdb \
--seg-fn-out ${BUILD_DIR}/segbits_gtx_channelx.db
${XRAY_MASKMERGE} ${BUILD_DIR}/mask_gtx_channelx.db $$(find $(SPECIMENS) -name "segdata_gtx_channel_[0123]*")
pushdb:
mkdir -p $(CELLS_DATA_DIR)
cp attrs.json $(CELLS_DATA_DIR)/gtxe2_channel_attrs.json
cp $(BUILD_DIR)/gtxe2_channel_ports.json $(CELLS_DATA_DIR)/gtxe2_channel_ports.json
BUILD_DIR=$(BUILD_DIR) source pushdb.sh
.PHONY: database pushdb

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#!/usr/bin/env python3
# -*- coding: utf-8 -*-
#
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
import json
import os
from enum import Enum
from prjxray.segmaker import Segmaker, add_site_group_zero
INT = "INT"
BIN = "BIN"
BOOL = "BOOL"
STR = "STR"
def bitfilter_gtx_channel_x(frame, bit):
# Filter out interconnect bits.
if frame not in [28, 29, 30, 31]:
return False
return True
def bitfilter_gtx_channel_x_mid(frame, bit):
# Filter out interconnect bits.
if frame not in [0, 1, 2, 3]:
return False
return True
def main():
segmk = Segmaker("design.bits")
fuz_dir = os.getenv("FUZDIR", None)
assert fuz_dir
with open(os.path.join(fuz_dir, "attrs.json"), "r") as attr_file:
attrs = json.load(attr_file)
print("Loading tags")
with open("params.json") as f:
primitives_list = json.load(f)
for primitive in primitives_list:
tile_type = primitive["tile_type"]
params_list = primitive["params"]
for params in params_list:
site = params["site"]
if "GTXE2_CHANNEL" not in site:
continue
in_use = params["IN_USE"]
segmk.add_site_tag(site, "IN_USE", in_use)
if in_use:
for param, param_info in attrs.items():
value = params[param]
param_type = param_info["type"]
param_digits = param_info["digits"]
param_values = param_info["values"]
if param_type == INT:
param_encodings = param_info["encoding"]
param_encoding = param_encodings[param_values.index(
value)]
bitstr = [
int(x) for x in "{value:0{digits}b}".format(
value=param_encoding, digits=param_digits)
[::-1]
]
for i in range(param_digits):
segmk.add_site_tag(
site, '%s[%u]' % (param, i), bitstr[i])
elif param_type == BIN:
bitstr = [
int(x) for x in "{value:0{digits}b}".format(
value=value, digits=param_digits)[::-1]
]
for i in range(param_digits):
segmk.add_site_tag(
site, "%s[%u]" % (param, i), bitstr[i])
elif param_type == BOOL:
segmk.add_site_tag(site, param, value == "TRUE")
else:
assert param_type == STR
# The RXSLIDE_MODE parameter has overlapping bits
# for its possible values. We need to treat it
# differently
if param == "RXSLIDE_MODE":
add_site_group_zero(
segmk, site, "{}.".format(param), param_values,
"OFF", value)
else:
for param_value in param_values:
segmk.add_site_tag(
site, "{}.{}".format(param, param_value),
value == param_value)
for param in ["TXUSRCLK", "TXUSRCLK2", "TXPHDLYTSTCLK",
"RXUSRCLK", "RXUSRCLK2", "DRPCLK"]:
segmk.add_site_tag(site, "INV_" + param, params[param])
gtx_channel_x = [
"GTX_CHANNEL_0",
"GTX_CHANNEL_1",
"GTX_CHANNEL_2",
"GTX_CHANNEL_3",
]
gtx_channel_x_mid = [
"GTX_CHANNEL_0_MID_LEFT",
"GTX_CHANNEL_1_MID_LEFT",
"GTX_CHANNEL_2_MID_LEFT",
"GTX_CHANNEL_3_MID_LEFT",
"GTX_CHANNEL_0_MID_RIGHT",
"GTX_CHANNEL_1_MID_RIGHT",
"GTX_CHANNEL_2_MID_RIGHT",
"GTX_CHANNEL_3_MID_RIGHT",
]
if tile_type in gtx_channel_x:
bitfilter = bitfilter_gtx_channel_x
elif tile_type in gtx_channel_x_mid:
bitfilter = bitfilter_gtx_channel_x_mid
else:
assert False, tile_type
segmk.compile(bitfilter=bitfilter)
segmk.write()
if __name__ == '__main__':
main()

43
fuzzers/064-gtx-channel-conf/generate.tcl Normal file
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@ -0,0 +1,43 @@
# Copyright (C) 2017-2020 The Project X-Ray Authors
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
proc run {} {
create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}]
set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-48}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-47}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-1619}]
set_property IS_ENABLED 0 [get_drc_checks {AVAL-17}]
set_property IS_ENABLED 0 [get_drc_checks {AVAL-18}]
set_property IS_ENABLED 0 [get_drc_checks {AVAL-19}]
set_property IS_ENABLED 0 [get_drc_checks {AVAL-19}]
set_property IS_ENABLED 0 [get_drc_checks {AVAL-20}]
set_property IS_ENABLED 0 [get_drc_checks {AVAL-20}]
set_property IS_ENABLED 0 [get_drc_checks {AVAL-21}]
set_property IS_ENABLED 0 [get_drc_checks {AVAL-22}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-51}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-51}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-51}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-51}]
set_property IS_ENABLED 0 [get_drc_checks {AVAL-23}]
place_design
route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit
}
run

15
fuzzers/064-gtx-channel-conf/generate_ports.tcl Normal file
View File

@ -0,0 +1,15 @@
# Copyright (C) 2017-2020 The Project X-Ray Authors
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
source "$::env(XRAY_DIR)/utils/utils.tcl"
create_project -force -name design -part $::env(XRAY_PART)
set_property design_mode PinPlanning [current_fileset]
open_io_design -name io_1
dump_pins $::env(FILE_NAME) GTXE2_CHANNEL

40
fuzzers/064-gtx-channel-conf/pushdb.sh Normal file
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@ -0,0 +1,40 @@
#!/bin/bash
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
if ! test $(find ${BUILD_DIR} -name "segdata_gtx_channel_[0123]_mid_*.txt" | wc -c) -eq 0
then
${XRAY_MERGEDB} gtx_channel_0_mid_left ${BUILD_DIR}/segbits_gtx_channelx.db
${XRAY_MERGEDB} gtx_channel_1_mid_left ${BUILD_DIR}/segbits_gtx_channelx.db
${XRAY_MERGEDB} gtx_channel_2_mid_left ${BUILD_DIR}/segbits_gtx_channelx.db
${XRAY_MERGEDB} gtx_channel_3_mid_left ${BUILD_DIR}/segbits_gtx_channelx.db
${XRAY_MERGEDB} mask_gtx_channel_0_mid_left ${BUILD_DIR}/mask_gtx_channelx.db
${XRAY_MERGEDB} mask_gtx_channel_1_mid_left ${BUILD_DIR}/mask_gtx_channelx.db
${XRAY_MERGEDB} mask_gtx_channel_2_mid_left ${BUILD_DIR}/mask_gtx_channelx.db
${XRAY_MERGEDB} mask_gtx_channel_3_mid_left ${BUILD_DIR}/mask_gtx_channelx.db
${XRAY_MERGEDB} gtx_channel_0_mid_right ${BUILD_DIR}/segbits_gtx_channelx.db
${XRAY_MERGEDB} gtx_channel_1_mid_right ${BUILD_DIR}/segbits_gtx_channelx.db
${XRAY_MERGEDB} gtx_channel_2_mid_right ${BUILD_DIR}/segbits_gtx_channelx.db
${XRAY_MERGEDB} gtx_channel_3_mid_right ${BUILD_DIR}/segbits_gtx_channelx.db
${XRAY_MERGEDB} mask_gtx_channel_0_mid_right ${BUILD_DIR}/mask_gtx_channelx.db
${XRAY_MERGEDB} mask_gtx_channel_1_mid_right ${BUILD_DIR}/mask_gtx_channelx.db
${XRAY_MERGEDB} mask_gtx_channel_2_mid_right ${BUILD_DIR}/mask_gtx_channelx.db
${XRAY_MERGEDB} mask_gtx_channel_3_mid_right ${BUILD_DIR}/mask_gtx_channelx.db
fi
if ! test $(find ${BUILD_DIR} -name "segdata_gtx_channel_[0123].txt" | wc -c) -eq 0
then
${XRAY_MERGEDB} gtx_channel_0 ${BUILD_DIR}/segbits_gtx_channelx.db
${XRAY_MERGEDB} gtx_channel_1 ${BUILD_DIR}/segbits_gtx_channelx.db
${XRAY_MERGEDB} gtx_channel_2 ${BUILD_DIR}/segbits_gtx_channelx.db
${XRAY_MERGEDB} gtx_channel_3 ${BUILD_DIR}/segbits_gtx_channelx.db
${XRAY_MERGEDB} mask_gtx_channel_0 ${BUILD_DIR}/mask_gtx_channelx.db
${XRAY_MERGEDB} mask_gtx_channel_1 ${BUILD_DIR}/mask_gtx_channelx.db
${XRAY_MERGEDB} mask_gtx_channel_2 ${BUILD_DIR}/mask_gtx_channelx.db
${XRAY_MERGEDB} mask_gtx_channel_3 ${BUILD_DIR}/mask_gtx_channelx.db
fi

167
fuzzers/064-gtx-channel-conf/top.py Normal file
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@ -0,0 +1,167 @@
#!/usr/bin/env python3
# -*- coding: utf-8 -*-
#
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
import json
import os
import random
from collections import namedtuple
random.seed(int(os.getenv("SEED"), 16))
from prjxray import util
from prjxray import verilog
from prjxray.lut_maker import LutMaker
from prjxray.db import Database
INT = "INT"
BIN = "BIN"
BOOL = "BOOL"
STR = "STR"
def gen_sites(site):
db = Database(util.get_db_root(), util.get_part())
grid = db.grid()
already_used = list()
for tile_name in sorted(grid.tiles()):
loc = grid.loc_of_tilename(tile_name)
gridinfo = grid.gridinfo_at_loc(loc)
if gridinfo.tile_type not in [
"GTX_CHANNEL_0",
"GTX_CHANNEL_1",
"GTX_CHANNEL_2",
"GTX_CHANNEL_3",
"GTX_CHANNEL_0_MID_LEFT",
"GTX_CHANNEL_1_MID_LEFT",
"GTX_CHANNEL_2_MID_LEFT",
"GTX_CHANNEL_3_MID_LEFT",
"GTX_CHANNEL_0_MID_RIGHT",
"GTX_CHANNEL_1_MID_RIGHT",
"GTX_CHANNEL_2_MID_RIGHT",
"GTX_CHANNEL_3_MID_RIGHT",
] or gridinfo.tile_type in already_used:
continue
else:
tile_type = gridinfo.tile_type
already_used.append(tile_type)
for site_name, site_type in gridinfo.sites.items():
if site_type != site:
continue
if "RIGHT" in tile_type and "X0" in site_name:
continue
if "LEFT" in tile_type and "X1" in site_name:
continue
yield tile_name, tile_type, site_name, site_type
def main():
print(
'''
module top(
input wire in,
output wire out
);
assign out = in;
''')
luts = LutMaker()
primitives_list = list()
for tile_name, tile_type, site_name, site_type in gen_sites(
"GTXE2_CHANNEL"):
params_list = list()
params_dict = dict()
params_dict["tile_type"] = tile_type
params = dict()
params['site'] = site_name
verilog_attr = ""
verilog_attr = "#("
fuz_dir = os.getenv("FUZDIR", None)
assert fuz_dir
with open(os.path.join(fuz_dir, "attrs.json"), "r") as attrs_file:
attrs = json.load(attrs_file)
in_use = bool(random.randint(0, 9))
params["IN_USE"] = in_use
if in_use:
for param, param_info in attrs.items():
param_type = param_info["type"]
param_values = param_info["values"]
param_digits = param_info["digits"]
if param_type == INT:
value = random.choice(param_values)
value_str = value
elif param_type == BIN:
value = random.randint(0, param_values[0])
value_str = "{digits}'b{value:0{digits}b}".format(
value=value, digits=param_digits)
elif param_type in [BOOL, STR]:
value = random.choice(param_values)
value_str = verilog.quote(value)
params[param] = value
verilog_attr += """
.{}({}),""".format(param, value_str)
verilog_ports = ""
for param in ["TXUSRCLK", "TXUSRCLK2", "TXPHDLYTSTCLK",
"RXUSRCLK", "RXUSRCLK2", "DRPCLK"]:
is_inverted = random.randint(0, 1)
params[param] = is_inverted
verilog_attr += """
.IS_{}_INVERTED({}),""".format(param, is_inverted)
verilog_ports += """
.{}({}),""".format(param, luts.get_next_output_net())
verilog_attr = verilog_attr.rstrip(",")
verilog_attr += "\n)"
print("(* KEEP, DONT_TOUCH, LOC=\"{}\" *)".format(site_name))
print(
"""GTXE2_CHANNEL {attrs} {site} (
{ports}
);
""".format(
attrs=verilog_attr,
site=tile_type.lower(),
ports=verilog_ports.rstrip(",")))
params_list.append(params)
params_dict["params"] = params_list
primitives_list.append(params_dict)
for l in luts.create_wires_and_luts():
print(l)
print("endmodule")
with open('params.json', 'w') as f:
json.dump(primitives_list, f, indent=2)
if __name__ == '__main__':
main()

4
fuzzers/Makefile
View File

@ -191,6 +191,10 @@ $(eval $(call fuzzer,065-gtp-common-pips,005-tilegrid,part))
$(eval $(call fuzzer,065b-gtp-common-pips,005-tilegrid,part))
$(eval $(call fuzzer,066-gtp-int-pips,005-tilegrid,all))
endif
ifeq ($(XRAY_DATABASE),kintex7)
$(eval $(call fuzzer,063-gtx-common-conf,005-tilegrid,part))
$(eval $(call fuzzer,064-gtx-channel-conf,005-tilegrid,part))
endif
endif
endif
$(eval $(call fuzzer,100-dsp-mskpat,005-tilegrid,all))

6
prjxray/segmaker.py
View File

@ -391,6 +391,12 @@ class Segmaker:
tile_type_norm = 'GTP_COMMON'
if 'GTP_INT_INTERFACE' in tile_type_norm:
tile_type_norm = 'GTP_INT_INTERFACE'
if 'GTX_CHANNEL' in tile_type_norm:
tile_type_norm = 'GTX_CHANNEL'
if 'GTX_COMMON' in tile_type_norm:
tile_type_norm = 'GTX_COMMON'
if 'GTX_INT_INTERFACE' in tile_type_norm:
tile_type_norm = 'GTX_INT_INTERFACE'
if tile_type_norm in ['LIOI', 'RIOI']:
tile_type_norm = 'IOI'

2
third_party/abseil-cpp vendored

@ -1 +1 @@
Subproject commit 3735766b3bd68522c8f291675df3fddb4bc3c70d
Subproject commit cc70e832b01f6c10ce9461c34f067ad91f8a2698

2
third_party/yosys vendored

@ -1 +1 @@
Subproject commit 3d35f367cfc2c11a477f665c2bbc26eadb6b59ab
Subproject commit 38f858374c0ed83a6ac3ea66715263af015d7974

54
utils/mergedb.sh
View File

@ -235,6 +235,60 @@ case "$1" in
gtp_int_interface)
cp "$2" "$tmp1" ;;
gtx_common)
cp "$2" "$tmp1" ;;
gtx_common_mid_left)
sed < "$2" > "$tmp1" -e 's/^GTX_COMMON\./GTX_COMMON_MID_LEFT./' ;;
gtx_common_mid_right)
sed < "$2" > "$tmp1" -e 's/^GTX_COMMON\./GTX_COMMON_MID_RIGHT./' ;;
gtx_channel_0)
sed < "$2" > "$tmp1" -e 's/^GTX_CHANNEL\./GTX_CHANNEL_0./' ;;
gtx_channel_1)
sed < "$2" > "$tmp1" -e 's/^GTX_CHANNEL\./GTX_CHANNEL_1./' ;;
gtx_channel_2)
sed < "$2" > "$tmp1" -e 's/^GTX_CHANNEL\./GTX_CHANNEL_2./' ;;
gtx_channel_3)
sed < "$2" > "$tmp1" -e 's/^GTX_CHANNEL\./GTX_CHANNEL_3./' ;;
gtx_channel_0_mid_left)
sed < "$2" > "$tmp1" -e 's/^GTX_CHANNEL\./GTX_CHANNEL_0_MID_LEFT./' ;;
gtx_channel_1_mid_left)
sed < "$2" > "$tmp1" -e 's/^GTX_CHANNEL\./GTX_CHANNEL_1_MID_LEFT./' ;;
gtx_channel_2_mid_left)
sed < "$2" > "$tmp1" -e 's/^GTX_CHANNEL\./GTX_CHANNEL_2_MID_LEFT./' ;;
gtx_channel_3_mid_left)
sed < "$2" > "$tmp1" -e 's/^GTX_CHANNEL\./GTX_CHANNEL_3_MID_LEFT./' ;;
gtx_channel_0_mid_right)
sed < "$2" > "$tmp1" -e 's/^GTX_CHANNEL\./GTX_CHANNEL_0_MID_RIGHT./' ;;
gtx_channel_1_mid_right)
sed < "$2" > "$tmp1" -e 's/^GTX_CHANNEL\./GTX_CHANNEL_1_MID_RIGHT./' ;;
gtx_channel_2_mid_right)
sed < "$2" > "$tmp1" -e 's/^GTX_CHANNEL\./GTX_CHANNEL_2_MID_RIGHT./' ;;
gtx_channel_3_mid_right)
sed < "$2" > "$tmp1" -e 's/^GTX_CHANNEL\./GTX_CHANNEL_3_MID_RIGHT./' ;;
gtx_int_interface_l)
sed < "$2" > "$tmp1" -e 's/^GTX_INT_INTERFACE\.GTXE2_INT/GTX_INT_INTERFACE_L\.GTXE2_INT_LEFT/' ;;
gtx_int_interface_r)
sed < "$2" > "$tmp1" -e 's/^GTX_INT_INTERFACE\.GTXE2_INT/GTX_INT_INTERFACE_R\.GTXE2_INT_R/' ;;
gtx_int_interface)
cp "$2" "$tmp1" ;;
mask_*)
db=$XRAY_DATABASE_DIR/$XRAY_DATABASE/$1.db
ismask=true