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Add Virtex-7 (xc7vx485t) family support 

Port prjxray to the Virtex-7 family, modelled on Kintex-7, targeting
xc7vx485tffg1761-2 (vc707). Non-breaking for the existing families.

Family registration:
- settings/virtex7.sh, settings/virtex7/devices.yaml
- Makefile: virtex7 in DATABASES/XRAY_PARTS + db-extras-virtex7 targets
- utils/update_parts.py, update_resources.py: virtex7 choice
- CI matrix (Pipeline.yml), Vivado edition (xilinx.sh), README

Architecture adaptations for the HP-bank-only VX part (verified non-breaking):
- update_resources.tcl: fall back to HP banks when no HR banks exist
- XRAY_IOSTANDARD env (default LVCMOS33; LVCMOS18 for virtex7), parameterised
  across the fuzzer generate.tcl files
- fuzzers: enable HP-bank (iob18/ioi18) + IOI/HCLK handling for virtex7;
  GTX skipped (ffg1761 bonds only ~7 of 14 GTX quads)
- 005-tilegrid: HP/HR bank tile handling; iob18_int INT offset 3->2;
  ioi18 AUTO_FRAME; cfg PDRC-2 DRC disable; add_tdb skips unsolved edge tiles;
  per-specimen retry for transient FlexLM SIGSEGV under concurrency
- per-family Vivado version gate (virtex7 -> v2020.1.1)
- XRAY_ROI and XRAY_ROI_GRID tuned to a compact CLBLL+CLBLM region

General fixes:
- tools/bitread.cc: fix use-after-free of the mmap'd bitstream (exposed by the
  larger Virtex-7 bitstream)
- utils/environment.python.sh: add repo root to PYTHONPATH (PEP 660 editable
  install doesn't expose the repo-root utils/ package)

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
This commit is contained in:
Dr Jonathan Richard Robert Kimmitt 2026-05-24 07:21:23 +01:00
parent 132342f7a2
commit 39f5de415d
63 changed files with 331 additions and 172 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
.github/scripts/xilinx.sh vendored
View File

@ -32,7 +32,7 @@ echo "----------------------------------------"
(
set -e
cd /opt
if [ x"$XRAY_SETTINGS" = x"kintex7" ]; then
if [ x"$XRAY_SETTINGS" = x"kintex7" ] || [ x"$XRAY_SETTINGS" = x"virtex7" ]; then
echo "Using Xilinx Vivado Design Edition for $XRAY_SETTINGS build."
echo
ln -s /mnt/aux/Xilinx-design /opt/Xilinx

2
.github/workflows/Pipeline.yml vendored
View File

@ -18,7 +18,7 @@ jobs:
strategy:
fail-fast: false
matrix:
family: ['artix7', 'zynq7', 'kintex7', 'spartan7']
family: ['artix7', 'zynq7', 'kintex7', 'spartan7', 'virtex7']
env:
GHA_SSH_TUNNEL_KEY: "${{ secrets.LICENSE_TUNNEL_KEY_DATA }}"

12
Makefile
View File

@ -136,7 +136,7 @@ check-license:
# Targets related to Project X-Ray databases
# ------------------------
DATABASES=artix7 kintex7 zynq7 spartan7
DATABASES=artix7 kintex7 zynq7 spartan7 virtex7
define database
@ -191,8 +191,9 @@ ARTIX_PARTS=artix7_50t artix7_200t
ZYNQ_PARTS=zynq7010
KINTEX_PARTS=kintex7_160t kintex7_325t kintex7_420t kintex7_480t
SPARTAN_PARTS=
VIRTEX_PARTS=
XRAY_PARTS=${ARTIX_PARTS} ${ZYNQ_PARTS} ${KINTEX_PARTS} ${SPARTAN_PARTS}
XRAY_PARTS=${ARTIX_PARTS} ${ZYNQ_PARTS} ${KINTEX_PARTS} ${SPARTAN_PARTS} ${VIRTEX_PARTS}
define multiple-parts
@ -245,6 +246,13 @@ db-extras-kintex7-roi: $(addprefix db-roi-only-,$(KINTEX_PARTS))
db-extras-kintex7-harness:
@true
db-extras-virtex7-parts: $(addprefix db-part-only-,$(VIRTEX_PARTS))
db-extras-virtex7-roi: $(addprefix db-roi-only-,$(VIRTEX_PARTS))
db-extras-virtex7-harness:
@true
db-extras-spartan7-parts:
@true

2
README.md
View File

@ -237,7 +237,7 @@ it.
Current the focus has been on the Artix-7 50T part. This structure is common
between all footprints of the 15T, 35T and 50T varieties.
We have also started experimenting with the Kintex-7 parts.
We have also started experimenting with the Kintex-7 and Virtex-7 parts.
The aim is to eventually document all parts in the Xilinx 7-series FPGAs but we
can not do this alone, **we need your help**!

8
fuzzers/001-part-yaml/generate.tcl
View File

@ -29,10 +29,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog ../../top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]

33
fuzzers/005-tilegrid/Makefile
View File

@ -6,13 +6,33 @@
#
# SPDX-License-Identifier: ISC
# I/O bank types present on the target device. Most 7-series parts have
# high-range (HR) banks; Virtex-7 "VX" parts are high-performance (HP) only.
HAS_HIGH_RANGE_BANKS ?= 1
HAS_HIGH_PERFORMANCE_BANKS ?= 0
ifeq (${XRAY_DATABASE}, virtex7)
HAS_HIGH_PERFORMANCE_BANKS = 1
# TODO: some virtex devices also have high range banks
HAS_HIGH_RANGE_BANKS = 0
endif
ifeq (${XRAY_DATABASE}, kintex7)
# xc7k420t/xc7k480t have no high performance banks
ifneq (${XRAY_FABRIC}, $(filter ${XRAY_FABRIC}, xc7k480t))
HAS_HIGH_PERFORMANCE_BANKS = 1
endif
endif
FUZDIR=$(shell pwd)
BUILD_FOLDER=build_${XRAY_PART}
BUILD_DIR=$(FUZDIR)/$(BUILD_FOLDER)
TILEGRID_TDB_DEPENDENCIES=
# High-range (HR) bank I/O tiles
ifeq (${HAS_HIGH_RANGE_BANKS}, 1)
TILEGRID_TDB_DEPENDENCIES += iob/$(BUILD_FOLDER)/segbits_tilegrid.tdb
TILEGRID_TDB_DEPENDENCIES += iob_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb
TILEGRID_TDB_DEPENDENCIES += ioi/$(BUILD_FOLDER)/segbits_tilegrid.tdb
endif
TILEGRID_TDB_DEPENDENCIES += monitor/$(BUILD_FOLDER)/segbits_tilegrid.tdb
TILEGRID_TDB_DEPENDENCIES += bram/$(BUILD_FOLDER)/segbits_tilegrid.tdb
TILEGRID_TDB_DEPENDENCIES += bram_block/$(BUILD_FOLDER)/segbits_tilegrid.tdb
@ -47,19 +67,24 @@ ifeq (${XRAY_DATABASE}, zynq7)
TILEGRID_TDB_DEPENDENCIES += ps7_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb
endif
# Kintex7 only fuzzers
ifeq (${XRAY_DATABASE}, kintex7)
# xc7k420t/xc7k480t have no high performance banks
ifneq (${XRAY_FABRIC}, $(filter ${XRAY_FABRIC}, xc7k480t))
# High-performance (HP) bank I/O fuzzers.
# Present on Kintex-7 (except xc7k480t) and Virtex-7 VX parts.
ifeq (${HAS_HIGH_PERFORMANCE_BANKS}, 1)
TILEGRID_TDB_DEPENDENCIES += iob18/$(BUILD_FOLDER)/segbits_tilegrid.tdb
TILEGRID_TDB_DEPENDENCIES += iob18_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb
TILEGRID_TDB_DEPENDENCIES += ioi18/$(BUILD_FOLDER)/segbits_tilegrid.tdb
# GTX transceiver fuzzers. Kintex-7 only: the xc7vx485t-ffg1761 package used for
# virtex7 bonds only ~7 of its 14 GTX quads, so the unbonded GTX_COMMON tiles
# cannot be placed/fuzzed. GTX is therefore skipped for virtex7.
ifneq (${XRAY_DATABASE}, virtex7)
TILEGRID_TDB_DEPENDENCIES += gtx_common/$(BUILD_FOLDER)/segbits_tilegrid.tdb
TILEGRID_TDB_DEPENDENCIES += gtx_channel/$(BUILD_FOLDER)/segbits_tilegrid.tdb
TILEGRID_TDB_DEPENDENCIES += gtx_int_interface/$(BUILD_FOLDER)/segbits_tilegrid.tdb
endif
endif
# These kintex parts give an empty design
ifeq (${XRAY_DATABASE}, kintex7)
ifneq (${XRAY_FABRIC}, $(filter ${XRAY_FABRIC}, xc7k160t xc7k325t xc7k480t))
TILEGRID_TDB_DEPENDENCIES += orphan_int_column/$(BUILD_FOLDER)/segbits_tilegrid.tdb
endif

15
fuzzers/005-tilegrid/add_tdb.py
View File

@ -47,7 +47,17 @@ def load_db(fn):
parts = l.split(' ')
tagstr = parts[0]
addrlist = parts[1:]
assert not any(s == '<const0>' for s in addrlist), (fn, l)
# segmatch emits a "<...>" marker (e.g. "<const0>", "<const1>",
# "<0 candidates>") instead of a frame address when it could not solve a
# tag's bit, i.e. the tile was not exercised/uniquely toggled by the
# design (e.g. unplaceable edge/special tiles such as BRAM_L_X114Y0 or
# CFG_CENTER_MID_X157Y84 on xc7vx485t-ffg1761). Such tiles can't have a
# base address solved here, so skip them with a warning rather than
# aborting the whole tilegrid aggregation.
if not addrlist or any(s.startswith('<') for s in addrlist):
print("WARNING: skipping unsolved tile (no address): "
"%s in %s" % (l, fn))
continue
check_frames(tagstr, addrlist)
# Take the first address in the list
frame, wordidx, bitidx = parse_addr(addrlist[0])
@ -79,7 +89,8 @@ def load_db(fn):
if not bitidx_up:
bitidx = 0
assert bitidx == 0, l
assert frame % 0x80 == 0, "Unaligned frame at 0x%08X" % frame
assert frame % 0x80 == 0, \
"Unaligned frame at 0x%08X in %s: %s" % (frame, fn, l)
yield (tile, frame, wordidx)

8
fuzzers/005-tilegrid/bram/generate.tcl
View File

@ -12,10 +12,10 @@ proc run {} {
read_verilog top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]

5
fuzzers/005-tilegrid/cfg/generate.tcl
View File

@ -6,4 +6,9 @@
#
# SPDX-License-Identifier: ISC
source "$::env(XRAY_DIR)/utils/utils.tcl"
# The cfg fuzzer sweeps BSCANE2 JTAG_CHAIN values to locate config bits; some
# values fail DRC PDRC-2 (BSCAN site vs JTAG_CHAIN mismatch) under newer Vivado,
# which aborts write_bitstream. We only need the resulting config bits, not a
# JTAG-valid design, so disable that DRC check for this fuzzer.
set_property IS_ENABLED 0 [get_drc_checks {PDRC-2}]
generate_top

8
fuzzers/005-tilegrid/clb/generate.tcl
View File

@ -12,10 +12,10 @@ proc run {} {
read_verilog top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]

4
fuzzers/005-tilegrid/clb_int/generate.tcl
View File

@ -12,8 +12,8 @@ proc run {} {
read_verilog top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]

6
fuzzers/005-tilegrid/fuzzaddr/common.mk
View File

@ -9,7 +9,13 @@ database: $(BUILD_DIR)/segbits_tilegrid.tdb
$(BUILD_DIR)/segbits_tilegrid.tdb: $(SPECIMENS_OK)
${XRAY_SEGMATCH} -o $(BUILD_DIR)/segbits_tilegrid.tdb $$(find $(BUILD_DIR) -name "segdata_tilegrid.txt")
# Retry a specimen up to 3 times: Vivado's FlexLM license manager can crash
# (SIGSEGV in libXil_lmgr11/freeaddrinfo) under concurrent license checkouts.
# Such crashes are transient and unrelated to the design, so retry before giving
# up. The success path is unchanged (first attempt short-circuits the chain).
$(SPECIMENS_OK):
GENERATE_ARGS=${GENERATE_ARGS} bash ../fuzzaddr/generate.sh $(subst /OK,,$@) || \
GENERATE_ARGS=${GENERATE_ARGS} bash ../fuzzaddr/generate.sh $(subst /OK,,$@) || \
GENERATE_ARGS=${GENERATE_ARGS} bash ../fuzzaddr/generate.sh $(subst /OK,,$@)
touch $@

7
fuzzers/005-tilegrid/iob18_int/top.py
View File

@ -49,12 +49,15 @@ def gen_sites():
sites, _ = zip(*sorted(zip(sites, sites_y), key=lambda x: x[1]))
# IOI/IDELAY-to-INT column spacing is 3 on Kintex-7 but 2 on Virtex-7
# (verified from the tilegrid for all LIOI/RIOI variants).
int_dx = 2 if os.environ.get('XRAY_DATABASE') == 'virtex7' else 3
if gridinfo.tile_type[0] == 'L':
int_grid_x = loc.grid_x + 3
int_grid_x = loc.grid_x + int_dx
pad_grid_x = loc.grid_x - 1
int_tile_type = 'INT_L'
else:
int_grid_x = loc.grid_x - 3
int_grid_x = loc.grid_x - int_dx
pad_grid_x = loc.grid_x + 1
int_tile_type = 'INT_R'

8
fuzzers/005-tilegrid/ioi18/Makefile
View File

@ -6,5 +6,13 @@
#
# SPDX-License-Identifier: ISC
N ?= 24
# On Virtex-7 a few IOI18 tiles (e.g. LIOI_X82Y10, RIOI_X311Y10) place the
# toggled bit one frame above the Kintex-7 offset, so a fixed DFRAME mis-aligns
# their base address. Use AUTO_FRAME (round the base down to the 0x80 boundary)
# for virtex7 instead; it is equivalent to DFRAME:20 for the aligned tiles.
ifeq ($(XRAY_DATABASE),virtex7)
GENERATE_ARGS?="--oneval 1 --design params.csv --auto-frame --dword 3"
else
GENERATE_ARGS?="--oneval 1 --design params.csv --dframe 20 --dword 3"
endif
include ../fuzzaddr/common.mk

8
fuzzers/005-tilegrid/mmcm/generate.tcl
View File

@ -12,10 +12,10 @@ proc run {} {
read_verilog top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]

8
fuzzers/005-tilegrid/monitor/generate.tcl
View File

@ -12,10 +12,10 @@ proc run {} {
read_verilog top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]

8
fuzzers/005-tilegrid/ps7_int/generate.tcl
View File

@ -12,10 +12,10 @@ proc run {} {
read_verilog top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]

22
fuzzers/005-tilegrid/util.tcl
View File

@ -80,12 +80,16 @@ proc loc_dut_col_sites { dut_columns cellpre cellpost } {
proc make_io_pad_sites {} {
# get all possible IOB pins
set io_pad_sites [dict create]
foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] {
set site [get_sites -of_objects $pad]
if {[llength $site] == 0} {
continue
}
if [string match IOB33* [get_property SITE_TYPE $site]] {
# High-range (HR) banks expose IOB33 sites; high-performance (HP) banks
# (e.g. Virtex-7 "VX" parts) expose IOB18 sites.
set site_type [get_property SITE_TYPE $site]
if {[string match IOB33* $site_type] || [string match IOB18* $site_type]} {
dict append io_pad_sites $site $pad
}
}
@ -114,10 +118,10 @@ proc make_iob_sites {} {
}
proc assign_iobs_old {} {
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
}
proc assign_iobs {} {
@ -129,9 +133,9 @@ proc assign_iobs {} {
# Basic pins
# XXX: not all pads are valid, but seems to be working for now
# Maybe better to set to XRAY_PIN_* and take out of the list?
set_property -dict "PACKAGE_PIN [lindex $iopad 0] IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN [lindex $iopad 1] IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN [lindex $iopad 2] IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN [lindex $iopad 0] IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN [lindex $iopad 1] IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
set_property -dict "PACKAGE_PIN [lindex $iopad 2] IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
# din bus
set fixed_pins 3
@ -139,7 +143,7 @@ proc assign_iobs {} {
for {set i 0} {$i < [llength $iports]} {incr i} {
set pad [lindex $iopad [expr $i+$fixed_pins]]
set port [lindex $iports $i]
set_property -dict "PACKAGE_PIN $pad IOSTANDARD LVCMOS33" $port
set_property -dict "PACKAGE_PIN $pad IOSTANDARD $::env(XRAY_IOSTANDARD)" $port
}
}

4
fuzzers/007-timing/bel/runme.tcl
View File

@ -13,8 +13,8 @@ proc create_design {} {
read_verilog $::env(SRC_DIR)/top.v
synth_design -top top -flatten_hierarchy none
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]

4
fuzzers/007-timing/routing-bels/runme.tcl
View File

@ -13,8 +13,8 @@ proc create_design {} {
read_verilog $::env(SRC_DIR)/top.v
synth_design -top top -flatten_hierarchy none
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]

8
fuzzers/010-clb-lutinit/generate.tcl
View File

@ -10,10 +10,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog ../../top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]

8
fuzzers/011-clb-ffconfig/generate.tcl
View File

@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
create_pblock roi

8
fuzzers/012-clb-n5ffmux/generate.tcl
View File

@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
create_pblock roi

8
fuzzers/013-clb-ncy0/generate.tcl
View File

@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
create_pblock roi

8
fuzzers/014-clb-ffsrcemux/generate.tcl
View File

@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
create_pblock roi

8
fuzzers/015-clb-nffmux/generate.tcl
View File

@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
create_pblock roi

8
fuzzers/016-clb-noutmux/generate.tcl
View File

@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
create_pblock roi

8
fuzzers/017-clb-precyinit/generate.tcl
View File

@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
create_pblock roi

8
fuzzers/018-clb-ram/generate.tcl
View File

@ -10,10 +10,10 @@ proc build {} {
read_verilog top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
create_pblock roi

8
fuzzers/019-clb-ndi1mux/generate.tcl
View File

@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
create_pblock roi

8
fuzzers/025-bram-config/generate.tcl
View File

@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
create_pblock roi

8
fuzzers/025-bram-config/minitest/runme.tcl
View File

@ -10,10 +10,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog $::env(TOP_V)
synth_design -top top -flatten_hierarchy none -verilog_define ROI=$::env(PROJECT)
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
create_pblock roi

8
fuzzers/026-bram-data/minitest/runme.tcl
View File

@ -10,10 +10,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog $::env(TOP_V)
synth_design -top top -flatten_hierarchy none -verilog_define ROI=$::env(PROJECT)
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
create_pblock roi

8
fuzzers/030-iob/minitest/runme.tcl
View File

@ -10,10 +10,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog $::env(TOP_V)
synth_design -top top -flatten_hierarchy none -verilog_define ROI=$::env(PROJECT)
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
# set_property roi/dut

10
fuzzers/030-iob/minitest/template.tcl
View File

@ -11,10 +11,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog $::env(TOP_V)
synth_design -top top -flatten_hierarchy none
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
@ -27,6 +27,6 @@ route_design
write_checkpoint -force design.dcp
# set port [create_port -direction OUT myport]
# set_property -dict "PACKAGE_PIN D19 IOSTANDARD LVCMOS33" $port
# set_property -dict "PACKAGE_PIN D19 IOSTANDARD $::env(XRAY_IOSTANDARD)" $port
# set_property PULLTYPE PULLUP $port
# set_property PULLTYPE PULLDOWN $port

8
fuzzers/033-mon-xadc/generate.tcl
View File

@ -9,10 +9,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
create_pblock roi

2
fuzzers/035-iob-ilogic/Makefile
View File

@ -39,7 +39,7 @@ pushdb: build/segbits_rioi.db
${XRAY_MERGEDB} mask_rioi3 build/mask_xioi3.db
${XRAY_MERGEDB} mask_rioi3_tbytesrc build/mask_xioi3.db
${XRAY_MERGEDB} mask_rioi3_tbyteterm build/mask_xioi3.db
ifeq ($(XRAY_DATABASE),kintex7)
ifneq (,$(filter $(XRAY_DATABASE),kintex7 virtex7))
${XRAY_MERGEDB} rioi build/segbits_rioi.db
${XRAY_MERGEDB} rioi_tbytesrc build/segbits_rioi.db
${XRAY_MERGEDB} rioi_tbyteterm build/segbits_rioi.db

2
fuzzers/035b-iob-iserdes/Makefile
View File

@ -40,7 +40,7 @@ pushdb: build/segbits_rioi.db
${XRAY_MERGEDB} mask_rioi3 build/mask_xioi3.db
${XRAY_MERGEDB} mask_rioi3_tbytesrc build/mask_xioi3.db
${XRAY_MERGEDB} mask_rioi3_tbyteterm build/mask_xioi3.db
ifeq ($(XRAY_DATABASE),kintex7)
ifneq (,$(filter $(XRAY_DATABASE),kintex7 virtex7))
${XRAY_MERGEDB} rioi build/segbits_rioi.db
${XRAY_MERGEDB} rioi_tbytesrc build/segbits_rioi.db
${XRAY_MERGEDB} rioi_tbyteterm build/segbits_rioi.db

8
fuzzers/038-cfg/generate.tcl
View File

@ -10,10 +10,10 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
create_pblock roi

6
fuzzers/039-hclk-config/Makefile
View File

@ -9,7 +9,7 @@ N ?= 50
include ../fuzzer.mk
ifeq ($(XRAY_DATABASE),kintex7)
ifneq (,$(filter $(XRAY_DATABASE),kintex7 virtex7))
database: build/segbits_hclk_ioi.db
else
database: build/segbits_hclk_ioi3.db
@ -28,7 +28,7 @@ build/segbits_hclk_ioi3.db: build/segbits_hclk_ioi3.rdb
# The fuzzer results for the high performance banks
# are identical, so just copy those
ifeq ($(XRAY_DATABASE),kintex7)
ifneq (,$(filter $(XRAY_DATABASE),kintex7 virtex7))
build/segbits_hclk_ioi.db: build/segbits_hclk_ioi3.db
sed -e 's/HCLK_IOI3/HCLK_IOI/g' $< > $@
cp build/mask_hclk_ioi3.db build/mask_hclk_ioi.db
@ -37,7 +37,7 @@ endif
pushdb: database
${XRAY_MERGEDB} hclk_ioi3 build/segbits_hclk_ioi3.db
${XRAY_MERGEDB} mask_hclk_ioi3 build/mask_hclk_ioi3.db
ifeq ($(XRAY_DATABASE),kintex7)
ifneq (,$(filter $(XRAY_DATABASE),kintex7 virtex7))
${XRAY_MERGEDB} hclk_ioi build/segbits_hclk_ioi.db
${XRAY_MERGEDB} mask_hclk_ioi build/mask_hclk_ioi.db
endif

8
fuzzers/050-pip-seed/generate.tcl
View File

@ -15,10 +15,10 @@ read_verilog $::env(FUZDIR)/picorv32.v
puts "FUZ([pwd]): Synth design"
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports din]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports dout]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports din]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports dout]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
create_pblock roi
add_cells_to_pblock [get_pblocks roi] [get_cells roi]

8
fuzzers/051-pip-imuxlout-bypalts/generate.tcl
View File

@ -13,10 +13,10 @@ read_verilog $::env(FUZDIR)/top.v
read_verilog $::env(FUZDIR)/picorv32.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports din]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports dout]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports din]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports dout]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

4
fuzzers/052-pip-clkin/generate.tcl
View File

@ -43,8 +43,8 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog $::env(FUZDIR)/top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports o]
create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

4
fuzzers/053-pip-ctrlin/generate.tcl
View File

@ -12,8 +12,8 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog $::env(FUZDIR)/top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports o]
create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

4
fuzzers/054-pip-fan-alt/generate.tcl
View File

@ -13,8 +13,8 @@ proc build_basic {} {
read_verilog $::env(FUZDIR)/top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports o]
create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

4
fuzzers/055-pip-gnd/generate.tcl
View File

@ -12,8 +12,8 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog $::env(FUZDIR)/top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports o]
create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

4
fuzzers/056-pip-rem/generate.tcl
View File

@ -25,8 +25,8 @@ proc build_basic {} {
read_verilog $::env(FUZDIR)/top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports o]
create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

4
fuzzers/057-pip-bi/bipiplist.tcl
View File

@ -10,8 +10,8 @@ create_project -force -part $::env(XRAY_PART) bipiplist bipiplist
read_verilog $::env(XRAY_FUZZERS_DIR)/piplist/piplist.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports o]
create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

4
fuzzers/057-pip-bi/generate.tcl
View File

@ -10,8 +10,8 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog $::env(FUZDIR)/top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports o]
create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

4
fuzzers/058-pip-hclk/generate.tcl
View File

@ -12,8 +12,8 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog $::env(FUZDIR)/top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports o]
create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

4
fuzzers/059-pip-byp-bounce/generate.tcl
View File

@ -13,8 +13,8 @@ proc build_basic {} {
read_verilog $::env(FUZDIR)/top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports o]
create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

4
fuzzers/071-ppips/generate.tcl
View File

@ -10,8 +10,8 @@ create_project -force -part $::env(XRAY_PART) design design
read_verilog $::env(FUZDIR)/top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports a]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports y]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports a]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports y]
create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

8
fuzzers/100-dsp-mskpat/generate.tcl
View File

@ -12,10 +12,10 @@ proc run {} {
read_verilog top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports stb]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]

8
fuzzers/Makefile
View File

@ -84,7 +84,7 @@ fuzzer_$(1): fuzzer_ok/fuzzer_$(1)_$(XRAY_PART).ok
endef
ifeq ($(XRAY_DATABASE),kintex7)
ifneq (,$(filter $(XRAY_DATABASE),kintex7 virtex7))
HAS_HIGH_PERFORMANCE_BANKS=1
else
HAS_HIGH_PERFORMANCE_BANKS=0
@ -99,7 +99,7 @@ all:: 005-tilegrid/run.ok
touch 005-tilegrid/run.ok
endif
ifneq ($(XRAY_DATABASE),kintex7)
ifeq (,$(filter $(XRAY_DATABASE),kintex7 virtex7))
$(eval $(call fuzzer,007-timing,005-tilegrid,all))
endif
$(eval $(call fuzzer,010-clb-lutinit,005-tilegrid,all))
@ -124,7 +124,7 @@ endif
$(eval $(call fuzzer,031-cmt-mmcm,005-tilegrid,all))
$(eval $(call fuzzer,032-cmt-pll,005-tilegrid,all))
$(eval $(call fuzzer,034-cmt-pll-pips,005-tilegrid 071-ppips,all))
ifneq ($(XRAY_DATABASE),kintex7)
ifeq (,$(filter $(XRAY_DATABASE),kintex7 virtex7))
# FIXME: 034b fuzzer is generating conflicting bits around the FREQ_BB[N] bits.
# The fuzzer can be re-enabled once the conflicting bits are not generated anymore
$(eval $(call fuzzer,034b-cmt-mmcm-pips,005-tilegrid 071-ppips,all))
@ -191,6 +191,8 @@ $(eval $(call fuzzer,065-gtp-common-pips,005-tilegrid,part))
$(eval $(call fuzzer,065b-gtp-common-pips,005-tilegrid,part))
$(eval $(call fuzzer,066-gtp-int-pips,005-tilegrid,all))
endif
# GTX transceiver config fuzzers. Kintex-7 only: the virtex7 package
# (xc7vx485t-ffg1761) bonds only ~7 of 14 GTX quads, so GTX is skipped there.
ifeq ($(XRAY_DATABASE),kintex7)
$(eval $(call fuzzer,063-gtx-common-conf,005-tilegrid,part))
$(eval $(call fuzzer,064-gtx-channel-conf,005-tilegrid,part))

4
fuzzers/piplist/piplist.tcl
View File

@ -13,8 +13,8 @@ proc build_project {} {
read_verilog $::env(XRAY_FUZZERS_DIR)/piplist/piplist.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD $::env(XRAY_IOSTANDARD)" [get_ports o]
create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

62
settings/virtex7.sh Normal file
View File

@ -0,0 +1,62 @@
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
export XRAY_DATABASE="virtex7"
export XRAY_PART="xc7vx485tffg1761-2"
export XRAY_ROI_FRAMES="0x00000000:0xffffffff"
# Virtex-7 "VX" parts are high-performance-bank only: their general purpose I/O
# cannot drive 3.3V. LVCMOS18 is valid on both HP and HR banks, so it is used as
# the default I/O standard for all virtex7 fuzzers (see ${XRAY_IOSTANDARD}).
export XRAY_IOSTANDARD="LVCMOS18"
# Virtex-7 synthesis only checks out a license under Vivado 2020.1 on this setup
# (2017.2's license manager refuses xc7vx485t). Override the install path and the
# version gate for this family. Both are overridable from the environment.
export XRAY_VIVADO_SETTINGS="${XRAY_VIVADO_SETTINGS:-/NFS/apps/Xilinx/Vivado/2020.1/settings64.sh}"
export XRAY_VIVADO_VERSION="${XRAY_VIVADO_VERSION:-v2020.1.1}"
# NOTE: The tilegrid/ROI coordinates below are device-specific (xc7vx485t) and
# MUST be verified against Vivado before running the full database build. They
# are seeded from the equivalently-sized kintex7 xc7k325t layout as a starting
# point. To regenerate them for this part, inspect the part in Vivado (or the
# output of fuzzers/005-tilegrid) and update the SLICE/DSP48/RAMB/IOB extents.
export XRAY_ROI_TILEGRID="SLICE_X0Y0:SLICE_X153Y349 DSP48_X0Y0:DSP48_X5Y139 RAMB18_X0Y0:RAMB18_X5Y139 RAMB36_X0Y0:RAMB36_X4Y69"
export XRAY_EXCLUDE_ROI_TILEGRID=""
# The IOI tiles whose frame address sits one frame higher than the rest
# (handled specially by 005-tilegrid/generate_full.py propagate_IOI_Y9).
# On Virtex-7 these are the HP IOI (LIOI/RIOI) tiles at Y10, verified from the
# generated tilegrid (cf. Kintex-7's LIOI3_X0Y9).
export XRAY_IOI3_TILES="LIOI_X82Y10 RIOI_X311Y10"
# Compact fuzzing region for the placement-based main fuzzers (010-100). The
# SLICE block must densely cover adjacent CLBLL and CLBLM columns: with only the
# CLBLM columns here (X2,3,6,7,10,11 -> 6 cols x 50 x 4 = 1200 LUTs) the 2000-LUT
# fuzzer design cannot fit, so the placer is forced to also use the CLBLL columns
# (X0,1,4,5,8,9). A too-large region lets the placer pack everything into CLBLM
# (which produced no CLBLL segdata -> segmatch error). DSP48/RAMB/IOB ranges
# cover those resources for the DSP/BRAM/IOB fuzzers.
export XRAY_ROI="SLICE_X0Y0:SLICE_X11Y49 DSP48_X0Y0:DSP48_X5Y39 RAMB18_X0Y0:RAMB18_X5Y39 RAMB36_X0Y0:RAMB36_X5Y19 IOB_X0Y0:IOB_X0Y49"
# Grid (tile) coordinates of the same physical region as XRAY_ROI above, used by
# fuzzers that go through util.get_roi()/roi_xy() (e.g. 018-clb-ram). On
# xc7vx485t the XRAY_ROI SLICE block (X0-11, Y0-49) maps to grid_x 5-19,
# grid_y 313-363; bounds are exclusive on the high end.
export XRAY_ROI_GRID_X1="5"
export XRAY_ROI_GRID_X2="20"
export XRAY_ROI_GRID_Y1="313"
export XRAY_ROI_GRID_Y2="364"
source $(dirname ${BASH_SOURCE[0]})/../utils/environment.sh
env=$(python3 ${XRAY_UTILS_DIR}/create_environment.py)
ENV_RET=$?
if [[ $ENV_RET != 0 ]] ; then
return $ENV_RET
fi
eval $env

3
settings/virtex7/devices.yaml Normal file
View File

@ -0,0 +1,3 @@
# device to fabric mapping
"xc7vx485t":
fabric: "xc7vx485t"

9
tools/bitread.cc
View File

@ -319,11 +319,15 @@ int main(int argc, char** argv) {
frame_range_end = strtol(p.second.c_str(), nullptr, 0) + 1;
}
// NOTE: in_file and t must outlive their use through in_bytes below.
// in_bytes is only a view; keeping its backing storage at function scope
// avoids a use-after-free (munmap / vector free) before BitReader runs.
absl::Span<uint8_t> in_bytes;
std::unique_ptr<prjxray::MemoryMappedFile> in_file;
std::vector<uint8_t> t;
if (argc == 2) {
auto in_file_name = argv[1];
auto in_file =
prjxray::MemoryMappedFile::InitWithFile(in_file_name);
in_file = prjxray::MemoryMappedFile::InitWithFile(in_file_name);
if (!in_file) {
std::cerr << "Can't open input file '" << in_file_name
<< "' for reading!" << std::endl;
@ -336,7 +340,6 @@ int main(int argc, char** argv) {
in_bytes = absl::Span<uint8_t>(
static_cast<uint8_t*>(in_file->data()), in_file->size());
} else {
std::vector<uint8_t> t;
while (1) {
int c = getchar();
if (c == EOF)

6
utils/environment.python.sh
View File

@ -9,3 +9,9 @@
# Suppress the following warnings;
# - env/lib/python3.7/distutils/__init__.py:4: DeprecationWarning: the imp module is deprecated in favour of importlib; see the module's documentation for alternative uses
export PYTHONWARNINGS=ignore::DeprecationWarning:distutils
# Make the prjxray repo root importable so the fuzzers can `import utils.*` and
# `import prjxray.*`. A modern (PEP 660) editable install only exposes the
# `prjxray` package, not the repo-root `utils/` directory, so add the root here.
XRAY_PYTHON_ROOT="${XRAY_DIR:-$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)}"
export PYTHONPATH="${XRAY_PYTHON_ROOT}${PYTHONPATH:+:${PYTHONPATH}}"

15
utils/environment.sh
View File

@ -30,6 +30,11 @@ source $XRAY_UTILS_DIR/environment.python.sh
# Set environment to default output and overwrite localisation settings
export LC_ALL=C
# Default I/O standard used by the fuzzers' generic clk/data ports. Parts whose
# general purpose I/O cannot drive 3.3V (e.g. Virtex-7 "VX" high-performance
# banks) override this in their settings/<family>.sh (see settings/virtex7.sh).
export XRAY_IOSTANDARD="${XRAY_IOSTANDARD:-LVCMOS33}"
# tools
export XRAY_GENHEADER="${XRAY_UTILS_DIR}/genheader.sh"
export XRAY_BITREAD="${XRAY_TOOLS_DIR}/bitread --part_file ${XRAY_PART_YAML}"
@ -48,9 +53,13 @@ export XRAY_VIVADO="${XRAY_UTILS_DIR}/vivado.sh"
# Verify an approved version is in use
export XRAY_VIVADO_SETTINGS="${XRAY_VIVADO_SETTINGS:-/opt/Xilinx/Vivado/2017.2/settings64.sh}"
# Vivado v2017.2 (64-bit)
if [ "$(${XRAY_VIVADO} -h |grep Vivado |cut -d\ -f 2)" != "v2017.2" ] ; then
echo "Requires Vivado 2017.2. See https://github.com/SymbiFlow/prjxray/issues/14"
# Most families require Vivado v2017.2 (see prjxray issue #14). A family may
# override XRAY_VIVADO_VERSION (and XRAY_VIVADO_SETTINGS) in its settings file:
# e.g. virtex7 needs v2020.1 because only that version checks out a Virtex-7
# synthesis license on this setup (2017.2 is refused by the license manager).
export XRAY_VIVADO_VERSION="${XRAY_VIVADO_VERSION:-v2017.2}"
if [ "$(${XRAY_VIVADO} -h |grep Vivado |cut -d\ -f 2)" != "${XRAY_VIVADO_VERSION}" ] ; then
echo "Requires Vivado ${XRAY_VIVADO_VERSION}. See https://github.com/SymbiFlow/prjxray/issues/14"
# Can't exit since sourced script
# Trash a key environment variable to preclude use
export XRAY_DIR="/bad/vivado/version"

2
utils/update_parts.py
View File

@ -30,7 +30,7 @@ def main():
parser.add_argument(
'family',
help="Name of the device family.",
choices=['artix7', 'kintex7', 'zynq7', 'spartan7'])
choices=['artix7', 'kintex7', 'virtex7', 'zynq7', 'spartan7'])
util.db_root_arg(parser)
args = parser.parse_args()

2
utils/update_resources.py
View File

@ -30,7 +30,7 @@ def main():
parser.add_argument(
'family',
help="Name of the device family.",
choices=['artix7', 'kintex7', 'zynq7', 'spartan7'])
choices=['artix7', 'kintex7', 'virtex7', 'zynq7', 'spartan7'])
db_root_arg(parser)
args = parser.parse_args()

6
utils/update_resources.tcl
View File

@ -13,8 +13,12 @@ link_design -part $::env(XRAY_PART)
# one pin -> 0
set clk_pins [get_package_pins -filter "IS_CLK_CAPABLE"]
# three pins -> 1, 2, 3 on HR banks only
# three pins -> 1, 2, 3 on HR banks. High-performance-bank-only parts (e.g.
# Virtex-7 "VX" devices) have no high-range banks, so fall back to HP banks.
set banks [get_iobanks -filter "BANK_TYPE==BT_HIGH_RANGE"]
if {$banks == ""} {
set banks [get_iobanks -filter "BANK_TYPE==BT_HIGH_PERFORMANCE"]
}
set data_pins ""
foreach bank [split $banks " "] {