luke
/
prjxray
mirror of https://github.com/openXC7/prjxray.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
prjxray/minitests/litex/src.yosys
History
Maciej Kurc 01f77fd2b2 Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 		2019-06-13 15:58:06 +02:00
..
Makefile Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 2019-06-13 15:58:06 +02:00
VexRiscv.v Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 2019-06-13 15:58:06 +02:00
mem.init Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 2019-06-13 15:58:06 +02:00
mem_1.init Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 2019-06-13 15:58:06 +02:00
synth.ys Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 2019-06-13 15:58:06 +02:00
top.tcl Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 2019-06-13 15:58:06 +02:00
top.v Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 2019-06-13 15:58:06 +02:00
top.xdc Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 2019-06-13 15:58:06 +02:00