Maciej Kurc 01f77fd2b2 Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) ... Signed-off-by: Maciej Kurc <mkurc@antmicro.com>		2019-06-13 15:58:06 +02:00
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clb-bused	minitest: clean up folders	2019-01-07 23:31:44 +01:00
clb-carry_cin_cyinit	minitest: clean up folders	2019-01-07 23:31:44 +01:00
clb-configs	minitest: clean up folders	2019-01-07 23:31:44 +01:00
clb-muxf8	minitest: clean up folders	2019-01-07 23:31:44 +01:00
clkbuf	introduce vivado wrapper	2018-12-28 19:05:49 +01:00
eccbits	introduce vivado wrapper	2018-12-28 19:05:49 +01:00
fixedpnr	introduce vivado wrapper	2018-12-28 19:05:49 +01:00
litex	Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board)	2019-06-13 15:58:06 +02:00
lvb_long_mux	introduce vivado wrapper	2018-12-28 19:05:49 +01:00
nodes_wires_list	tcl: reformat existing code	2018-12-05 16:52:56 -08:00
partial_reconfig_flow	introduce vivado wrapper	2018-12-28 19:05:49 +01:00
picorv32-v	introduce vivado wrapper	2018-12-28 19:05:49 +01:00
picorv32-y	introduce vivado wrapper	2018-12-28 19:05:49 +01:00
pip-switchboxes	minitest: clean up folders	2019-01-07 23:31:44 +01:00
roi_harness	Add make targets to build additional outputs from each database.	2019-04-10 11:55:39 -07:00
tiles_wires_pips	introduce vivado wrapper	2018-12-28 19:05:49 +01:00
timing	Add README for timing minitest.	2019-05-29 15:05:18 -07:00
util	introduce vivado wrapper	2018-12-28 19:05:49 +01:00