luke
/
prjxray
mirror of https://github.com/openXC7/prjxray.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
prjxray/minitests/litex
History
Maciej Kurc 01f77fd2b2 Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 		2019-06-13 15:58:06 +02:00
..
src.vivado Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 2019-06-13 15:58:06 +02:00
src.yosys Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 2019-06-13 15:58:06 +02:00
.gitignore Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 2019-06-13 15:58:06 +02:00