f92fb52576
Merge branch 'master' into add_pll_interconnect_fuzzer
2019-07-08 11:22:49 -07:00
3d1fade706
Change error output to stderr.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-07-08 11:21:43 -07:00
948a3b21cc
Merge pull request #915 from antmicro/913_hclk_ioi_baseaddress
...
Calculate base addresses for HCLK_IOI3 tiles.
2019-07-04 23:32:20 +02:00
b77c47b155
Fixes for zynq7 and PLL fuzzing.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-07-03 13:19:03 -07:00
a7f5a305b9
Add 034 to fuzzer makefile.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-07-03 13:19:03 -07:00
2728b781d1
Limit pips to the ones we care about.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-07-03 13:19:03 -07:00
30648d554a
Complete initial PLL fuzzer.
...
This solves for all unknown bits, but results in a large "IN_USE"
feature for apparently constant bits.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-07-03 13:18:58 -07:00
bc822f8337
Update 032 with some fixes found during interconnect fuzzing.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-07-03 13:18:58 -07:00
68ad409d23
Refactor PLL segbits to leverage known register file.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-07-03 13:18:53 -07:00
219f0f0175
Merge pull request #899 from antmicro/routing-bels
...
Fuzzers: 007-timing: add routing BELs fuzzer
2019-07-03 05:36:28 +02:00
78346781ce
fuzzers: 007: fix Makefile targets definitions
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2019-07-02 19:04:10 +02:00
28d961a650
fuzzers: routing BELs: group timings by interconn oputput
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2019-07-02 13:08:14 +02:00
e096d9c172
005-tilegrid: Add HCLK_IOI base addresses calculation
...
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2019-07-01 08:58:45 +02:00
fac9212751
third-party: bump python-sdf-timing submodule
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2019-06-29 14:12:08 +02:00
6cc614f1fb
fuzzers: 007: fix BEL fuzzer Makefile
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2019-06-29 14:12:08 +02:00
9658653da8
fuzzers: bel: emit routing bels timings as INTERCONN
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2019-06-29 14:12:08 +02:00
eaa8e50fe1
utils: sdfmerge: use ns timescale
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2019-06-29 14:12:08 +02:00
03252bc46f
fuzzers: 007: add gitignores
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2019-06-29 14:12:08 +02:00
a99e26bbd4
fuzzers: 007: make both bels and routing-bels
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2019-06-29 14:12:08 +02:00
cb3a2b42d7
fuzzers: 007: produce sdf files for routing bels
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2019-06-29 14:12:08 +02:00
b0cc42353a
third-party: bump python-sdf-timing submodule
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2019-06-29 14:12:08 +02:00
2c1d4342b7
fuzzers: 007: format python
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2019-06-29 14:12:08 +02:00
94f3baf157
third-party: bump python-sdf-timing submodule
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2019-06-29 14:12:08 +02:00
ec28d95604
fuzzers: 007: add routing BELs fuzzer
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2019-06-29 14:12:08 +02:00
f357aa06c1
Merge pull request #896 from antmicro/895_falsely_ignored_pips
...
Fix problem with falsely ignored PIPs
2019-06-28 08:55:14 -07:00
36e9120fc7
Fix problem with falsely ignored PIPs
...
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2019-06-27 08:01:01 +02:00
5fb2153a0a
Merge pull request #889 from antmicro/875_44_clk_bufg_pips
...
Fix duplicate tag in 044-clk-bufg-pips
2019-06-26 08:31:58 -07:00
38087b313b
Merge pull request #909 from litghost/slow_harness
...
Add ROI base file that adds a clock divider.
2019-06-26 08:19:53 -07:00
ca6bbee193
Merge pull request #908 from antmicro/fix-bram-timing-fuzzer
...
007-timing: added missing aliases for bram timing
2019-06-26 13:00:20 +02:00
e697365c7d
Add ROI base file that adds a clock divider.
...
This cannot be used for an ROI harness until
https://github.com/SymbiFlow/prjxray/issues/891 is complete.
Command to build new harness
```
XRAY_ROIV=../roi_base_div2.v make
```
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-06-25 12:05:44 -07:00
b8f64484da
Merge pull request #901 from antmicro/bel-fuzzer-stabilization
...
BEL fuzzer stabilization
2019-06-25 10:43:12 -07:00
73a6bc5d77
Merge pull request #906 from antmicro/tilegrid_ioi
...
Calculate base addresses for IOI tiles
2019-06-25 10:20:06 -07:00
00c4672c12
fuzzers: Add 046-clk-bufg-mixed-pips fuzzer
...
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2019-06-25 18:52:00 +02:00
19ed8c5af8
044-clk-bufg-pips: Exclude CK_BUFG_(BOT|TOP)_R_CK_MUXED from todo list
...
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2019-06-25 18:52:00 +02:00
87a51b96bb
Merge pull request #883 from antmicro/litex_minitest2
...
Litex SoC minitest (sources)
2019-06-25 09:28:26 -07:00
5845918552
Merge pull request #838 from antmicro/041_clk_hrow_pips_timeout
...
041-clk-hrow-pips: Fix timeout and bit collision problems
2019-06-25 09:18:44 -07:00
bc3fcb0db2
Merge pull request #900 from litghost/extend_zero_db_features
...
Add support to zero db to support simple groups.
2019-06-25 09:02:10 -07:00
6476443a52
007-timing: added missing aliases for bram timing
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-06-25 17:13:44 +02:00
86164fdc18
005-tilegrid: propagate IOI SING and Y9 tiles
...
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2019-06-25 12:12:37 +02:00
9fb26b6915
005-tilegrid: calculate IOI base address
...
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2019-06-25 11:32:32 +02:00
68c810ce3b
Added source files dependencies to Makefiles
...
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-06-25 10:14:20 +02:00
f6450b72b8
fuzzers: 007: bel: sort timing keywords
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2019-06-21 17:28:48 +02:00
a560cc3500
fuzzers: 007: bel: do not copy timing data
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2019-06-21 17:28:05 +02:00
7821cb743c
fuzzers: 007: refactor bel properties handling
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2019-06-21 17:27:26 +02:00
b4634413da
fuzzers: 007: bel: use functions for searching in speed_model
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2019-06-21 17:25:37 +02:00
29210f81da
Add empty defaults for additional new database files.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-06-20 09:39:41 -07:00
816c87a393
Do not require zero features to have zero bits, but do ignore them.
...
During database building, zero features may have other bits. For now,
ignore the fact that zero features have non-zero bits.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-06-20 09:38:47 -07:00
01a0be3162
Add support to zero db to support simple groups.
...
Previously these kinds of zero groups would require encoding the
final bits, rather than tags. This is extends the dbfixup to
construct groups via groups of tags, rather than groups of bits.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-06-19 14:46:39 -07:00
0548c105e4
Merge pull request #897 from antmicro/clean-007
...
Fuzzers: 007-timings: remove unused code
2019-06-19 21:06:26 +02:00
8c059c627b
int_maketodo.py: Replace assertion with warning if PIP can't be balanced
...
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2019-06-19 11:11:40 +02:00
Keith Rothman
Tomasz Michalak
Karol Gugala
Alessandro Comodi
Alessandro Comodi
Maciej Kurc