014462de26
Ported tag grouping to dbfixup.py
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2020-02-13 13:47:32 +01:00
1196f67f71
Moved the group.py script to the utils dir.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2020-02-11 12:24:34 +01:00
b20bae5341
Added grouping of IN_TERM features so they can be decoded unambigosly.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2020-02-11 12:24:34 +01:00
de763a309c
fuzzers: Add support for KiB, MiB and GiB units
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Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2020-01-29 12:33:13 +01:00
45338f1af4
Reworked the PS7 port def. extractor so instead of a minitest its now a fuzzer.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2020-01-28 12:17:16 +01:00
3f0804a417
Merge pull request #1162 from antmicro/zynq_7020_tilegrid
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Tilegrid generation for Zynq 7020
2020-01-27 19:24:07 -08:00
e7667a8daf
Merge pull request #1212 from daveshah1/dspimprove
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fuzzers: Improve DSP fuzzer
2020-01-27 07:18:21 -08:00
31cfa88344
generate both xc7010 and xc7020 parts
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-27 11:26:55 +01:00
5a8e10bba6
zynq: sorted and renamed ignored_wires in 074-dump_all fuzzer
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-27 11:26:55 +01:00
ecab15cd39
zynq: 034-cmt-pll-pips: Remove Zynq specific workarounds
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Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2020-01-27 11:26:55 +01:00
22213404a5
fuzzers: Improve DSP fuzzer
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Signed-off-by: David Shah <dave@ds0.me>
2020-01-27 09:27:46 +00:00
895612c264
zynq: Add ignored wires for Zynq
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-27 10:21:38 +01:00
b211908e26
zynq: fuzzers: Remove Zynq specific workarounds
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-27 10:21:38 +01:00
fb26896dcb
zynq: Allow LIOB baseaddr
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-27 10:21:38 +01:00
13ba74194a
zynq: Add BRKH_INT_PSS tile type to fix assertion
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Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2020-01-27 10:20:22 +01:00
0b623982e5
divided harness and extra parts creation
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There is an issue with the roi_harness creation, for which the
multi-process make does not correctly works for roi_harness target
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
5ae155fd9c
copy tileconn.json in the correct diretory
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
117f3e51b2
revert 074 and 072 to use previous Makefile configuration
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
4a0ca41077
roi_only: copy tilegrid and tileconn from equivalent part
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005-tilegrid fuzzer cannot run for some parts as some of the IOBs are
not available, therefore the fuzzer exits with errors.
Instead, the tilegrid is copied from the specified equivalent part.
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
dfb0717f2c
fix makefile part_only dependencies
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
4849f49724
005-tilegrid: added comment on EXCLUDE_ROI env variable
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
5db213293c
072-ordered_wires: better handling of Lock
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
15d914f2c5
074-dump_all: changed ignored_wires location
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
90d88bc7a2
fix roi_only parts
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
88f7830456
addressed review comments
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
9a88b77620
run make format
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
e464172e03
074-dump_all: exclude tiles and node that are in the excluded roi
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
cb9944d392
005-tilegrid: use variable for dependencies
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
070931ec6e
074-dump_all: fix tilegrid location
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
61cd47dc36
043-clk-rebuf-pips: fixed missing argument
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
127412b5b9
fix wrong location of tilegrid and yaml
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
e84a1d63df
075-pins: create destination directory
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
e44027bcaf
Move all part-specific files to dedicated directory
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
3865c726f2
074-dump_all: increase jobs and tiles per job
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
63bb8337f8
072-ordered_wires: increased parallel jobs.
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This changes also the way the ordered wires final files are generated.
In fact, now, with the help of a Lock, all the suprocesses directly
access the final files, updating them. Once the write completes, the
temporary file is deleted.
This saves up disk space.
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
c5a33cb161
005-tilegrid: further increasing to 6 number of specimens for mmcm
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
e8a2777a17
005-tilegrid: reduce number of specimens
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
5c829daa8c
005-tilegrid: fixed some over-specific settings in generate_full
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Also added specimens to make some rquired fuzzers find all necessary
features
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
93d1ae82f7
Enable the generation of extra part-dependents files
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This change affects the extra-db target, by adding also the generation
of other part-dependent files, such as tilegrid, tileconn, and others.
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
cce638930c
Add clock_region to tilegrid.json for constructing clock networks.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-12-14 22:28:22 -08:00
cc9e00da8f
Merge pull request #1174 from antmicro/zynq_ps7_clocks
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Zynq PS7 clocks
2019-12-12 13:05:29 -08:00
0d0a38cf52
Merge pull request #1175 from antmicro/zynq_ps7_ppips
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Dumping PPIPs for Zynq PS7
2019-12-12 08:50:12 -08:00
810473ef46
Disabled initialization of LIOB3/LIOI33 segbit files for Zynq7
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-12-12 17:20:53 +01:00
ef8d405bdb
Added dumping of PPIPs for Zynq PS7 tiles and interconnects.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-12-12 09:57:41 +01:00
0507f92345
Ran make format
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-12-12 09:31:59 +01:00
24ccfb3bb5
Automatic inference of CLK_HROW with PS7 clocks, use of todo list for PS7 clock sources.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-12-11 22:39:04 +01:00
fb65464c42
A little hacky but working version.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-12-11 19:05:04 +01:00
d84c28b38c
Modified fuzzer 075 to dump IO bank number for each pin.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-12-11 17:10:41 +01:00
6086e6d6f5
Modified fuzzer 041 to solve Zynq PS7 FCLK clocks.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-12-11 16:25:45 +01:00
7bd13efdcb
WIP
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-12-10 15:21:28 +01:00
Maciej Kurc
Tomasz Michalak
litghost
Alessandro Comodi
David Shah