This system standardises on /opt/Xilinx/Vivado/2020.1 not the NFS share
the upstream default points at; honour the local standardisation while
remaining overridable via the env var.
Pairs with task #50 (005-tilegrid virtex7 unaligned-frame fix).
Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
- settings/virtex7.sh: move XRAY_ROI and XRAY_ROI_GRID off the device bottom
edge (SLICE_X0Y50:X11Y99; grid 5-20/261-312). Edge tiles at Y0 can't exercise
features like BRAM36 ECC/cascade, and the bottom-edge BRAM is unsolvable.
- prjxray/segmaker.py: when a tile has no bitstream info (dummy tile, or an edge
tile dropped from the tilegrid such as BRAM_L_X114Y0 on xc7vx485t), account
for any tags on it and skip with a warning instead of asserting. Fixes the
BRAM config/FIFO fuzzers (027, 029, ...) for virtex7; no-op for normal dummy
tiles. Also print the unsolved tags before the all-tags-used assertion.
- fuzzers/Makefile: skip 018-clb-ram for virtex7 (Vivado 2020.1 packs SRL/RAM
into different BEL slots than the fuzzer pins).
Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
Port prjxray to the Virtex-7 family, modelled on Kintex-7, targeting
xc7vx485tffg1761-2 (vc707). Non-breaking for the existing families.
Family registration:
- settings/virtex7.sh, settings/virtex7/devices.yaml
- Makefile: virtex7 in DATABASES/XRAY_PARTS + db-extras-virtex7 targets
- utils/update_parts.py, update_resources.py: virtex7 choice
- CI matrix (Pipeline.yml), Vivado edition (xilinx.sh), README
Architecture adaptations for the HP-bank-only VX part (verified non-breaking):
- update_resources.tcl: fall back to HP banks when no HR banks exist
- XRAY_IOSTANDARD env (default LVCMOS33; LVCMOS18 for virtex7), parameterised
across the fuzzer generate.tcl files
- fuzzers: enable HP-bank (iob18/ioi18) + IOI/HCLK handling for virtex7;
GTX skipped (ffg1761 bonds only ~7 of 14 GTX quads)
- 005-tilegrid: HP/HR bank tile handling; iob18_int INT offset 3->2;
ioi18 AUTO_FRAME; cfg PDRC-2 DRC disable; add_tdb skips unsolved edge tiles;
per-specimen retry for transient FlexLM SIGSEGV under concurrency
- per-family Vivado version gate (virtex7 -> v2020.1.1)
- XRAY_ROI and XRAY_ROI_GRID tuned to a compact CLBLL+CLBLM region
General fixes:
- tools/bitread.cc: fix use-after-free of the mmap'd bitstream (exposed by the
larger Virtex-7 bitstream)
- utils/environment.python.sh: add repo root to PYTHONPATH (PEP 660 editable
install doesn't expose the repo-root utils/ package)
Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
The previous xc7s50t branch was messed up. This new branch is created to re-submit xc7s50t's changes for merging.
Signed-off-by: Steve <steve.bohan.liu@outlook.com>
"eval $(python3 script.py)" does not handle the return code correctly and would try to evaluate
the complete output of the Python traceback. Temporarily save the output in a variable and check
the return code. If the RC is unequal to zero, return the RC and leave the bash script.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
These files contain information about the part information used by the
fuzzers and should help to add new parts easier, later.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
LIOI_X0Y9 has empty "bits" in tilegrid.json. Note there is no RIOI at Y9,
since the bottom right region of the 100T is high speed serial IO.
Signed-off-by: Tim Callahan <tcal@google.com>
This change affects the extra-db target, by adding also the generation
of other part-dependent files, such as tilegrid, tileconn, and others.
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Creates the .db files via make rather than via sourcing settings.sh
allowing pip fuzzers to interact correctly with `make clean`.
Fixes#604.
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
Dr Jonathan Richard Robert Kimmitt
Hans Baier
Hans Baier
Steve
Daniel Schultz
Alessandro Comodi
Robert Winkler
Tomasz Michalak
Tim Callahan
Keith Rothman
Lukasz Dalek
Tim 'mithro' Ansell
Karol Gugala