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Author SHA1 Message Date
Dr Jonathan Richard Robert Kimmitt 39f5de415d Add Virtex-7 (xc7vx485t) family support 
Port prjxray to the Virtex-7 family, modelled on Kintex-7, targeting
xc7vx485tffg1761-2 (vc707). Non-breaking for the existing families.

Family registration:
- settings/virtex7.sh, settings/virtex7/devices.yaml
- Makefile: virtex7 in DATABASES/XRAY_PARTS + db-extras-virtex7 targets
- utils/update_parts.py, update_resources.py: virtex7 choice
- CI matrix (Pipeline.yml), Vivado edition (xilinx.sh), README

Architecture adaptations for the HP-bank-only VX part (verified non-breaking):
- update_resources.tcl: fall back to HP banks when no HR banks exist
- XRAY_IOSTANDARD env (default LVCMOS33; LVCMOS18 for virtex7), parameterised
  across the fuzzer generate.tcl files
- fuzzers: enable HP-bank (iob18/ioi18) + IOI/HCLK handling for virtex7;
  GTX skipped (ffg1761 bonds only ~7 of 14 GTX quads)
- 005-tilegrid: HP/HR bank tile handling; iob18_int INT offset 3->2;
  ioi18 AUTO_FRAME; cfg PDRC-2 DRC disable; add_tdb skips unsolved edge tiles;
  per-specimen retry for transient FlexLM SIGSEGV under concurrency
- per-family Vivado version gate (virtex7 -> v2020.1.1)
- XRAY_ROI and XRAY_ROI_GRID tuned to a compact CLBLL+CLBLM region

General fixes:
- tools/bitread.cc: fix use-after-free of the mmap'd bitstream (exposed by the
  larger Virtex-7 bitstream)
- utils/environment.python.sh: add repo root to PYTHONPATH (PEP 660 editable
  install doesn't expose the repo-root utils/ package)

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
 2026-05-24 07:21:23 +01:00
Andrew Butt 2f03a575e2 Fix SDF generation 
Signed-off-by: Andrew Butt <butta@seas.upenn.edu>
 2020-07-08 10:55:20 -04:00
Tomasz Michalak c66f4f4aa1 Add license headers to tcl files 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
 2020-05-26 07:33:12 -07:00
Tomasz Michalak 300bc62227 Add licensing header to bash scripts 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
 2020-05-26 07:33:12 -07:00
Tomasz Michalak 159d6a8e88 Add licensing header to Makefiles 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
 2020-05-26 07:33:12 -07:00
Tomasz Michalak 950d7534ec Add licensing header to fuzzers' python scripts 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
 2020-05-26 07:33:12 -07:00
Keith Rothman 49b5a8cde6 Handle weird bel pins that aren't really clocks. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-12 12:59:14 -08:00
Keith Rothman 2f388235e4 Update doctests. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-11 20:55:07 -08:00
Keith Rothman ec69db772d Remove progressbar 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-11 20:50:50 -08:00
Keith Rothman 0c1a404ab1 Run make format. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-11 20:49:09 -08:00
Keith Rothman 564863ccad Refactor remaining function in tim2json.py 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-11 20:38:34 -08:00
Keith Rothman e17f9e8140 Refactor routines to read pins, props, and site pins. 
Also fix Makefile intermediate.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-11 20:38:27 -08:00
Keith Rothman b9f8f962f1 Start of SERDES timing. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-11 16:52:12 -08:00
Karol Gugala 2b93883d78 fuzzers: 007: run make format 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-07-23 14:50:10 +02:00
Karol Gugala 10e022140e fuzzers: 007: reorganize Makefiles 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-07-23 14:49:45 +02:00
Lukasz Dalek 7665003311 fuzzers: 007-timing: Add CARRY4 [ABCD]CY muxes 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2019-07-23 10:21:02 +02:00
Karol Gugala 78346781ce fuzzers: 007: fix Makefile targets definitions 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-07-02 19:04:10 +02:00
Karol Gugala 28d961a650 fuzzers: routing BELs: group timings by interconn oputput 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-07-02 13:08:14 +02:00
Karol Gugala 6cc614f1fb fuzzers: 007: fix BEL fuzzer Makefile 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala 9658653da8 fuzzers: bel: emit routing bels timings as INTERCONN 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala 03252bc46f fuzzers: 007: add gitignores 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala a99e26bbd4 fuzzers: 007: make both bels and routing-bels 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala cb3a2b42d7 fuzzers: 007: produce sdf files for routing bels 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala 2c1d4342b7 fuzzers: 007: format python 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala ec28d95604 fuzzers: 007: add routing BELs fuzzer 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Alessandro Comodi ca6bbee193
Merge pull request #908 from antmicro/fix-bram-timing-fuzzer 
007-timing: added missing aliases for bram timing
 2019-06-26 13:00:20 +02:00
Alessandro Comodi 6476443a52 007-timing: added missing aliases for bram timing 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-06-25 17:13:44 +02:00
Karol Gugala f6450b72b8 fuzzers: 007: bel: sort timing keywords 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-21 17:28:48 +02:00
Karol Gugala a560cc3500 fuzzers: 007: bel: do not copy timing data 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-21 17:28:05 +02:00
Karol Gugala 7821cb743c fuzzers: 007: refactor bel properties handling 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-21 17:27:26 +02:00
Karol Gugala b4634413da fuzzers: 007: bel: use functions for searching in speed_model 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-21 17:25:37 +02:00
Karol Gugala d5dc09948a fuzzers: 007: remove unused code 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-19 10:53:19 +02:00
Karol Gugala 0fe609353e fuzzers: 007: update docstring for find_aliased_pin 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 2d26781992 fuzzers: 007: tim2json: update docstrings 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 37626d75e5 fuzzers: 007: fixup_timings: update docstrings 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 9b04747da9 fuzzers: 007: bel: add README 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala afb0cc78da fuzzers: 007: add docstring and assert to line_fixup function 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 63e6d17b50 fuzzers: 007: rename pin alias property -> is_property_related 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala bb9bc7bfdd fuzzers: 007: refactor aliased pins detection 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 26614e5ed4 fuzzers: 007: restore missing continue 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala c9d661d161 fuzzers: 007: run make format 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 73979fdf04 fuzzers: 007: handle pin/pin and pin/prop aliases 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala b122f07896 fuzzers: 007: do not emit clk -> clk timing checks 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 209240e77f fuzzers: 007: handle output vector pins 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala cdcb759299 fuzzers: 007: remove commented code 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 83657adbb9 fuzzers: 007: fix clock inputs inferring 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala ecb4fa1289 fuzzers: 007: use timings fixup 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 91e7f3910e fuzzers: 007: add timings_fixup script 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Maciej Kurc 8366e324af Code refactoring. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-18 18:30:48 +02:00
Maciej Kurc d05945ff81 Added support for aliases of pins with underscore in names. Added doctests 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-18 18:30:48 +02:00