luke
/
prjxray-db
mirror of https://github.com/openXC7/prjxray-db.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Compare commits

base: luke:0.9.1
Branches Tags
luke:master
luke:0.9.1
luke:0.8.2
luke:0.8.1
luke:0.8.0
luke:0.7.0
luke:0.6.1
luke:0.6.0
..
compare: luke:master
Branches Tags
luke:master
luke:0.9.1
luke:0.8.2
luke:0.8.1
luke:0.8.0
luke:0.7.0
luke:0.6.1
luke:0.6.0

6 Commits
0.9.1 ... master

Author SHA1 Message Date
Hans Baier ab1fc60c38 README: add 'funded by NLnet Foundation' badge 2026-08-15 08:17:44 +07:00
Hans Baier d17fea26eb
Merge pull request #6 from cavearr/db/artix7-ilogic-sameedge-pipelined-p1-openxc7 
artix7: add ILOGIC IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED and IFFDELMUXE3.P1
 2026-08-14 03:58:57 +07:00
Carlos Venegas Arrabé ef46e80c55
artix7: add ILOGIC IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED and IFFDELMUXE3.P1 
Materialisation of the fuzzer tag-group fix f4pga/prjxray#2570 (three
groups under-declared in 035-iob-ilogic; diagnosis by gHashTag): the
four ILOGIC tags whose encoding is all-bits-clear solved to nothing
because dbfixup's group_tags had no group to derive the zero-sides
from. Added per IOI3 variant, segbits + origin_info; masks unchanged:

  ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED !26_99 !27_98
  ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED !26_29 !27_28
  ILOGIC_Y0.IFFDELMUXE3.P1 !28_116
  ILOGIC_Y1.IFFDELMUXE3.P1 !29_11

Provenance: fuzzer 035-iob-ilogic re-run with the #2570 groups on
xc7a100tfgg676-1, Vivado ML 2026.1, N=30 specimens, standard
publication pipeline (pushdb, parsedb --strict, sort_db). Gate: the
stock fuzzer under the same environment first regenerated the
committed DDR_CLK_EDGE.{OPPOSITE,SAME}_EDGE and IFFDELMUXE3.P0 lines
byte-identical. Control: the raw segmatch output of the extended run
is byte-identical to the stock run's — tag_groups.txt was the only
variable in the experiment.

This repository is the revision nextpnr-xilinx's submodule records, so
these rows land here first; the same change is filed against
f4pga/prjxray-db as the archival copy. Unblocks the
SAME_EDGE_PIPELINED / IFFDELMUXE3.P1 emission classes
(openXC7/nextpnr-xilinx#114, #65). IDELMUXE3.P2/IFFDELMUXE3.P2 stay
open on purpose: no fuzzer specimen ever selects P2, so they need
top.py/generate.py coverage, not tag grouping.
 2026-08-13 19:52:06 +02:00
Hans Baier 399a099bb9 kintex7: add missing RIOI_Y9 tilegrid frame bits 
The bottom-edge RIOI row (k160t RIOI_X73Y9, k325t RIOI_X95Y9) had an
empty bits entry while its neighbours (Y5 offset 10, Y11 offset 22)
carried the CLB_IO_CLK frame map; the k70t X43Y9 confirms the expected
offset 18 (+4 per row).  Any routed TQ->T1 pass-through through that
row made fasm2frames abort with FasmLookupError (seen on
litex-ddr-enclustra-kx2).
 2026-08-08 15:11:48 +07:00
Hans Baier d429061eab kintex7, virtex7: add RIOB18.IOB_Y1.LVCMOS12_LVCMOS15.IN 
Single-ended LVCMOS12/15 input on the Y1 (slave) site of an HP-bank
IOB18 tile was missing.  nextpnr emits it for LVCMOS15 inputs on the
N pin of a diff pair; fasm2frames failed with FasmLookupError
(blinky/hdmi-stlv7325, RIOB18_X95Y25).  Bit value mirrors the
LVCMOS12_LVCMOS15_LVCMOS18.IN variant at the same site, matching the
bit-identity of the Y0 with/without-LVCMOS18 pair (verified in both
families).
 2026-08-06 22:53:45 +07:00
Hans Baier 3bd17eb8d9 kintex7: HP-bank IOB18/INT IOB_COL segbits (virtex7 arch mirror) 
RIOB18: IBUFDS_BANK_GLUE, LVDS/SSTL IN_DIFF + IN_ONLY groups,
LVCMOS12_LVCMOS15.IN, LVDS DRIVE/IN_USE, SSTL*.IN_USE, Y1
LVCMOS12_LVCMOS15_SSTL12_SSTL135_SSTL15.IN_ONLY, OBUF_HP_BANK_GLUE
Y0/Y1 and the LVCMOS-family SLEW.SLOW group (LIOB18 mirror).
INT_L/INT_R: IOB_COL_BANK_ACTIVE, IOB_COL_OBUF_CASCADE_Y1.

kintex7 and virtex7 are bit-identical for these tile types (55 shared
RIOB18 + 2020 shared INT_L + 2020 shared INT_R entries, zero
differences), so virtex7 fuzz data transfers directly.  Entries
validated with a Vivado 2017.2 golden bitstream on xc7k70tfbg676-2
(IBUFDS input, LVCMOS15/SSTL15 outputs on HP bank 33, SE input):
bitread + bit2fasm decode confirms OBUF_HP_BANK_GLUE, long SLEW.SLOW
group, Y1 IBUF_HP_BANK_GLUE and INT_R IOB_COL bits.  Origin tags
record provenance (virtex7-arch-mirror / liob18-arch-mirror).

Unblocks kintex7 open-flow builds using LVDS/diff clocks or HP-bank
pins (previously FasmLookupError in fasm2frames).
 2026-08-06 20:01:27 +07:00
23 changed files with 88 additions and 2 deletions
Show Stats Expand all files Collapse all files

2
README.md
View File

@ -1,5 +1,7 @@
# Project X-Ray - Xilinx Series 7 Bitstream Documentation # Project X-Ray - Xilinx Series 7 Bitstream Documentation
[![NLnet Foundation](https://img.shields.io/badge/funded%20by-NLnet%20Foundation-74AA00)](https://nlnet.nl/)
[TOC] [TOC]
This repo contains the bitstream documentation database for Xilinx Series 7 This repo contains the bitstream documentation database for Xilinx Series 7

4
artix7/segbits_lioi3.db
View File

@ -44,6 +44,7 @@ LIOI3.ILOGIC_Y0.IDDR.IN_USE 26_71 26_121 27_70
LIOI3.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70 LIOI3.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70
LIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98 LIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98
LIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98 LIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98
LIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED !26_99 !27_98
LIOI3.ILOGIC_Y0.IFF.INV_OCLK 28_124 LIOI3.ILOGIC_Y0.IFF.INV_OCLK 28_124
LIOI3.ILOGIC_Y0.IFF.SRTYPE.ASYNC !29_67 LIOI3.ILOGIC_Y0.IFF.SRTYPE.ASYNC !29_67
LIOI3.ILOGIC_Y0.IFF.SRTYPE.SYNC 29_67 LIOI3.ILOGIC_Y0.IFF.SRTYPE.SYNC 29_67
@ -85,10 +86,12 @@ LIOI3.ILOGIC_Y0.ZINV_D 29_109
LIOI3.ILOGIC_Y0.IDELMUXE3.P0 29_101 LIOI3.ILOGIC_Y0.IDELMUXE3.P0 29_101
LIOI3.ILOGIC_Y0.IDELMUXE3.P1 !29_101 LIOI3.ILOGIC_Y0.IDELMUXE3.P1 !29_101
LIOI3.ILOGIC_Y0.IFFDELMUXE3.P0 28_116 LIOI3.ILOGIC_Y0.IFFDELMUXE3.P0 28_116
LIOI3.ILOGIC_Y0.IFFDELMUXE3.P1 !28_116
LIOI3.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56 LIOI3.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56
LIOI3.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56 LIOI3.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56
LIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28 LIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28
LIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28 LIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28
LIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED !26_29 !27_28
LIOI3.ILOGIC_Y1.IFF.INV_OCLK 29_03 LIOI3.ILOGIC_Y1.IFF.INV_OCLK 29_03
LIOI3.ILOGIC_Y1.IFF.SRTYPE.ASYNC !28_60 LIOI3.ILOGIC_Y1.IFF.SRTYPE.ASYNC !28_60
LIOI3.ILOGIC_Y1.IFF.SRTYPE.SYNC 28_60 LIOI3.ILOGIC_Y1.IFF.SRTYPE.SYNC 28_60
@ -130,6 +133,7 @@ LIOI3.ILOGIC_Y1.ZINV_D 28_18
LIOI3.ILOGIC_Y1.IDELMUXE3.P0 28_26 LIOI3.ILOGIC_Y1.IDELMUXE3.P0 28_26
LIOI3.ILOGIC_Y1.IDELMUXE3.P1 !28_26 LIOI3.ILOGIC_Y1.IDELMUXE3.P1 !28_26
LIOI3.ILOGIC_Y1.IFFDELMUXE3.P0 29_11 LIOI3.ILOGIC_Y1.IFFDELMUXE3.P0 29_11
LIOI3.ILOGIC_Y1.IFFDELMUXE3.P1 !29_11
LIOI3.IOI_OCLK_0.IOI_LEAF_GCLK0 28_83 28_95 29_88 LIOI3.IOI_OCLK_0.IOI_LEAF_GCLK0 28_83 28_95 29_88
LIOI3.IOI_OCLK_0.IOI_LEAF_GCLK1 28_83 28_97 29_88 LIOI3.IOI_OCLK_0.IOI_LEAF_GCLK1 28_83 28_97 29_88
LIOI3.IOI_OCLK_0.IOI_LEAF_GCLK2 28_83 29_88 29_94 LIOI3.IOI_OCLK_0.IOI_LEAF_GCLK2 28_83 29_88 29_94

4
artix7/segbits_lioi3.origin_info.db
View File

@ -44,6 +44,7 @@ LIOI3.ILOGIC_Y0.IDDR.IN_USE origin:035b-iob-iserdes 26_121 26_71 27_70
LIOI3.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70 LIOI3.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70
LIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98 LIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98
LIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99 LIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99
LIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED origin:035-iob-ilogic !26_99 !27_98
LIOI3.ILOGIC_Y0.IFF.INV_OCLK origin:035-iob-ilogic 28_124 LIOI3.ILOGIC_Y0.IFF.INV_OCLK origin:035-iob-ilogic 28_124
LIOI3.ILOGIC_Y0.IFF.SRTYPE.ASYNC origin:035-iob-ilogic !29_67 LIOI3.ILOGIC_Y0.IFF.SRTYPE.ASYNC origin:035-iob-ilogic !29_67
LIOI3.ILOGIC_Y0.IFF.SRTYPE.SYNC origin:035-iob-ilogic 29_67 LIOI3.ILOGIC_Y0.IFF.SRTYPE.SYNC origin:035-iob-ilogic 29_67
@ -85,10 +86,12 @@ LIOI3.ILOGIC_Y0.ZINV_D origin:035-iob-ilogic 29_109
LIOI3.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101 LIOI3.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101
LIOI3.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101 LIOI3.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101
LIOI3.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116 LIOI3.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116
LIOI3.ILOGIC_Y0.IFFDELMUXE3.P1 origin:035-iob-ilogic !28_116
LIOI3.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56 LIOI3.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56
LIOI3.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56 LIOI3.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56
LIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29 LIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29
LIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28 LIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28
LIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED origin:035-iob-ilogic !26_29 !27_28
LIOI3.ILOGIC_Y1.IFF.INV_OCLK origin:035-iob-ilogic 29_03 LIOI3.ILOGIC_Y1.IFF.INV_OCLK origin:035-iob-ilogic 29_03
LIOI3.ILOGIC_Y1.IFF.SRTYPE.ASYNC origin:035-iob-ilogic !28_60 LIOI3.ILOGIC_Y1.IFF.SRTYPE.ASYNC origin:035-iob-ilogic !28_60
LIOI3.ILOGIC_Y1.IFF.SRTYPE.SYNC origin:035-iob-ilogic 28_60 LIOI3.ILOGIC_Y1.IFF.SRTYPE.SYNC origin:035-iob-ilogic 28_60
@ -130,6 +133,7 @@ LIOI3.ILOGIC_Y1.ZINV_D origin:035-iob-ilogic 28_18
LIOI3.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26 LIOI3.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26
LIOI3.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26 LIOI3.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26
LIOI3.ILOGIC_Y1.IFFDELMUXE3.P0 origin:035-iob-ilogic 29_11 LIOI3.ILOGIC_Y1.IFFDELMUXE3.P0 origin:035-iob-ilogic 29_11
LIOI3.ILOGIC_Y1.IFFDELMUXE3.P1 origin:035-iob-ilogic !29_11
LIOI3.IOI_OCLK_0.IOI_LEAF_GCLK0 origin:037-iob-pips 28_83 28_95 29_88 LIOI3.IOI_OCLK_0.IOI_LEAF_GCLK0 origin:037-iob-pips 28_83 28_95 29_88
LIOI3.IOI_OCLK_0.IOI_LEAF_GCLK1 origin:037-iob-pips 28_83 28_97 29_88 LIOI3.IOI_OCLK_0.IOI_LEAF_GCLK1 origin:037-iob-pips 28_83 28_97 29_88
LIOI3.IOI_OCLK_0.IOI_LEAF_GCLK2 origin:037-iob-pips 28_83 29_88 29_94 LIOI3.IOI_OCLK_0.IOI_LEAF_GCLK2 origin:037-iob-pips 28_83 29_88 29_94

4
artix7/segbits_lioi3_tbytesrc.db
View File

@ -44,6 +44,7 @@ LIOI3_TBYTESRC.ILOGIC_Y0.IDDR.IN_USE 26_71 26_121 27_70
LIOI3_TBYTESRC.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70 LIOI3_TBYTESRC.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70
LIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98 LIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98
LIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98 LIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98
LIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED !26_99 !27_98
LIOI3_TBYTESRC.ILOGIC_Y0.IFF.INV_OCLK 28_124 LIOI3_TBYTESRC.ILOGIC_Y0.IFF.INV_OCLK 28_124
LIOI3_TBYTESRC.ILOGIC_Y0.IFF.SRTYPE.ASYNC !29_67 LIOI3_TBYTESRC.ILOGIC_Y0.IFF.SRTYPE.ASYNC !29_67
LIOI3_TBYTESRC.ILOGIC_Y0.IFF.SRTYPE.SYNC 29_67 LIOI3_TBYTESRC.ILOGIC_Y0.IFF.SRTYPE.SYNC 29_67
@ -85,10 +86,12 @@ LIOI3_TBYTESRC.ILOGIC_Y0.ZINV_D 29_109
LIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P0 29_101 LIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P0 29_101
LIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P1 !29_101 LIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P1 !29_101
LIOI3_TBYTESRC.ILOGIC_Y0.IFFDELMUXE3.P0 28_116 LIOI3_TBYTESRC.ILOGIC_Y0.IFFDELMUXE3.P0 28_116
LIOI3_TBYTESRC.ILOGIC_Y0.IFFDELMUXE3.P1 !28_116
LIOI3_TBYTESRC.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56 LIOI3_TBYTESRC.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56
LIOI3_TBYTESRC.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56 LIOI3_TBYTESRC.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56
LIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28 LIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28
LIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28 LIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28
LIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED !26_29 !27_28
LIOI3_TBYTESRC.ILOGIC_Y1.IFF.INV_OCLK 29_03 LIOI3_TBYTESRC.ILOGIC_Y1.IFF.INV_OCLK 29_03
LIOI3_TBYTESRC.ILOGIC_Y1.IFF.SRTYPE.ASYNC !28_60 LIOI3_TBYTESRC.ILOGIC_Y1.IFF.SRTYPE.ASYNC !28_60
LIOI3_TBYTESRC.ILOGIC_Y1.IFF.SRTYPE.SYNC 28_60 LIOI3_TBYTESRC.ILOGIC_Y1.IFF.SRTYPE.SYNC 28_60
@ -130,6 +133,7 @@ LIOI3_TBYTESRC.ILOGIC_Y1.ZINV_D 28_18
LIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P0 28_26 LIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P0 28_26
LIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P1 !28_26 LIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P1 !28_26
LIOI3_TBYTESRC.ILOGIC_Y1.IFFDELMUXE3.P0 29_11 LIOI3_TBYTESRC.ILOGIC_Y1.IFFDELMUXE3.P0 29_11
LIOI3_TBYTESRC.ILOGIC_Y1.IFFDELMUXE3.P1 !29_11
LIOI3_TBYTESRC.IOI_OCLK_0.IOI_LEAF_GCLK0 28_83 28_95 29_88 LIOI3_TBYTESRC.IOI_OCLK_0.IOI_LEAF_GCLK0 28_83 28_95 29_88
LIOI3_TBYTESRC.IOI_OCLK_0.IOI_LEAF_GCLK1 28_83 28_97 29_88 LIOI3_TBYTESRC.IOI_OCLK_0.IOI_LEAF_GCLK1 28_83 28_97 29_88
LIOI3_TBYTESRC.IOI_OCLK_0.IOI_LEAF_GCLK2 28_83 29_88 29_94 LIOI3_TBYTESRC.IOI_OCLK_0.IOI_LEAF_GCLK2 28_83 29_88 29_94

4
artix7/segbits_lioi3_tbytesrc.origin_info.db
View File

@ -44,6 +44,7 @@ LIOI3_TBYTESRC.ILOGIC_Y0.IDDR.IN_USE origin:035b-iob-iserdes 26_121 26_71 27_70
LIOI3_TBYTESRC.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70 LIOI3_TBYTESRC.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70
LIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98 LIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98
LIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99 LIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99
LIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED origin:035-iob-ilogic !26_99 !27_98
LIOI3_TBYTESRC.ILOGIC_Y0.IFF.INV_OCLK origin:035-iob-ilogic 28_124 LIOI3_TBYTESRC.ILOGIC_Y0.IFF.INV_OCLK origin:035-iob-ilogic 28_124
LIOI3_TBYTESRC.ILOGIC_Y0.IFF.SRTYPE.ASYNC origin:035-iob-ilogic !29_67 LIOI3_TBYTESRC.ILOGIC_Y0.IFF.SRTYPE.ASYNC origin:035-iob-ilogic !29_67
LIOI3_TBYTESRC.ILOGIC_Y0.IFF.SRTYPE.SYNC origin:035-iob-ilogic 29_67 LIOI3_TBYTESRC.ILOGIC_Y0.IFF.SRTYPE.SYNC origin:035-iob-ilogic 29_67
@ -85,10 +86,12 @@ LIOI3_TBYTESRC.ILOGIC_Y0.ZINV_D origin:035-iob-ilogic 29_109
LIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101 LIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101
LIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101 LIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101
LIOI3_TBYTESRC.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116 LIOI3_TBYTESRC.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116
LIOI3_TBYTESRC.ILOGIC_Y0.IFFDELMUXE3.P1 origin:035-iob-ilogic !28_116
LIOI3_TBYTESRC.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56 LIOI3_TBYTESRC.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56
LIOI3_TBYTESRC.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56 LIOI3_TBYTESRC.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56
LIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29 LIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29
LIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28 LIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28
LIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED origin:035-iob-ilogic !26_29 !27_28
LIOI3_TBYTESRC.ILOGIC_Y1.IFF.INV_OCLK origin:035-iob-ilogic 29_03 LIOI3_TBYTESRC.ILOGIC_Y1.IFF.INV_OCLK origin:035-iob-ilogic 29_03
LIOI3_TBYTESRC.ILOGIC_Y1.IFF.SRTYPE.ASYNC origin:035-iob-ilogic !28_60 LIOI3_TBYTESRC.ILOGIC_Y1.IFF.SRTYPE.ASYNC origin:035-iob-ilogic !28_60
LIOI3_TBYTESRC.ILOGIC_Y1.IFF.SRTYPE.SYNC origin:035-iob-ilogic 28_60 LIOI3_TBYTESRC.ILOGIC_Y1.IFF.SRTYPE.SYNC origin:035-iob-ilogic 28_60
@ -130,6 +133,7 @@ LIOI3_TBYTESRC.ILOGIC_Y1.ZINV_D origin:035-iob-ilogic 28_18
LIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26 LIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26
LIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26 LIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26
LIOI3_TBYTESRC.ILOGIC_Y1.IFFDELMUXE3.P0 origin:035-iob-ilogic 29_11 LIOI3_TBYTESRC.ILOGIC_Y1.IFFDELMUXE3.P0 origin:035-iob-ilogic 29_11
LIOI3_TBYTESRC.ILOGIC_Y1.IFFDELMUXE3.P1 origin:035-iob-ilogic !29_11
LIOI3_TBYTESRC.IOI_OCLK_0.IOI_LEAF_GCLK0 origin:037-iob-pips 28_83 28_95 29_88 LIOI3_TBYTESRC.IOI_OCLK_0.IOI_LEAF_GCLK0 origin:037-iob-pips 28_83 28_95 29_88
LIOI3_TBYTESRC.IOI_OCLK_0.IOI_LEAF_GCLK1 origin:037-iob-pips 28_83 28_97 29_88 LIOI3_TBYTESRC.IOI_OCLK_0.IOI_LEAF_GCLK1 origin:037-iob-pips 28_83 28_97 29_88
LIOI3_TBYTESRC.IOI_OCLK_0.IOI_LEAF_GCLK2 origin:037-iob-pips 28_83 29_88 29_94 LIOI3_TBYTESRC.IOI_OCLK_0.IOI_LEAF_GCLK2 origin:037-iob-pips 28_83 29_88 29_94

4
artix7/segbits_lioi3_tbyteterm.db
View File

@ -44,6 +44,7 @@ LIOI3_TBYTETERM.ILOGIC_Y0.IDDR.IN_USE 26_71 26_121 27_70
LIOI3_TBYTETERM.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70 LIOI3_TBYTETERM.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70
LIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98 LIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98
LIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98 LIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98
LIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED !26_99 !27_98
LIOI3_TBYTETERM.ILOGIC_Y0.IFF.INV_OCLK 28_124 LIOI3_TBYTETERM.ILOGIC_Y0.IFF.INV_OCLK 28_124
LIOI3_TBYTETERM.ILOGIC_Y0.IFF.SRTYPE.ASYNC !29_67 LIOI3_TBYTETERM.ILOGIC_Y0.IFF.SRTYPE.ASYNC !29_67
LIOI3_TBYTETERM.ILOGIC_Y0.IFF.SRTYPE.SYNC 29_67 LIOI3_TBYTETERM.ILOGIC_Y0.IFF.SRTYPE.SYNC 29_67
@ -85,10 +86,12 @@ LIOI3_TBYTETERM.ILOGIC_Y0.ZINV_D 29_109
LIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P0 29_101 LIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P0 29_101
LIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P1 !29_101 LIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P1 !29_101
LIOI3_TBYTETERM.ILOGIC_Y0.IFFDELMUXE3.P0 28_116 LIOI3_TBYTETERM.ILOGIC_Y0.IFFDELMUXE3.P0 28_116
LIOI3_TBYTETERM.ILOGIC_Y0.IFFDELMUXE3.P1 !28_116
LIOI3_TBYTETERM.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56 LIOI3_TBYTETERM.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56
LIOI3_TBYTETERM.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56 LIOI3_TBYTETERM.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56
LIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28 LIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28
LIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28 LIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28
LIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED !26_29 !27_28
LIOI3_TBYTETERM.ILOGIC_Y1.IFF.INV_OCLK 29_03 LIOI3_TBYTETERM.ILOGIC_Y1.IFF.INV_OCLK 29_03
LIOI3_TBYTETERM.ILOGIC_Y1.IFF.SRTYPE.ASYNC !28_60 LIOI3_TBYTETERM.ILOGIC_Y1.IFF.SRTYPE.ASYNC !28_60
LIOI3_TBYTETERM.ILOGIC_Y1.IFF.SRTYPE.SYNC 28_60 LIOI3_TBYTETERM.ILOGIC_Y1.IFF.SRTYPE.SYNC 28_60
@ -130,6 +133,7 @@ LIOI3_TBYTETERM.ILOGIC_Y1.ZINV_D 28_18
LIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P0 28_26 LIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P0 28_26
LIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P1 !28_26 LIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P1 !28_26
LIOI3_TBYTETERM.ILOGIC_Y1.IFFDELMUXE3.P0 29_11 LIOI3_TBYTETERM.ILOGIC_Y1.IFFDELMUXE3.P0 29_11
LIOI3_TBYTETERM.ILOGIC_Y1.IFFDELMUXE3.P1 !29_11
LIOI3_TBYTETERM.IOI_OCLK_0.IOI_LEAF_GCLK0 28_83 28_95 29_88 LIOI3_TBYTETERM.IOI_OCLK_0.IOI_LEAF_GCLK0 28_83 28_95 29_88
LIOI3_TBYTETERM.IOI_OCLK_0.IOI_LEAF_GCLK1 28_83 28_97 29_88 LIOI3_TBYTETERM.IOI_OCLK_0.IOI_LEAF_GCLK1 28_83 28_97 29_88
LIOI3_TBYTETERM.IOI_OCLK_0.IOI_LEAF_GCLK2 28_83 29_88 29_94 LIOI3_TBYTETERM.IOI_OCLK_0.IOI_LEAF_GCLK2 28_83 29_88 29_94

4
artix7/segbits_lioi3_tbyteterm.origin_info.db
View File

@ -44,6 +44,7 @@ LIOI3_TBYTETERM.ILOGIC_Y0.IDDR.IN_USE origin:035b-iob-iserdes 26_121 26_71 27_70
LIOI3_TBYTETERM.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70 LIOI3_TBYTETERM.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70
LIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98 LIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98
LIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99 LIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99
LIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED origin:035-iob-ilogic !26_99 !27_98
LIOI3_TBYTETERM.ILOGIC_Y0.IFF.INV_OCLK origin:035-iob-ilogic 28_124 LIOI3_TBYTETERM.ILOGIC_Y0.IFF.INV_OCLK origin:035-iob-ilogic 28_124
LIOI3_TBYTETERM.ILOGIC_Y0.IFF.SRTYPE.ASYNC origin:035-iob-ilogic !29_67 LIOI3_TBYTETERM.ILOGIC_Y0.IFF.SRTYPE.ASYNC origin:035-iob-ilogic !29_67
LIOI3_TBYTETERM.ILOGIC_Y0.IFF.SRTYPE.SYNC origin:035-iob-ilogic 29_67 LIOI3_TBYTETERM.ILOGIC_Y0.IFF.SRTYPE.SYNC origin:035-iob-ilogic 29_67
@ -85,10 +86,12 @@ LIOI3_TBYTETERM.ILOGIC_Y0.ZINV_D origin:035-iob-ilogic 29_109
LIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101 LIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101
LIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101 LIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101
LIOI3_TBYTETERM.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116 LIOI3_TBYTETERM.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116
LIOI3_TBYTETERM.ILOGIC_Y0.IFFDELMUXE3.P1 origin:035-iob-ilogic !28_116
LIOI3_TBYTETERM.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56 LIOI3_TBYTETERM.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56
LIOI3_TBYTETERM.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56 LIOI3_TBYTETERM.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56
LIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29 LIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29
LIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28 LIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28
LIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED origin:035-iob-ilogic !26_29 !27_28
LIOI3_TBYTETERM.ILOGIC_Y1.IFF.INV_OCLK origin:035-iob-ilogic 29_03 LIOI3_TBYTETERM.ILOGIC_Y1.IFF.INV_OCLK origin:035-iob-ilogic 29_03
LIOI3_TBYTETERM.ILOGIC_Y1.IFF.SRTYPE.ASYNC origin:035-iob-ilogic !28_60 LIOI3_TBYTETERM.ILOGIC_Y1.IFF.SRTYPE.ASYNC origin:035-iob-ilogic !28_60
LIOI3_TBYTETERM.ILOGIC_Y1.IFF.SRTYPE.SYNC origin:035-iob-ilogic 28_60 LIOI3_TBYTETERM.ILOGIC_Y1.IFF.SRTYPE.SYNC origin:035-iob-ilogic 28_60
@ -130,6 +133,7 @@ LIOI3_TBYTETERM.ILOGIC_Y1.ZINV_D origin:035-iob-ilogic 28_18
LIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26 LIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26
LIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26 LIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26
LIOI3_TBYTETERM.ILOGIC_Y1.IFFDELMUXE3.P0 origin:035-iob-ilogic 29_11 LIOI3_TBYTETERM.ILOGIC_Y1.IFFDELMUXE3.P0 origin:035-iob-ilogic 29_11
LIOI3_TBYTETERM.ILOGIC_Y1.IFFDELMUXE3.P1 origin:035-iob-ilogic !29_11
LIOI3_TBYTETERM.IOI_OCLK_0.IOI_LEAF_GCLK0 origin:037-iob-pips 28_83 28_95 29_88 LIOI3_TBYTETERM.IOI_OCLK_0.IOI_LEAF_GCLK0 origin:037-iob-pips 28_83 28_95 29_88
LIOI3_TBYTETERM.IOI_OCLK_0.IOI_LEAF_GCLK1 origin:037-iob-pips 28_83 28_97 29_88 LIOI3_TBYTETERM.IOI_OCLK_0.IOI_LEAF_GCLK1 origin:037-iob-pips 28_83 28_97 29_88
LIOI3_TBYTETERM.IOI_OCLK_0.IOI_LEAF_GCLK2 origin:037-iob-pips 28_83 29_88 29_94 LIOI3_TBYTETERM.IOI_OCLK_0.IOI_LEAF_GCLK2 origin:037-iob-pips 28_83 29_88 29_94

4
artix7/segbits_rioi3.db
View File

@ -44,6 +44,7 @@ RIOI3.ILOGIC_Y0.IDDR.IN_USE 26_71 26_121 27_70
RIOI3.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70 RIOI3.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70
RIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98 RIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98
RIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98 RIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98
RIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED !26_99 !27_98
RIOI3.ILOGIC_Y0.IFF.INV_OCLK 28_124 RIOI3.ILOGIC_Y0.IFF.INV_OCLK 28_124
RIOI3.ILOGIC_Y0.IFF.SRTYPE.ASYNC !29_67 RIOI3.ILOGIC_Y0.IFF.SRTYPE.ASYNC !29_67
RIOI3.ILOGIC_Y0.IFF.SRTYPE.SYNC 29_67 RIOI3.ILOGIC_Y0.IFF.SRTYPE.SYNC 29_67
@ -85,10 +86,12 @@ RIOI3.ILOGIC_Y0.ZINV_D 29_109
RIOI3.ILOGIC_Y0.IDELMUXE3.P0 29_101 RIOI3.ILOGIC_Y0.IDELMUXE3.P0 29_101
RIOI3.ILOGIC_Y0.IDELMUXE3.P1 !29_101 RIOI3.ILOGIC_Y0.IDELMUXE3.P1 !29_101
RIOI3.ILOGIC_Y0.IFFDELMUXE3.P0 28_116 RIOI3.ILOGIC_Y0.IFFDELMUXE3.P0 28_116
RIOI3.ILOGIC_Y0.IFFDELMUXE3.P1 !28_116
RIOI3.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56 RIOI3.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56
RIOI3.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56 RIOI3.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56
RIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28 RIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28
RIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28 RIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28
RIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED !26_29 !27_28
RIOI3.ILOGIC_Y1.IFF.INV_OCLK 29_03 RIOI3.ILOGIC_Y1.IFF.INV_OCLK 29_03
RIOI3.ILOGIC_Y1.IFF.SRTYPE.ASYNC !28_60 RIOI3.ILOGIC_Y1.IFF.SRTYPE.ASYNC !28_60
RIOI3.ILOGIC_Y1.IFF.SRTYPE.SYNC 28_60 RIOI3.ILOGIC_Y1.IFF.SRTYPE.SYNC 28_60
@ -130,6 +133,7 @@ RIOI3.ILOGIC_Y1.ZINV_D 28_18
RIOI3.ILOGIC_Y1.IDELMUXE3.P0 28_26 RIOI3.ILOGIC_Y1.IDELMUXE3.P0 28_26
RIOI3.ILOGIC_Y1.IDELMUXE3.P1 !28_26 RIOI3.ILOGIC_Y1.IDELMUXE3.P1 !28_26
RIOI3.ILOGIC_Y1.IFFDELMUXE3.P0 29_11 RIOI3.ILOGIC_Y1.IFFDELMUXE3.P0 29_11
RIOI3.ILOGIC_Y1.IFFDELMUXE3.P1 !29_11
RIOI3.IOI_OCLK_0.IOI_LEAF_GCLK0 28_83 28_95 29_88 RIOI3.IOI_OCLK_0.IOI_LEAF_GCLK0 28_83 28_95 29_88
RIOI3.IOI_OCLK_0.IOI_LEAF_GCLK1 28_83 28_97 29_88 RIOI3.IOI_OCLK_0.IOI_LEAF_GCLK1 28_83 28_97 29_88
RIOI3.IOI_OCLK_0.IOI_LEAF_GCLK2 28_83 29_88 29_94 RIOI3.IOI_OCLK_0.IOI_LEAF_GCLK2 28_83 29_88 29_94

4
artix7/segbits_rioi3.origin_info.db
View File

@ -44,6 +44,7 @@ RIOI3.ILOGIC_Y0.IDDR.IN_USE origin:035b-iob-iserdes 26_121 26_71 27_70
RIOI3.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70 RIOI3.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70
RIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98 RIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98
RIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99 RIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99
RIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED origin:035-iob-ilogic !26_99 !27_98
RIOI3.ILOGIC_Y0.IFF.INV_OCLK origin:035-iob-ilogic 28_124 RIOI3.ILOGIC_Y0.IFF.INV_OCLK origin:035-iob-ilogic 28_124
RIOI3.ILOGIC_Y0.IFF.SRTYPE.ASYNC origin:035-iob-ilogic !29_67 RIOI3.ILOGIC_Y0.IFF.SRTYPE.ASYNC origin:035-iob-ilogic !29_67
RIOI3.ILOGIC_Y0.IFF.SRTYPE.SYNC origin:035-iob-ilogic 29_67 RIOI3.ILOGIC_Y0.IFF.SRTYPE.SYNC origin:035-iob-ilogic 29_67
@ -85,10 +86,12 @@ RIOI3.ILOGIC_Y0.ZINV_D origin:035-iob-ilogic 29_109
RIOI3.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101 RIOI3.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101
RIOI3.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101 RIOI3.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101
RIOI3.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116 RIOI3.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116
RIOI3.ILOGIC_Y0.IFFDELMUXE3.P1 origin:035-iob-ilogic !28_116
RIOI3.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56 RIOI3.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56
RIOI3.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56 RIOI3.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56
RIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29 RIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29
RIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28 RIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28
RIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED origin:035-iob-ilogic !26_29 !27_28
RIOI3.ILOGIC_Y1.IFF.INV_OCLK origin:035-iob-ilogic 29_03 RIOI3.ILOGIC_Y1.IFF.INV_OCLK origin:035-iob-ilogic 29_03
RIOI3.ILOGIC_Y1.IFF.SRTYPE.ASYNC origin:035-iob-ilogic !28_60 RIOI3.ILOGIC_Y1.IFF.SRTYPE.ASYNC origin:035-iob-ilogic !28_60
RIOI3.ILOGIC_Y1.IFF.SRTYPE.SYNC origin:035-iob-ilogic 28_60 RIOI3.ILOGIC_Y1.IFF.SRTYPE.SYNC origin:035-iob-ilogic 28_60
@ -130,6 +133,7 @@ RIOI3.ILOGIC_Y1.ZINV_D origin:035-iob-ilogic 28_18
RIOI3.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26 RIOI3.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26
RIOI3.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26 RIOI3.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26
RIOI3.ILOGIC_Y1.IFFDELMUXE3.P0 origin:035-iob-ilogic 29_11 RIOI3.ILOGIC_Y1.IFFDELMUXE3.P0 origin:035-iob-ilogic 29_11
RIOI3.ILOGIC_Y1.IFFDELMUXE3.P1 origin:035-iob-ilogic !29_11
RIOI3.IOI_OCLK_0.IOI_LEAF_GCLK0 origin:037-iob-pips 28_83 28_95 29_88 RIOI3.IOI_OCLK_0.IOI_LEAF_GCLK0 origin:037-iob-pips 28_83 28_95 29_88
RIOI3.IOI_OCLK_0.IOI_LEAF_GCLK1 origin:037-iob-pips 28_83 28_97 29_88 RIOI3.IOI_OCLK_0.IOI_LEAF_GCLK1 origin:037-iob-pips 28_83 28_97 29_88
RIOI3.IOI_OCLK_0.IOI_LEAF_GCLK2 origin:037-iob-pips 28_83 29_88 29_94 RIOI3.IOI_OCLK_0.IOI_LEAF_GCLK2 origin:037-iob-pips 28_83 29_88 29_94

4
artix7/segbits_rioi3_tbytesrc.db
View File

@ -44,6 +44,7 @@ RIOI3_TBYTESRC.ILOGIC_Y0.IDDR.IN_USE 26_71 26_121 27_70
RIOI3_TBYTESRC.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70 RIOI3_TBYTESRC.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70
RIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98 RIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98
RIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98 RIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98
RIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED !26_99 !27_98
RIOI3_TBYTESRC.ILOGIC_Y0.IFF.INV_OCLK 28_124 RIOI3_TBYTESRC.ILOGIC_Y0.IFF.INV_OCLK 28_124
RIOI3_TBYTESRC.ILOGIC_Y0.IFF.SRTYPE.ASYNC !29_67 RIOI3_TBYTESRC.ILOGIC_Y0.IFF.SRTYPE.ASYNC !29_67
RIOI3_TBYTESRC.ILOGIC_Y0.IFF.SRTYPE.SYNC 29_67 RIOI3_TBYTESRC.ILOGIC_Y0.IFF.SRTYPE.SYNC 29_67
@ -85,10 +86,12 @@ RIOI3_TBYTESRC.ILOGIC_Y0.ZINV_D 29_109
RIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P0 29_101 RIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P0 29_101
RIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P1 !29_101 RIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P1 !29_101
RIOI3_TBYTESRC.ILOGIC_Y0.IFFDELMUXE3.P0 28_116 RIOI3_TBYTESRC.ILOGIC_Y0.IFFDELMUXE3.P0 28_116
RIOI3_TBYTESRC.ILOGIC_Y0.IFFDELMUXE3.P1 !28_116
RIOI3_TBYTESRC.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56 RIOI3_TBYTESRC.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56
RIOI3_TBYTESRC.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56 RIOI3_TBYTESRC.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56
RIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28 RIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28
RIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28 RIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28
RIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED !26_29 !27_28
RIOI3_TBYTESRC.ILOGIC_Y1.IFF.INV_OCLK 29_03 RIOI3_TBYTESRC.ILOGIC_Y1.IFF.INV_OCLK 29_03
RIOI3_TBYTESRC.ILOGIC_Y1.IFF.SRTYPE.ASYNC !28_60 RIOI3_TBYTESRC.ILOGIC_Y1.IFF.SRTYPE.ASYNC !28_60
RIOI3_TBYTESRC.ILOGIC_Y1.IFF.SRTYPE.SYNC 28_60 RIOI3_TBYTESRC.ILOGIC_Y1.IFF.SRTYPE.SYNC 28_60
@ -130,6 +133,7 @@ RIOI3_TBYTESRC.ILOGIC_Y1.ZINV_D 28_18
RIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P0 28_26 RIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P0 28_26
RIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P1 !28_26 RIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P1 !28_26
RIOI3_TBYTESRC.ILOGIC_Y1.IFFDELMUXE3.P0 29_11 RIOI3_TBYTESRC.ILOGIC_Y1.IFFDELMUXE3.P0 29_11
RIOI3_TBYTESRC.ILOGIC_Y1.IFFDELMUXE3.P1 !29_11
RIOI3_TBYTESRC.IOI_OCLK_0.IOI_LEAF_GCLK0 28_83 28_95 29_88 RIOI3_TBYTESRC.IOI_OCLK_0.IOI_LEAF_GCLK0 28_83 28_95 29_88
RIOI3_TBYTESRC.IOI_OCLK_0.IOI_LEAF_GCLK1 28_83 28_97 29_88 RIOI3_TBYTESRC.IOI_OCLK_0.IOI_LEAF_GCLK1 28_83 28_97 29_88
RIOI3_TBYTESRC.IOI_OCLK_0.IOI_LEAF_GCLK2 28_83 29_88 29_94 RIOI3_TBYTESRC.IOI_OCLK_0.IOI_LEAF_GCLK2 28_83 29_88 29_94

4
artix7/segbits_rioi3_tbytesrc.origin_info.db
View File

@ -44,6 +44,7 @@ RIOI3_TBYTESRC.ILOGIC_Y0.IDDR.IN_USE origin:035b-iob-iserdes 26_121 26_71 27_70
RIOI3_TBYTESRC.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70 RIOI3_TBYTESRC.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70
RIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98 RIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98
RIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99 RIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99
RIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED origin:035-iob-ilogic !26_99 !27_98
RIOI3_TBYTESRC.ILOGIC_Y0.IFF.INV_OCLK origin:035-iob-ilogic 28_124 RIOI3_TBYTESRC.ILOGIC_Y0.IFF.INV_OCLK origin:035-iob-ilogic 28_124
RIOI3_TBYTESRC.ILOGIC_Y0.IFF.SRTYPE.ASYNC origin:035-iob-ilogic !29_67 RIOI3_TBYTESRC.ILOGIC_Y0.IFF.SRTYPE.ASYNC origin:035-iob-ilogic !29_67
RIOI3_TBYTESRC.ILOGIC_Y0.IFF.SRTYPE.SYNC origin:035-iob-ilogic 29_67 RIOI3_TBYTESRC.ILOGIC_Y0.IFF.SRTYPE.SYNC origin:035-iob-ilogic 29_67
@ -85,10 +86,12 @@ RIOI3_TBYTESRC.ILOGIC_Y0.ZINV_D origin:035-iob-ilogic 29_109
RIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101 RIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101
RIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101 RIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101
RIOI3_TBYTESRC.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116 RIOI3_TBYTESRC.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116
RIOI3_TBYTESRC.ILOGIC_Y0.IFFDELMUXE3.P1 origin:035-iob-ilogic !28_116
RIOI3_TBYTESRC.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56 RIOI3_TBYTESRC.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56
RIOI3_TBYTESRC.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56 RIOI3_TBYTESRC.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56
RIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29 RIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29
RIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28 RIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28
RIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED origin:035-iob-ilogic !26_29 !27_28
RIOI3_TBYTESRC.ILOGIC_Y1.IFF.INV_OCLK origin:035-iob-ilogic 29_03 RIOI3_TBYTESRC.ILOGIC_Y1.IFF.INV_OCLK origin:035-iob-ilogic 29_03
RIOI3_TBYTESRC.ILOGIC_Y1.IFF.SRTYPE.ASYNC origin:035-iob-ilogic !28_60 RIOI3_TBYTESRC.ILOGIC_Y1.IFF.SRTYPE.ASYNC origin:035-iob-ilogic !28_60
RIOI3_TBYTESRC.ILOGIC_Y1.IFF.SRTYPE.SYNC origin:035-iob-ilogic 28_60 RIOI3_TBYTESRC.ILOGIC_Y1.IFF.SRTYPE.SYNC origin:035-iob-ilogic 28_60
@ -130,6 +133,7 @@ RIOI3_TBYTESRC.ILOGIC_Y1.ZINV_D origin:035-iob-ilogic 28_18
RIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26 RIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26
RIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26 RIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26
RIOI3_TBYTESRC.ILOGIC_Y1.IFFDELMUXE3.P0 origin:035-iob-ilogic 29_11 RIOI3_TBYTESRC.ILOGIC_Y1.IFFDELMUXE3.P0 origin:035-iob-ilogic 29_11
RIOI3_TBYTESRC.ILOGIC_Y1.IFFDELMUXE3.P1 origin:035-iob-ilogic !29_11
RIOI3_TBYTESRC.IOI_OCLK_0.IOI_LEAF_GCLK0 origin:037-iob-pips 28_83 28_95 29_88 RIOI3_TBYTESRC.IOI_OCLK_0.IOI_LEAF_GCLK0 origin:037-iob-pips 28_83 28_95 29_88
RIOI3_TBYTESRC.IOI_OCLK_0.IOI_LEAF_GCLK1 origin:037-iob-pips 28_83 28_97 29_88 RIOI3_TBYTESRC.IOI_OCLK_0.IOI_LEAF_GCLK1 origin:037-iob-pips 28_83 28_97 29_88
RIOI3_TBYTESRC.IOI_OCLK_0.IOI_LEAF_GCLK2 origin:037-iob-pips 28_83 29_88 29_94 RIOI3_TBYTESRC.IOI_OCLK_0.IOI_LEAF_GCLK2 origin:037-iob-pips 28_83 29_88 29_94

4
artix7/segbits_rioi3_tbyteterm.db
View File

@ -44,6 +44,7 @@ RIOI3_TBYTETERM.ILOGIC_Y0.IDDR.IN_USE 26_71 26_121 27_70
RIOI3_TBYTETERM.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70 RIOI3_TBYTETERM.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70
RIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98 RIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98
RIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98 RIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98
RIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED !26_99 !27_98
RIOI3_TBYTETERM.ILOGIC_Y0.IFF.INV_OCLK 28_124 RIOI3_TBYTETERM.ILOGIC_Y0.IFF.INV_OCLK 28_124
RIOI3_TBYTETERM.ILOGIC_Y0.IFF.SRTYPE.ASYNC !29_67 RIOI3_TBYTETERM.ILOGIC_Y0.IFF.SRTYPE.ASYNC !29_67
RIOI3_TBYTETERM.ILOGIC_Y0.IFF.SRTYPE.SYNC 29_67 RIOI3_TBYTETERM.ILOGIC_Y0.IFF.SRTYPE.SYNC 29_67
@ -85,10 +86,12 @@ RIOI3_TBYTETERM.ILOGIC_Y0.ZINV_D 29_109
RIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P0 29_101 RIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P0 29_101
RIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P1 !29_101 RIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P1 !29_101
RIOI3_TBYTETERM.ILOGIC_Y0.IFFDELMUXE3.P0 28_116 RIOI3_TBYTETERM.ILOGIC_Y0.IFFDELMUXE3.P0 28_116
RIOI3_TBYTETERM.ILOGIC_Y0.IFFDELMUXE3.P1 !28_116
RIOI3_TBYTETERM.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56 RIOI3_TBYTETERM.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56
RIOI3_TBYTETERM.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56 RIOI3_TBYTETERM.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56
RIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28 RIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28
RIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28 RIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28
RIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED !26_29 !27_28
RIOI3_TBYTETERM.ILOGIC_Y1.IFF.INV_OCLK 29_03 RIOI3_TBYTETERM.ILOGIC_Y1.IFF.INV_OCLK 29_03
RIOI3_TBYTETERM.ILOGIC_Y1.IFF.SRTYPE.ASYNC !28_60 RIOI3_TBYTETERM.ILOGIC_Y1.IFF.SRTYPE.ASYNC !28_60
RIOI3_TBYTETERM.ILOGIC_Y1.IFF.SRTYPE.SYNC 28_60 RIOI3_TBYTETERM.ILOGIC_Y1.IFF.SRTYPE.SYNC 28_60
@ -130,6 +133,7 @@ RIOI3_TBYTETERM.ILOGIC_Y1.ZINV_D 28_18
RIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P0 28_26 RIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P0 28_26
RIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P1 !28_26 RIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P1 !28_26
RIOI3_TBYTETERM.ILOGIC_Y1.IFFDELMUXE3.P0 29_11 RIOI3_TBYTETERM.ILOGIC_Y1.IFFDELMUXE3.P0 29_11
RIOI3_TBYTETERM.ILOGIC_Y1.IFFDELMUXE3.P1 !29_11
RIOI3_TBYTETERM.IOI_OCLK_0.IOI_LEAF_GCLK0 28_83 28_95 29_88 RIOI3_TBYTETERM.IOI_OCLK_0.IOI_LEAF_GCLK0 28_83 28_95 29_88
RIOI3_TBYTETERM.IOI_OCLK_0.IOI_LEAF_GCLK1 28_83 28_97 29_88 RIOI3_TBYTETERM.IOI_OCLK_0.IOI_LEAF_GCLK1 28_83 28_97 29_88
RIOI3_TBYTETERM.IOI_OCLK_0.IOI_LEAF_GCLK2 28_83 29_88 29_94 RIOI3_TBYTETERM.IOI_OCLK_0.IOI_LEAF_GCLK2 28_83 29_88 29_94

4
artix7/segbits_rioi3_tbyteterm.origin_info.db
View File

@ -44,6 +44,7 @@ RIOI3_TBYTETERM.ILOGIC_Y0.IDDR.IN_USE origin:035b-iob-iserdes 26_121 26_71 27_70
RIOI3_TBYTETERM.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70 RIOI3_TBYTETERM.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70
RIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98 RIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98
RIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99 RIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99
RIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED origin:035-iob-ilogic !26_99 !27_98
RIOI3_TBYTETERM.ILOGIC_Y0.IFF.INV_OCLK origin:035-iob-ilogic 28_124 RIOI3_TBYTETERM.ILOGIC_Y0.IFF.INV_OCLK origin:035-iob-ilogic 28_124
RIOI3_TBYTETERM.ILOGIC_Y0.IFF.SRTYPE.ASYNC origin:035-iob-ilogic !29_67 RIOI3_TBYTETERM.ILOGIC_Y0.IFF.SRTYPE.ASYNC origin:035-iob-ilogic !29_67
RIOI3_TBYTETERM.ILOGIC_Y0.IFF.SRTYPE.SYNC origin:035-iob-ilogic 29_67 RIOI3_TBYTETERM.ILOGIC_Y0.IFF.SRTYPE.SYNC origin:035-iob-ilogic 29_67
@ -85,10 +86,12 @@ RIOI3_TBYTETERM.ILOGIC_Y0.ZINV_D origin:035-iob-ilogic 29_109
RIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101 RIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101
RIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101 RIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101
RIOI3_TBYTETERM.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116 RIOI3_TBYTETERM.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116
RIOI3_TBYTETERM.ILOGIC_Y0.IFFDELMUXE3.P1 origin:035-iob-ilogic !28_116
RIOI3_TBYTETERM.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56 RIOI3_TBYTETERM.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56
RIOI3_TBYTETERM.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56 RIOI3_TBYTETERM.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56
RIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29 RIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29
RIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28 RIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28
RIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED origin:035-iob-ilogic !26_29 !27_28
RIOI3_TBYTETERM.ILOGIC_Y1.IFF.INV_OCLK origin:035-iob-ilogic 29_03 RIOI3_TBYTETERM.ILOGIC_Y1.IFF.INV_OCLK origin:035-iob-ilogic 29_03
RIOI3_TBYTETERM.ILOGIC_Y1.IFF.SRTYPE.ASYNC origin:035-iob-ilogic !28_60 RIOI3_TBYTETERM.ILOGIC_Y1.IFF.SRTYPE.ASYNC origin:035-iob-ilogic !28_60
RIOI3_TBYTETERM.ILOGIC_Y1.IFF.SRTYPE.SYNC origin:035-iob-ilogic 28_60 RIOI3_TBYTETERM.ILOGIC_Y1.IFF.SRTYPE.SYNC origin:035-iob-ilogic 28_60
@ -130,6 +133,7 @@ RIOI3_TBYTETERM.ILOGIC_Y1.ZINV_D origin:035-iob-ilogic 28_18
RIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26 RIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26
RIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26 RIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26
RIOI3_TBYTETERM.ILOGIC_Y1.IFFDELMUXE3.P0 origin:035-iob-ilogic 29_11 RIOI3_TBYTETERM.ILOGIC_Y1.IFFDELMUXE3.P0 origin:035-iob-ilogic 29_11
RIOI3_TBYTETERM.ILOGIC_Y1.IFFDELMUXE3.P1 origin:035-iob-ilogic !29_11
RIOI3_TBYTETERM.IOI_OCLK_0.IOI_LEAF_GCLK0 origin:037-iob-pips 28_83 28_95 29_88 RIOI3_TBYTETERM.IOI_OCLK_0.IOI_LEAF_GCLK0 origin:037-iob-pips 28_83 28_95 29_88
RIOI3_TBYTETERM.IOI_OCLK_0.IOI_LEAF_GCLK1 origin:037-iob-pips 28_83 28_97 29_88 RIOI3_TBYTETERM.IOI_OCLK_0.IOI_LEAF_GCLK1 origin:037-iob-pips 28_83 28_97 29_88
RIOI3_TBYTETERM.IOI_OCLK_0.IOI_LEAF_GCLK2 origin:037-iob-pips 28_83 29_88 29_94 RIOI3_TBYTETERM.IOI_OCLK_0.IOI_LEAF_GCLK2 origin:037-iob-pips 28_83 29_88 29_94

2
kintex7/segbits_int_l.db
View File

@ -3634,3 +3634,5 @@ INT_L.WW4BEG3.SW2END2 02_49 04_49
INT_L.WW4BEG3.SW6END2 04_49 05_48 INT_L.WW4BEG3.SW6END2 04_49 05_48
INT_L.WW4BEG3.WW2END2 03_48 03_49 INT_L.WW4BEG3.WW2END2 03_48 03_49
INT_L.WW4BEG3.WW4END3 03_49 05_48 INT_L.WW4BEG3.WW4END3 03_49 05_48
INT_L.IOB_COL_BANK_ACTIVE 38_012 38_032 38_034
INT_L.IOB_COL_OBUF_CASCADE_Y1 30_041 32_016 33_061

2
kintex7/segbits_int_l.origin_info.db
View File

@ -3634,3 +3634,5 @@ INT_L.WW4BEG3.SW2END2 origin:050-pip-seed 02_49 04_49
INT_L.WW4BEG3.SW6END2 origin:050-pip-seed 04_49 05_48 INT_L.WW4BEG3.SW6END2 origin:050-pip-seed 04_49 05_48
INT_L.WW4BEG3.WW2END2 origin:050-pip-seed 03_48 03_49 INT_L.WW4BEG3.WW2END2 origin:050-pip-seed 03_48 03_49
INT_L.WW4BEG3.WW4END3 origin:050-pip-seed 03_49 05_48 INT_L.WW4BEG3.WW4END3 origin:050-pip-seed 03_49 05_48
INT_L.IOB_COL_BANK_ACTIVE origin:virtex7-arch-mirror 38_012 38_032 38_034
INT_L.IOB_COL_OBUF_CASCADE_Y1 origin:virtex7-arch-mirror 30_041 32_016 33_061

2
kintex7/segbits_int_r.db
View File

@ -3634,3 +3634,5 @@ INT_R.WW4BEG3.SW2END2 02_49 04_49
INT_R.WW4BEG3.SW6END2 04_49 05_48 INT_R.WW4BEG3.SW6END2 04_49 05_48
INT_R.WW4BEG3.WW2END2 03_48 03_49 INT_R.WW4BEG3.WW2END2 03_48 03_49
INT_R.WW4BEG3.WW4END3 03_49 05_48 INT_R.WW4BEG3.WW4END3 03_49 05_48
INT_R.IOB_COL_BANK_ACTIVE 38_012 38_032 38_034
INT_R.IOB_COL_OBUF_CASCADE_Y1 30_041 32_016 33_061

2
kintex7/segbits_int_r.origin_info.db
View File

@ -3634,3 +3634,5 @@ INT_R.WW4BEG3.SW2END2 origin:050-pip-seed 02_49 04_49
INT_R.WW4BEG3.SW6END2 origin:050-pip-seed 04_49 05_48 INT_R.WW4BEG3.SW6END2 origin:050-pip-seed 04_49 05_48
INT_R.WW4BEG3.WW2END2 origin:050-pip-seed 03_48 03_49 INT_R.WW4BEG3.WW2END2 origin:050-pip-seed 03_48 03_49
INT_R.WW4BEG3.WW4END3 origin:050-pip-seed 03_49 05_48 INT_R.WW4BEG3.WW4END3 origin:050-pip-seed 03_49 05_48
INT_R.IOB_COL_BANK_ACTIVE origin:virtex7-arch-mirror 38_012 38_032 38_034
INT_R.IOB_COL_OBUF_CASCADE_Y1 origin:virtex7-arch-mirror 30_041 32_016 33_061

13
kintex7/segbits_riob18.db
View File

@ -60,3 +60,16 @@ RIOB18.IOB_Y1.SSTL15.SLEW.FAST !38_38 !38_46 38_14 38_16 38_22 38_26 38_50 39_13
RIOB18.IOB_Y1.SSTL15.SLEW.SLOW !38_14 !38_16 !38_22 !38_26 !39_13 38_38 38_46 38_50 39_45 RIOB18.IOB_Y1.SSTL15.SLEW.SLOW !38_14 !38_16 !38_22 !38_26 !39_13 38_38 38_46 38_50 39_45
RIOB18.IOB_Y1.ZIBUF_LOW_PWR 38_02 RIOB18.IOB_Y1.ZIBUF_LOW_PWR 38_02
RIOB18.OUT_DIFF 39_17 39_43 RIOB18.OUT_DIFF 39_17 39_43
RIOB18.IOB_Y0.IBUFDS_BANK_GLUE 38_008 38_028 38_040 39_015 39_021 39_037 39_041
RIOB18.IOB_Y0.LVCMOS12_LVCMOS15.IN !39_01 38_126 39_127
RIOB18.IOB_Y0.LVCMOS12_LVCMOS15_SSTL12_SSTL135_SSTL15.IN_ONLY !38_104 !38_72 !38_86 !39_73 !39_83 !39_93 !39_95 !39_97 38_78 38_80 38_94 39_103 39_79
RIOB18.IOB_Y0.LVDS.IN_DIFF !38_126 !39_127 39_01
RIOB18.IOB_Y0.SSTL12_SSTL135_SSTL15.IN_DIFF !39_127 38_126 39_01
RIOB18.IOB_Y1.SSTL12_SSTL135_SSTL15.IN_DIFF 38_00 38_126 39_01
RIOB18.IOB_Y1.LVCMOS12_LVCMOS15_SSTL12_SSTL135_SSTL15.IN_ONLY !38_30 !38_44 !39_23 !39_55 38_24 38_48 39_33 39_47 39_49
RIOB18.IOB_Y0.OBUF_HP_BANK_GLUE 31_086 32_066 33_111
RIOB18.IOB_Y1.OBUF_HP_BANK_GLUE 30_041 32_016 33_061
RIOB18.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW !38_114 !38_82 !39_101 !39_105 !39_111 !39_113 !39_77 !39_81 !39_89
RIOB18.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW !38_14 !38_16 !38_22 !38_26 !38_38 !38_46 !38_50 !39_13 !39_45
RIOB18.IOB_Y1.IBUF_HP_BANK_GLUE 29_109
RIOB18.IOB_Y1.LVCMOS12_LVCMOS15.IN 38_00 39_01

13
kintex7/segbits_riob18.origin_info.db
View File

@ -60,3 +60,16 @@ RIOB18.IOB_Y1.SSTL15.SLEW.FAST origin:030-iob18 !38_38 !38_46 38_14 38_16 38_22
RIOB18.IOB_Y1.SSTL15.SLEW.SLOW origin:030-iob18 !38_14 !38_16 !38_22 !38_26 !39_13 38_38 38_46 38_50 39_45 RIOB18.IOB_Y1.SSTL15.SLEW.SLOW origin:030-iob18 !38_14 !38_16 !38_22 !38_26 !39_13 38_38 38_46 38_50 39_45
RIOB18.IOB_Y1.ZIBUF_LOW_PWR origin:030-iob18 38_02 RIOB18.IOB_Y1.ZIBUF_LOW_PWR origin:030-iob18 38_02
RIOB18.OUT_DIFF origin:030-iob18 39_17 39_43 RIOB18.OUT_DIFF origin:030-iob18 39_17 39_43
RIOB18.IOB_Y0.IBUFDS_BANK_GLUE origin:virtex7-arch-mirror 38_008 38_028 38_040 39_015 39_021 39_037 39_041
RIOB18.IOB_Y0.LVCMOS12_LVCMOS15.IN origin:virtex7-arch-mirror !39_01 38_126 39_127
RIOB18.IOB_Y0.LVCMOS12_LVCMOS15_SSTL12_SSTL135_SSTL15.IN_ONLY origin:virtex7-arch-mirror !38_104 !38_72 !38_86 !39_73 !39_83 !39_93 !39_95 !39_97 38_78 38_80 38_94 39_103 39_79
RIOB18.IOB_Y0.LVDS.IN_DIFF origin:virtex7-arch-mirror !38_126 !39_127 39_01
RIOB18.IOB_Y0.SSTL12_SSTL135_SSTL15.IN_DIFF origin:virtex7-arch-mirror !39_127 38_126 39_01
RIOB18.IOB_Y1.SSTL12_SSTL135_SSTL15.IN_DIFF origin:virtex7-arch-mirror 38_00 38_126 39_01
RIOB18.IOB_Y1.LVCMOS12_LVCMOS15_SSTL12_SSTL135_SSTL15.IN_ONLY origin:kintex7-y1-in-only-mirror !38_30 !38_44 !39_23 !39_55 38_24 38_48 39_33 39_47 39_49
RIOB18.IOB_Y0.OBUF_HP_BANK_GLUE origin:liob18-arch-mirror 31_086 32_066 33_111
RIOB18.IOB_Y1.OBUF_HP_BANK_GLUE origin:liob18-arch-mirror 30_041 32_016 33_061
RIOB18.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW origin:liob18-arch-mirror !38_114 !38_82 !39_101 !39_105 !39_111 !39_113 !39_77 !39_81 !39_89
RIOB18.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW origin:liob18-arch-mirror !38_14 !38_16 !38_22 !38_26 !38_38 !38_46 !38_50 !39_13 !39_45
RIOB18.IOB_Y1.IBUF_HP_BANK_GLUE origin:liob18-arch-mirror-verify 29_109
RIOB18.IOB_Y1.LVCMOS12_LVCMOS15.IN origin:kintex7-y1-in-mirror 38_00 39_01

2
kintex7/xc7k160t/tilegrid.json
View File

@ -734807,7 +734807,7 @@
"type": "RIOI" "type": "RIOI"
}, },
"RIOI_X73Y9": { "RIOI_X73Y9": {
"bits": {}, "bits": {"CLB_IO_CLK": {"baseaddr": "0x00442480", "frames": 42, "offset": 18, "words": 4}},
"clock_region": "X1Y0", "clock_region": "X1Y0",
"grid_x": 188, "grid_x": 188,
"grid_y": 250, "grid_y": 250,

2
kintex7/xc7k325t/tilegrid.json
View File

@ -1335306,7 +1335306,7 @@
"type": "RIOI" "type": "RIOI"
}, },
"RIOI_X95Y9": { "RIOI_X95Y9": {
"bits": {}, "bits": {"CLB_IO_CLK": {"baseaddr": "0x00442F80", "frames": 42, "offset": 18, "words": 4}},
"clock_region": "X1Y0", "clock_region": "X1Y0",
"grid_x": 235, "grid_x": 235,
"grid_y": 354, "grid_y": 354,

1
virtex7/segbits_riob18.db
View File

@ -66,3 +66,4 @@ RIOB18.IOB_Y1.SSTL15.SLEW.FAST !38_38 !38_46 38_14 38_16 38_22 38_26 38_50 39_13
RIOB18.IOB_Y1.SSTL15.SLEW.SLOW !38_14 !38_16 !38_22 !38_26 !39_13 38_38 38_46 38_50 39_45 RIOB18.IOB_Y1.SSTL15.SLEW.SLOW !38_14 !38_16 !38_22 !38_26 !39_13 38_38 38_46 38_50 39_45
RIOB18.IOB_Y1.ZIBUF_LOW_PWR 38_02 RIOB18.IOB_Y1.ZIBUF_LOW_PWR 38_02
RIOB18.OUT_DIFF 39_17 39_43 RIOB18.OUT_DIFF 39_17 39_43
RIOB18.IOB_Y1.LVCMOS12_LVCMOS15.IN 38_00 39_01

1
virtex7/segbits_riob18.origin_info.db
View File

@ -71,3 +71,4 @@ RIOB18.IOB_Y1.SSTL15.SLEW.FAST origin:030-iob18 !38_38 !38_46 38_14 38_16 38_22
RIOB18.IOB_Y1.SSTL15.SLEW.SLOW origin:030-iob18 !38_14 !38_16 !38_22 !38_26 !39_13 38_38 38_46 38_50 39_45 RIOB18.IOB_Y1.SSTL15.SLEW.SLOW origin:030-iob18 !38_14 !38_16 !38_22 !38_26 !39_13 38_38 38_46 38_50 39_45
RIOB18.IOB_Y1.ZIBUF_LOW_PWR origin:030-iob18 38_02 RIOB18.IOB_Y1.ZIBUF_LOW_PWR origin:030-iob18 38_02
RIOB18.OUT_DIFF origin:030-iob18 39_17 39_43 RIOB18.OUT_DIFF origin:030-iob18 39_17 39_43
RIOB18.IOB_Y1.LVCMOS12_LVCMOS15.IN origin:kintex7-y1-in-mirror 38_00 39_01