Files
openFPGALoader/spiOverJtag
Gwenhael Goavec-Merou 6c4a48f445 spiOverJtag: reworks Artix and Spartan 7 approach:
For a specific FPGA size, pins name is only a matter of package,
 internally physical pads are the same: a unique bitstream per size is
 necessary. This also simplify build.py by removing complexity to
 extract model, size and package.

 - a dict is added with supported packages per size
 - only one bitstream is produces for artix/spartan7 size, package+size bitstreams are only symlinks.
 - constraints files are also updated with BSCANE2/DRCK clocks constraints
 - the gz is produces by build.py instead of by the Makefile
 - all possibles bitstreams for XC7A/XC7S are now present.
2025-05-26 09:53:25 +02:00
..
2023-04-27 16:41:17 +02:00
2023-04-27 16:41:17 +02:00