b119a955a6
gowin: GW5A SPI flash support
2023-11-19 13:29:15 +01:00
a5f2aa56c8
gowin: displayReadReg update. Now GW5A field are correctly displayed
2023-11-19 10:25:06 +01:00
31c89e21a3
gowin: detectFamily new function
2023-11-19 10:18:45 +01:00
1cbdee362d
jtag,main: fix warnings
2023-11-19 10:17:54 +01:00
7059c15960
Add user device list for non-fpga JTAG devices
2023-11-10 14:00:24 -07:00
63c1950f2f
Add xc7k70t and small fixes for xc7k160t
2023-11-09 07:45:46 +07:00
1a86fa21ae
Merge pull request #399 from bg-gsl/fix_lattice_bscan_nexus
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Fix lattice bscan nexus in clearSRAM()
2023-11-08 12:47:34 +01:00
fa5ff873e4
lattice.cpp: restore bypass instruction in clearSRAM()
2023-11-08 09:49:14 +01:00
f71858f96a
Rewrite GOWIN algorithms
2023-10-29 08:07:48 +01:00
790d2bccab
fsParser: adding GW5A-25 IDCODE
2023-10-29 07:02:12 +01:00
59b56bcc95
all jtag cable: no more hardcoding tdi bit with writeTMS
2023-10-29 06:41:39 +01:00
43ae0d8fdd
ftdiJtagMPSSE,jtagInterface: {set|get}{Read|Write}Edge signature
2023-10-29 06:12:09 +01:00
46ce2e61a7
ALINX AX7101 board.
2023-10-28 17:22:42 +02:00
d58a1c3fc7
lattice: correct mask for sram erase for NEXUS_FAMILY, as it is 0x00
2023-10-26 11:30:24 +02:00
917e42127b
lattice: fix bscan register initialization inside clearSRAM()
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For NEXUS family fpgas, the Bscan register is 362 bits long
or 45.25 bytes => 46 bytes.
This error was already correct when programming the sram.
clearSRAM() is instead used when programming the spi flash memory.
2023-10-25 17:43:49 +02:00
a87d689d83
ALINX AX7102 board.
2023-10-24 14:03:18 +02:00
fd8497026a
ftdiJtagMPSSE,jtag,jtagInterface: allows to force read/write edge configuration (useful to mimic SPI through JTAG)
2023-10-24 07:26:19 +02:00
b76a67963e
board: SiPEED tang Mega 138K
2023-10-24 06:11:53 +02:00
9a2fe6e157
board: SiPEED tang Primer 25K
2023-10-24 06:07:42 +02:00
988bedefb6
lattice: fix typo / warning
2023-10-23 07:12:45 +02:00
590611a8d5
lattice: fix the warning "left shift count >= width of type" shown in win32/64 builds
2023-10-20 08:44:20 +02:00
bab386911a
spi flash: add mapping for Micron MT25/N25Q128_1_8V (Lattice Certus Versa and CertusPro eval boards) and distinguish between N25Q128 1.8V and 3V memories
2023-10-20 07:57:56 +02:00
940da5fb2b
spi flash: add mapping for Macronix MX25L51245G (CertusPro Versa board and gr740-mini)
2023-10-20 07:55:53 +02:00
5f6074a7fc
lattice: fix bscan width and other minor things for NEXUS family
2023-10-20 07:55:53 +02:00
dce0c050a7
board: add gr740-mini
2023-10-20 07:55:53 +02:00
2754e99215
cable: add FTDI FT4232HP mapping
2023-10-20 07:55:53 +02:00
0bbf817c92
part: fix typo
2023-10-19 17:46:50 +02:00
32ef0bd29c
Adding xcku115 to parts list ( #394 )
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* Adding xcku115 to parts list
* Adding xcku115 to list of supported FPGAs
---------
Co-authored-by: Stephen Goadhouse <stephen.david.goadhouse@cern.ch>
2023-10-19 17:45:42 +02:00
dafe350fbe
lattice nexus family: REFRESH (plus config logic reset) in case of fpga in error state and add capabilities to handle the whole 64-bits status register
2023-10-12 09:06:54 +02:00
5733ca29c3
fix lattice programming and add nexus boards
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Fix to lattice programming:
we considered a svf file generated by Lattice Radiant-Programmer
and compared it with the current way lattice devices were programmed.
There were few differences dealing with configuration reset and REFRESH.
These fixes allow us to program an fpga when it is in a state
of error (e.g. there's no bitstream in the SPI Flash).
Lattice parts added:
- CertusPro FPGA
Nexus boards added:
- Certus Versa Evaluation board
- CertusPro Evaluation board
- CertusPro Versa Evaluation board
2023-10-11 09:52:45 +02:00
ec35f15a51
altera,efinix,gowin,xilinx: Fix 'Flash SRAM' -> 'Load SRAM'
2023-10-09 14:53:57 +02:00
18056180a8
gatemate: do not call ftdi-related routines when using alternative cables
2023-10-04 15:41:10 +02:00
ad5ada90db
board: trion_t20_bga256_jtag support
2023-10-03 06:51:38 +02:00
e9b31425d6
cable: efinix jtag ft2232 variant
2023-10-03 06:48:47 +02:00
c0ad3225cc
Add support for Xilinx xczu17eg. It's tested on xczu17eg board with Digilent HS3 at 30Mbps.
2023-09-22 19:33:01 -07:00
c82a8e6207
Make CH347 driver faster
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Speed up toggleClk
Defer write-only USB transactions to better utilize bus
2023-09-22 07:08:48 +02:00
67159e8297
Move JTAG chain bit init to device_select()
2023-09-22 07:05:20 +02:00
4c39abf51c
Add missing pieces to JTAG
2023-09-22 07:01:48 +02:00
85f9791600
drop div_by_5 to allow 2.5MHz clock
2023-09-22 06:55:21 +02:00
01ac90a172
[xilinx] add jtag->flush before sleep
2023-09-21 07:38:25 +02:00
b10be9ae8a
properly fill dummy arrays
2023-09-21 07:36:41 +02:00
d3410e0e30
Update JTAG chain detect
2023-09-21 07:33:54 +02:00
afbf0c4ff8
board: adding @lambdaconcept ecpix5_r03 (ft4232)
2023-09-21 06:24:30 +02:00
6c16417ee9
Merge UPDATE_DR and UPDATE_IR handling in JTAG state machines
2023-09-20 07:59:34 +02:00
6a0de15bff
Parse LoadingRate field
2023-09-20 07:58:06 +02:00
0c89ac9a44
Add GD32VF103 to misc devices
2023-09-20 07:48:21 +02:00
94b62460c5
jtag: shiftDR: (fix daisy chain) when more than one FPGA, a sequence of '0' before and/or after must be sent instead of '1' ( fix #189 and #133
2023-09-17 08:59:26 +02:00
9810735e32
jtag: rework detectChain: try unmasked idcode first
2023-09-14 21:53:27 +02:00
57fc9bcb6f
part: machXO3: re-add partially revision
2023-09-14 21:52:53 +02:00
5e9cc7c440
pass along reset paramaters to provide control to the caller
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Upsteam-Status: Submitted [https://github.com/traucucayre/openFPGALoader ]
- Submitted to upstream, waiting approval
2023-09-10 20:46:08 -07:00
Gwenhael Goavec-Merou
Mark Featherston
Hans Baier
Giovanni Bruni
Alexey Starikovskiy
Haakan T Johansson
sgoadhouse
Patrick Urban
Zhongyi Chen
Rodrigo Rengifo