65a1e995ec
xilinx: be more verbose when spiOverJtag not available
2021-04-19 21:08:11 +02:00
858d9e6273
add support for Alchitry Au
2021-04-16 21:20:30 +02:00
4defec0db1
add support for artix 7 75t
2021-04-15 15:38:36 +02:00
4e2b1aa73e
cable: add SecuringHardware Tigard programmer
2021-03-27 18:43:56 +01:00
32d3872f69
part.hpp: sort altera cyclone V device by alphabetical order
2021-03-27 18:31:39 +01:00
508635f788
Merge pull request #80 from emard/master
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recognize altera cyclone V 5CEBA4 FPGA
2021-03-27 18:30:28 +01:00
fa70a9a3b2
part.hpp: sort xilinx device by alphabetical order
2021-03-27 18:25:52 +01:00
52efdab421
recognize altera cyclone V 5CEBA4 FPGA
2021-03-27 02:00:18 +01:00
16f85fff63
add support for kintex xc7k325t
2021-03-24 17:25:05 +01:00
f33d30dbce
main: fix bitbang check: config pins must be the shift value
2021-03-21 18:51:13 +01:00
630a976884
add support for cycloneIII and Terasic DE0 board
2021-03-20 12:23:17 +01:00
ea141fdcfe
Remove spurious files in previous commit
2021-02-27 13:25:22 -08:00
e9b1a2e610
fix for space
2021-02-27 13:19:25 -08:00
6e96d8f6d0
Conditionalization of ftdi_tcioflush
2021-02-27 13:12:21 -08:00
5d8ec9a162
Attempt to satisfy a comment from the owner
2021-02-27 12:45:12 -08:00
fdd1037d46
Remove temporary support for a hypotetical version based on Teensy 4
2021-02-27 11:35:45 -08:00
94ef653682
Resolved bunch of comments from owner
2021-02-27 10:37:07 -08:00
9ee8e84fba
Support for new DirtyJtag2 protocol. Merged with head
2021-02-27 09:59:38 -08:00
43caa612ca
lattice: drop the limitation, for .bin, to write at offset > 0
2021-02-27 06:49:42 +01:00
6d1c51d0a4
fix purge buffer fix libftdi >= 1.5
...
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
2021-02-25 13:37:33 +01:00
566d33c2f1
progressBar: use chrono instead of clock
2021-02-24 13:31:55 +01:00
16932786db
all parser:
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- _raw_data is now filled in configBitstreamParser
- source may be a file or a pipe
- displayHeader become a common method (configBitstreamParser)
- improve/rewrite some parser (efinixHexparser 1s -> 11ms)
2021-02-24 06:36:48 +01:00
e27da3276f
Merge pull request #75 from Disasm/add-gw1ns-2c
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Add support for GW1NS-2C FPGA chips
2021-02-21 18:48:16 +01:00
df52d523bf
All devices: new CLI argument to bypass file type autodetection
2021-02-21 18:30:13 +01:00
d226ab7671
Add support for GW1NS-2C FPGA chips
2021-02-21 17:31:09 +03:00
7cc5676e8e
ftdi: drop divide_by_5 param, now it's automatically set/unset according to the frequency. Better freq display
2021-02-19 07:07:10 +01:00
5f9a8835da
devices: simplify write RAM/Flash
2021-02-18 21:09:34 +01:00
48e65fa0ad
bitparser: drop garbage characters, use _hdr, best header parsing and display
2021-02-17 19:02:57 +01:00
4a555bb102
dfuFileParser: parser for bitstream with DFU suffix
2021-02-15 07:33:58 +01:00
590553e432
src/fsparser: rewrite to use header instead of comments, add support for compressed bitstream
2021-02-12 07:34:14 +01:00
210bdac09a
configBitstreamParser: external access to header keys/values
2021-02-10 08:02:20 +01:00
e91c251eb0
svf_jtag: suppress CR when file is in DOS format
2021-02-08 06:31:56 +01:00
d4692d5049
rawParser: typo
2021-02-06 11:42:50 +01:00
1545b99748
rawParser: use raw_data buffer
2021-02-06 11:36:34 +01:00
f6c036f1c0
anlogicBitParser: use _raw_data and work with this one instead of file descriptor
2021-02-06 11:29:32 +01:00
5c49b1465a
all cable: always display real used frequency
2021-02-05 06:28:19 +01:00
582261c758
xilinx: allow bin file to memory
2021-02-04 07:29:35 +01:00
ad21a3bb36
recast verbose to int8_t to have more level of verbosity (-1 quiet, 0 normal, 1 verbose), add --quiet option, display progress bar when verbosity level >= 0
2021-01-30 07:57:49 +01:00
1992360667
main: catch exception if FPGA can't be claimed.
2021-01-29 06:19:42 +01:00
956d506bf7
fsparser: display warning message for missing or unknown idcode
2021-01-28 07:23:38 +01:00
71c4b32202
display: add warning message
2021-01-28 07:22:24 +01:00
dbc78f8c57
add seeedstudio runber (gowin GW1N-4)
2021-01-28 06:19:43 +01:00
502546fcfc
fsparser: add missing GW1N-4(ES) idcode
2021-01-28 06:07:51 +01:00
60800ee1a6
board: add entry for tec0117
2021-01-25 18:52:54 +01:00
883268be25
efinixHexParser: use _raw_data instead of custom buffer
2021-01-24 18:21:47 +01:00
46beaea14d
configBitstreamParser: introduce a buffer for unprocessed file content
2021-01-24 18:16:09 +01:00
cd625d4c99
add efinix Xyloni support (spi mode only)
2021-01-21 07:11:10 +01:00
0e5e609b34
ftdipp_mpsse: don't configures high bytes for devices with only one bank per channel
2021-01-21 06:57:35 +01:00
717870e18b
Made last_time a private member of the ProgressBar class per code review comment.
2020-12-28 09:33:35 -08:00
11baca9337
limit the progressBar update rate to 5 per second. This speeds up loading of small bin files.
2020-12-26 09:50:48 -08:00
6fefebd02c
prepare release v0.2.1
2020-12-17 13:58:30 +01:00
1b065277f9
add acorn CLE 215+ support
2020-12-17 09:28:45 +01:00
6e44797677
add fairwaves xtrx pro board
2020-12-15 09:47:10 +01:00
54b31651f3
xilinx: since xilinx generates bin file, drop limitation about flash start offset
2020-12-15 09:46:47 +01:00
a11ec92a25
Fix gcc 10.2 error messages.
2020-12-12 15:48:45 -08:00
922d3b0b56
xilinx: add xca50t support
2020-12-08 07:32:30 +01:00
ed7e9340ba
lattice: add a memset to avoid valgrind warn
2020-11-27 08:29:09 +01:00
88522b0e91
ftdiJtagBitbang: quick fix to avoid overflow in writeTDI
2020-11-26 09:26:08 +01:00
bec5e4f35c
add xc7s25 support
2020-11-18 08:15:15 +01:00
14c5b8e681
add support for ice40 FPGA and iCEBreaker, icestick, iCE40-HX8K, iCE40-HX1K-EVN boards
2020-10-31 15:02:54 +01:00
818dbd301c
ftdipp_mpsse: reduce useless write
2020-10-31 11:10:14 +01:00
7e15b5cabb
board: Fireant support
2020-10-31 10:44:44 +01:00
6aa2176be1
board: typo
2020-10-31 10:44:14 +01:00
537f02fa89
board: fix control pins size
2020-10-31 10:43:45 +01:00
14b7122b4d
ftdispi: fix control size
2020-10-31 10:42:40 +01:00
aa23aff388
main: review SPI mode for efinix active mode
2020-10-31 10:41:44 +01:00
70fb5c8439
add efinix support
2020-10-31 10:39:06 +01:00
3c9870bba3
introduce CBUS/DBUS pins value, add macro and pin mapping for board in SPI mode, reset and done signals
2020-10-31 08:40:18 +01:00
fe8cd9998d
board: simplify board definition using preprocessor macro
2020-10-31 08:04:43 +01:00
1bc20fee85
ftdispi: cleanup + fix + add support for wpn and holdn pins
2020-10-31 07:45:30 +01:00
deefcd2d38
ftdipp_mpsse: update direction method
2020-10-31 07:38:06 +01:00
b2abafa76d
ftdispi: start to use spi_pins_conf
2020-10-30 08:26:15 +01:00
e347d2afd6
board: add spi_pins_conf structure
2020-10-30 08:23:49 +01:00
b0f73aa8d9
ftdipp_mpsse: add method to configure individually pins direction
2020-10-30 08:18:38 +01:00
2398ee1445
part: add LCMXO2-640HC
2020-10-29 08:24:30 +01:00
88c6b2ff6d
Improve FTDI communication in bitbang mode
...
sub layer cut package in allowed size, so it's not mandatory to do this
at openFPGALoader level. The only situation when the size is important
is in read mode. So increase buffer size to reduce system calls.
2020-10-29 08:15:32 +01:00
e0a5d376ba
ftdipp_mpsse: change VID/PID visibility
2020-10-29 07:40:56 +01:00
f75a7f8395
ftdiJtagBitbang: some cleanup and reuse parent class buffer
2020-10-29 07:39:47 +01:00
78ea8ac808
ftdipp_mpsse: change _buffer visibility
2020-10-29 07:39:07 +01:00
09c28c23a7
ftdispi: cleanup
2020-10-28 21:26:33 +01:00
05e1c57cc5
ftdipp_mpsse: add method to update pins direction
2020-10-28 19:48:59 +01:00
ed006711b7
ftdipp_mpsse: introduce gpio bitbanging with MPSSE
2020-10-28 07:58:33 +01:00
b3a67f896f
ftdipp_mpsse: store cable configuration
2020-10-27 20:27:02 +01:00
4dde89e082
Merge remote-tracking branch 'origin/review_usb_transaction'
2020-10-27 19:29:44 +01:00
5254116ad8
main: if board has no default cable, don't override potential user choise
2020-10-25 16:51:21 +01:00
f22b25428d
main: allow users board cable to be override
2020-10-21 13:41:26 +02:00
2170a2af86
altera: add support for RBF (only tested with SRAM)
2020-10-17 18:40:16 +02:00
15e9907655
add cycloneV E support and QMTech CycloneV board
2020-10-17 15:45:00 +02:00
717d5065b4
ftdiJtagMPSSE: use correct size for ch552 dummy buffer
2020-10-17 15:44:21 +02:00
04df474e12
Merge pull request #56 from GbGp/master
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add support for artix-7 200t and nexys video board
2020-10-16 19:10:10 +02:00
a874a51be3
Fix part name typo
2020-10-16 08:08:44 +02:00
fbb8c58f46
Add MachXO3D Development Board Support
2020-10-16 08:03:45 +02:00
edad461d88
add support for artix-7 200t and nexys video board
2020-10-15 16:07:55 +02:00
235505c660
gowin:
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- increase delay before checking CRC
- fix message
2020-10-12 15:34:50 +02:00
adb6efca39
ftdiJtagMPSSE: don't flush/write everytime
2020-10-09 21:30:45 +02:00
23c9733a6d
gowin: force flush when it's mandatory
2020-10-09 21:29:48 +02:00
da65579d0d
jtag: don't force flush everywhere
2020-10-09 21:28:00 +02:00
06d0e44f71
gowin: eraseFLASH(): fix buffer size, set this to 0
2020-10-09 21:22:03 +02:00
a27c99376d
ftdiJtagMPSSE: don't use MPSSE_DO_WRITE for read only transaction
2020-10-09 21:17:04 +02:00
487bc21d66
Fix fsparser:
...
- first bit in header lines maybe be 0 or 1 depending on crc_check
- data line length depend on crc_check too. Instead of trying to deduce
length, use idcode to have this.
2020-10-09 19:26:50 +02:00
Gwenhael Goavec-Merou
emard
Giuseppe Gebbia
phdussud
Vadim Kaushan
Francisco Ayala Le Brun