add cycloneV E support and QMTech CycloneV board

README.md

@@ -13,6 +13,7 @@ __Current support kits:__
 * [Lattice MachXO3D Development Board (LCMXO3D-9400HC)](https://www.latticesemi.com/products/developmentboardsandkits/machxo3d_development_board)
 * [Lattice CrossLink-NX Evaluation Board (LIFCL-40-EVN)](https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/CrossLink-NXEvaluationBoard) (memory and spi flash)
 * [Lattice ECP5 5G Evaluation Board (LFE5UM5G-85F-EVN)](https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/ECP5EvaluationBoard) (memory and spi flash)
+* [QMTech CycloneV Core Board](https://fr.aliexpress.com/i/1000006622149.html) (memory)
 * [Trenz Gowin LittleBee (TEC0117)](https://shop.trenz-electronic.de/en/TEC0117-01-FPGA-Module-with-GOWIN-LittleBee-and-8-MByte-internal-SDRAM)
 * [Saanlima Pipistrello LX45](http://pipistrello.saanlima.com/index.php?title=Welcome_to_Pipistrello) (memory)
 * [SeeedStudio Spartan Edge Accelerator Board](http://wiki.seeedstudio.com/Spartan-Edge-Accelerator-Board) (memory)
@@ -34,6 +35,7 @@ __Supported (tested) FPGA:__
 * Xilinx Spartan 6 [xc6slx45](https://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html) (memory)
 * Xilinx Spartan 7 [xc7s15, xc7s50](https://www.xilinx.com/products/silicon-devices/fpga/spartan-7.html) (memory (all) and spi flash (xc7s50))
 * Intel Cyclone IV CE [EP4CE22](https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iv/features.html) (memory. See note below)
+* Intel Cyclone V E [5CEA2](https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-v.html)
 * Intel Cyclone 10 LP [10CL025](https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-10.html)
 
 **Note**: cyclone IV and cyclone 10 have same idcode. A WA is mandatory to

src/board.hpp

@@ -51,6 +51,7 @@ static std::map <std::string, target_cable_t> board_list = {
 	{"littleBee",  {"ft2232",     {}}},
 	{"spartanEdgeAccelBoard", {"",{}}},
 	{"pipistrello", {"ft2232",    {}}},
+	{"qmtechCycloneV", {"",       {}}},
 	{"tangnano",   {"ft2232",     {}}},
 	{"ulx2s",      {"ft232RL",  {FT232RL_RI, FT232RL_DSR, FT232RL_CTS, FT232RL_DCD}}},
 	{"ulx3s",      {"ft231X",   {FT232RL_DCD, FT232RL_DSR, FT232RL_RI, FT232RL_CTS}}},

src/part.hpp

@@ -23,6 +23,8 @@ static std::map <int, fpga_model> fpga_list = {
 
 	{0x020f30dd, {"altera", "cyclone 10 LP", "10CL025"}},
 
+	{0x02b150dd, {"altera", "cyclone V", "5CEA2"}},
+
 	{0x010F0043, {"lattice", "CrosslinkNX", "LIFCL-17"}},
 	{0x010F1043, {"lattice", "CrosslinkNX", "LIFCL-40-ES"}},
 	{0x110F1043, {"lattice", "CrosslinkNX", "LIFCL-40"}},