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add support for artix-7 200t and nexys video board

This commit is contained in:
Giuseppe Gebbia 2020-10-15 16:07:55 +02:00
parent 06d0e44f71
commit edad461d88
7 changed files with 19 additions and 2 deletions
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2
spiOverJtag/Makefile
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@ -1,5 +1,5 @@
VIVADO := vivado -nolog -nojournal -mode batch -source
MODELS := xc7a35 xc7a100 xc7s50
MODELS := xc7a35 xc7a100 xc7s50 xc7a200
BIT_FILES := $(addsuffix .bit,$(addprefix spiOverJtag_, $(MODELS)))
all: $(BIT_FILES)

9
spiOverJtag/constr_xc7a200.xdc Normal file
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@ -0,0 +1,9 @@
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS33} [get_ports {csn}]
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}]
set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}]
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}]
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}]

BIN
spiOverJtag/spiOverJtag_xc7a200.bit Normal file
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7
spiOverJtag/xilinx_spiOverJtag.tcl
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@ -6,7 +6,12 @@ set build_path tmp_${model}
file delete -force $build_path
# Project creation
set parts [dict create xc7a35 xc7a35ticsg324-1L xc7a100 xc7a100tfgg484-2 xc7s50 xc7s50csga324-1]
set parts [dict create \
xc7a35 xc7a35ticsg324-1L \
xc7s50 xc7s50csga324-1 \
xc7a100 xc7a100tfgg484-2 \
xc7a200 xc7a200tsbg484-1 \
]
create_project $project_name $build_path -part [dict get $parts $model]
add_files -norecurse xilinx_spiOverJtag.vhd

1
src/board.hpp
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@ -38,6 +38,7 @@ typedef struct {
static std::map <std::string, target_cable_t> board_list = {
{"arty", {"digilent", {}}},
{"nexysVideo", {"digilent_b", {}}},
{"colorlight", {"", {}}},
{"crosslinknx_evn", {"ft2232", {}}},
{"cyc1000", {"ft2232", {}}},

1
src/cable.hpp
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@ -29,6 +29,7 @@ static std::map <std::string, cable_t> cable_list = {
{"bus_blaster", {MODE_FTDI_SERIAL, {0x0403, 0x6010, INTERFACE_A, 0x08, 0x1B, 0x08, 0x0B}}},
{"bus_blaster_b",{MODE_FTDI_SERIAL, {0x0403, 0x6010, INTERFACE_B, 0x08, 0x0B, 0x08, 0x0B}}},
{"digilent", {MODE_FTDI_SERIAL, {0x0403, 0x6010, INTERFACE_A, 0xe8, 0xeb, 0x00, 0x60}}},
{"digilent_b", {MODE_FTDI_SERIAL, {0x0403, 0x6010, INTERFACE_B, 0xe8, 0xeb, 0x00, 0x60}}},
{"digilent_hs2", {MODE_FTDI_SERIAL, {0x0403, 0x6014, INTERFACE_A, 0xe8, 0xeb, 0x00, 0x60}}},
{"digilent_hs3", {MODE_FTDI_SERIAL, {0x0403, 0x6014, INTERFACE_A, 0x88, 0x8B, 0x20, 0x30}}},
{"dirtyJtag", {MODE_DIRTYJTAG, {}}},

1
src/part.hpp
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@ -15,6 +15,7 @@ static std::map <int, fpga_model> fpga_list = {
{0x0362D093, {"xilinx", "artix a7 35t", "xc7a35"}},
{0x13631093, {"xilinx", "artix a7 100t", "xc7a100"}},
{0x13636093, {"xilinx", "artix a7 200t", "xc7a200"}},
{0x44008093, {"xilinx", "spartan6", "xc6slx45"}},
{0x03620093, {"xilinx", "spartan7", "xc7s15ftgb196-1"}},