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openFPGALoader
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Add MachXO3D Development Board Support

This commit is contained in:
Francisco Ayala Le Brun 2020-10-16 08:03:45 +02:00
parent 06d0e44f71
commit fbb8c58f46
5 changed files with 10 additions and 2 deletions
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2
README.md
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@ -9,6 +9,7 @@ __Current support kits:__
* [Digilent Arty S7 xc7s50](https://reference.digilentinc.com/reference/programmable-logic/arty-s7/start) (memory and spi flash)
* [Lattice MachXO2 Breakout Board Evaluation Kit (LCMXO2-7000HE)](https://www.latticesemi.com/products/developmentboardsandkits/machxo2breakoutboard) (memory and flash)
* Lattice MachXO3LF Starter Kit LCMX03LF-6900C (memory and flash)
* [Lattice MachXO3D Development Board (LCMXO3D-9400HC)](https://www.latticesemi.com/products/developmentboardsandkits/machxo3d_development_board)
* [Lattice CrossLink-NX Evaluation Board (LIFCL-40-EVN)](https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/CrossLink-NXEvaluationBoard) (memory and spi flash)
* [Lattice ECP5 5G Evaluation Board (LFE5UM5G-85F-EVN)](https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/ECP5EvaluationBoard) (memory and spi flash)
* [Trenz Gowin LittleBee (TEC0117)](https://shop.trenz-electronic.de/en/TEC0117-01-FPGA-Module-with-GOWIN-LittleBee-and-8-MByte-internal-SDRAM)
@ -25,6 +26,7 @@ __Supported (tested) FPGA:__
* Gowin [GW1N (GW1N-1, GW1N-4, GW1NR-9)](https://www.gowinsemi.com/en/product/detail/2/) (SRAM and Flash)
* Lattice [MachXO2](https://www.latticesemi.com/en/Products/FPGAandCPLD/MachXO2) (SRAM and Flash)
* Lattice [MachXO3LF](http://www.latticesemi.com/en/Products/FPGAandCPLD/MachXO3.aspx) (SRAM and Flash)
* Lattice [MachXO3D](http://www.latticesemi.com/en/Products/FPGAandCPLD/MachXO3D.aspx) (SRAM and Flash)
* Lattice [ECP5 (25F, 5G 85F](http://www.latticesemi.com/Products/FPGAandCPLD/ECP5) (SRAM and Flash)
* Lattice [ECP5 (25F, 5G 85F, CrossLink-NX (LIFCL-40)](https://www.latticesemi.com/en/Products/FPGAandCPLD/CrossLink-NX) (SRAM and Flash)
* Xilinx Artix 7 [xc7a35ti, xc7a100t](https://www.xilinx.com/products/silicon-devices/fpga/artix-7.html) (memory (all) and spi flash (xc7a35ti)

1
src/board.hpp
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@ -45,6 +45,7 @@ static std::map <std::string, target_cable_t> board_list = {
{"ecp5_evn", {"ft2232", {}}},
{"machXO2EVN", {"ft2232", {}}},
{"machXO3SK", {"ft2232", {}}},
{"machXO3EVN", {"ft2232", {}}},
{"licheeTang", {"anlogicCable", {}}},
{"littleBee", {"ft2232", {}}},
{"spartanEdgeAccelBoard", {"",{}}},

2
src/lattice.cpp
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@ -92,6 +92,8 @@ Lattice::Lattice(Jtag *jtag, const string filename,
_fpga_family = MACHXO2_FAMILY;
else if (family == "MachXO3LF")
_fpga_family = MACHXO3_FAMILY;
else if (family == "MachXO3D")
_fpga_family = MACHXO3D_FAMILY;
else if (family == "ECP5")
_fpga_family = ECP5_FAMILY;
else if (family == "CrosslinkNX")

5
src/lattice.hpp
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@ -52,8 +52,9 @@ class Lattice: public Device, SPIInterface {
enum lattice_family_t {
MACHXO2_FAMILY = 0,
MACHXO3_FAMILY = 1,
ECP5_FAMILY = 2,
NEXUS_FAMILY = 3,
MACHXO3D_FAMILY = 2,
ECP5_FAMILY = 3,
NEXUS_FAMILY = 4,
UNKNOWN_FAMILY = 999
};

2
src/part.hpp
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@ -43,6 +43,8 @@ static std::map <int, fpga_model> fpga_list = {
{0x612BE043, {"lattice", "MachXO3LF", "LCMX03LF-9400C"}},
{0x612B6043, {"lattice", "MachXO3LF", "LCMX03LF-9400E"}},
{0x212e3043, {"lattice", "MachXO3D", "LCMX03D-9400H"}},
{0x21111043, {"lattice", "ECP5", "LFE5U-12"}},
{0x41111043, {"lattice", "ECP5", "LFE5U-25"}},
{0x41112043, {"lattice", "ECP5", "LFE5U-45"}},