0779034921
Merge pull request #233 from Icenowy/ep4ce115
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Add EP4CE115 support
2022-06-16 06:23:35 +02:00
dba873af6e
spiOverJtag: add bitstream for EP4CE115F23
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Built with Quartus Prime Lite 18.1.1.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-06-16 08:58:49 +08:00
f46498b6ae
update spiOverJtag_5ce927.rbf.gz created with Lite 20.1.1
2022-06-14 08:18:53 +02:00
d7fbdabdb8
spiOverJtag: enable init done pin for cycloneV device
2022-06-10 19:06:33 +02:00
1c7a9a7ffe
spiOverJtag: support xc7k160tffg676
2022-05-14 14:30:01 +07:00
4c0f683f9f
spiOverJtag: support xc7k420tffg901
2022-05-14 09:53:56 +07:00
dd85b5a579
spiOverJtag: xc7a100tfgg676 variant
2022-05-10 19:09:21 +02:00
eb4ac2536a
spiOverJtag: add artix fgg676 constraints file
2022-05-10 19:08:32 +02:00
3a3fe9a3cb
spiOverJtag: add cycloneV 5CEBA9F27 variant
2022-05-05 07:03:06 +02:00
a12793ed70
Added spiOverJtag for Spartan3E (xc3s500evq100)
2022-03-25 21:29:00 +01:00
2ed5eb5eec
Rename 5cefa5f23 to 5ce523, add documentation for board and fpga
2022-03-13 09:14:52 -04:00
7b36bdc893
Add qmtechCycloneV_5cefa5f23 board and spiOverJtag/spiOverJtag_5cefa5f23.rbf.gz bitstream to write flash
2022-03-12 09:25:22 -05:00
9854f4c590
spiOverJtag: compress the kintex7 bitstreams
2022-03-11 15:08:49 +10:30
03769be937
spiOverJtag: Xilinx Spartan6 LX150T
2022-03-03 15:36:11 +01:00
255d90b750
add spiOverJtag build process for Kintex7 ffg900-2 packages, amend and extend build process for ff676-1 package
2022-02-22 13:01:02 -04:00
d4e8eef676
Add board and cable defaults for genesys2
2022-02-21 08:11:57 +00:00
18a24c65ea
Add spiOverJtag support for Xilinx xc7k325tffg676 part.
2022-02-19 13:14:50 +10:30
ed4d8398ac
added spiOverJtag_xc6slx16csg324.bit.gz
2022-01-28 07:18:44 +00:00
11a85eb19d
added spi flash support for xc6slx16csg324
2022-01-27 08:19:55 +00:00
6597dcf374
spiOverJtag: add bitstream for spartan6 LX16 FTG256
2022-01-15 11:47:15 +01:00
1d94270eaf
spiOverJtag: spartan6 FTG 256 ucf
2022-01-15 11:47:15 +01:00
5760676c73
spiOverJtag_xc7s50csga324: compress
2021-12-21 18:21:16 +01:00
af72b787ec
constr_xc7a_csg324.xdc: enable compression
2021-12-21 18:20:47 +01:00
603cbc0578
spiOverJtag: fix spiOverJtag_xc7a100tcsg324 compression
2021-12-21 18:20:14 +01:00
3674406227
spiOverJtag: xc7a100tcsg324
2021-12-21 07:02:14 +01:00
a4965ddcbb
spiOverJtag: add missing spiOverJtag_xc7s25csga324.bit.gz
2021-12-20 18:11:52 +01:00
70ed45fdef
spiOverJtag: gzip xilinx bitstream
2021-12-19 17:33:39 +01:00
b5f2483852
spiOverJtag/constr_xc7s_csga324.xdc: set compress
2021-12-19 17:30:34 +01:00
ea4b8d8a6d
spiOverJtag: add xc7s25csga324
2021-12-19 17:30:06 +01:00
7ceaab0126
spiOverJtag: add bitstream for ECP4CE15F23
2021-11-28 16:51:42 +01:00
f9980a566f
spiOverJtag: add spiOverJtag_5ce423.rbf.gz
2021-11-28 10:00:37 +01:00
c6b02b4358
spiOverJtag: add 5CEBA4F23C8, fix sdc file and compress rbf file
2021-11-28 10:00:21 +01:00
6a1f67bc69
spiOverJtag: add constr_xc6s_csg324
2021-07-11 09:05:15 +02:00
0d57b58c26
spiOverJtag: use build.py for all devices, add xc6slx45
2021-07-11 08:57:46 +02:00
7d3000f88d
spiOverJtag: rewrite xilinx spiOverJtag vhd -> v
2021-07-11 08:57:00 +02:00
c90a4b7734
altera: spi flash support for cycloneV and qmtech
2021-07-10 08:20:27 +02:00
0c4aedcb23
altera: add spi flash support for de0nano (EP4CE22F17C6)
2021-07-09 07:40:55 +02:00
592cbd87b7
spiOverJtag: add real bridge (virtual jtag) for cyc1000 and build system based on edalize
2021-07-08 20:59:28 +02:00
db73fedf40
Adds wpn and hldn signals.
2021-07-04 21:35:07 -04:00
05c07df4cc
Condenses TCL script.
2021-07-04 21:34:23 -04:00
1d6505182c
Adds .gitignore for ISE build files.
2021-07-04 21:33:48 -04:00
f937cb9ab5
Adds support for the xc6slx100fgg484.
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Tested on a Pano Logic G2.
2021-07-03 05:01:56 -04:00
a4ccdae7df
add basys3 support
2021-04-20 21:28:14 +02:00
7039465353
rework xilinx fpga spiOverJtag to respect model/package
2021-04-19 21:17:08 +02:00
922d3b0b56
xilinx: add xca50t support
2020-12-08 07:32:30 +01:00
edad461d88
add support for artix-7 200t and nexys video board
2020-10-15 16:07:55 +02:00
20d72de3c4
spiOverJtag: add xc7a100 bitstream
2020-09-22 15:02:42 +02:00
ced3363ee5
Support Arty S7-50
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Added Xilinx xc7s50 device to part.hpp; added support for generating
spiOverJtag bitstream file for that device and added bitstream to repo.
Converted xdc file from DOC line endings to native line endings.
2020-08-08 11:42:38 +02:00
5acae16a82
add design and bitstream to access SPI through JTAG
2019-10-05 19:03:28 +02:00
Gwenhael Goavec-Merou
Icenowy Zheng
Simon Buhrow
Hans Baier
Stephan Ruloff
Stéphane Chevigny
Rod Whitby
unbtorsten
jonathan kimmitt
Dave Berkeley
Billy Stevens
Giuseppe Gebbia
Staf Verhaegen