Merge pull request #233 from Icenowy/ep4ce115

Add EP4CE115 support

doc/FPGAs.yml

@@ -68,7 +68,9 @@ Intel:
     Flash: OK
 
   - Description: Cyclone IV CE
-    Model: EP4CE22
+    Model:
+      - EP4CE22
+      - EP4CE115
     URL: https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iv/features.html
     Memory: OK
     Flash: OK

spiOverJtag/Makefile

@@ -10,7 +10,7 @@ XILINX_PARTS := xc3s500evq100 xc6slx16ftg256 xc6slx16csg324 xc6slx45csg324 xc6sl
 	xc7k420tffg901
 XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS)))
 
-ALTERA_PARTS := 10cl025256 ep4ce2217 ep4ce1523 5ce223 5ce423 5ce523 5ce927
+ALTERA_PARTS := 10cl025256 ep4ce2217 ep4ce1523 ep4ce11523 5ce223 5ce423 5ce523 5ce927
 ALTERA_BIT_FILES := $(addsuffix .rbf.gz, $(addprefix spiOverJtag_, $(ALTERA_PARTS)))
 
 BIT_FILES := $(ALTERA_BIT_FILES) $(XILINX_BIT_FILES)

spiOverJtag/build.py

@@ -121,6 +121,7 @@ if tool in ["ise", "vivado"]:
 else:
     full_part = {
         "10cl025256": "10CL025YU256C8G",
+        "ep4ce11523": "EP4CE115F23C7",
         "ep4ce2217" : "EP4CE22F17C6",
         "ep4ce1523" : "EP4CE15F23C8",
         "5ce223"    : "5CEFA2F23I7",

src/part.hpp

@@ -79,6 +79,7 @@ static std::map <uint32_t, fpga_model> fpga_list = {
 	{0x04730093, {"xilinx", "zynqmp",      "xczu7ev", 6}},
 
 	{0x020f20dd, {"altera", "cyclone III/IV", "EP3C16/EP4CE15", 10}},
+	{0x020f70dd, {"altera", "cyclone IV", "EP4CE115", 10}},
 
 	{0x020f30dd, {"altera", "cyclone 10 LP", "10CL025", 10}},