2093ce7520
gowin: fix gw1n external flash access
2023-12-14 11:48:14 +01:00
1dbc9e664b
gowin: programFlash/writeFlash: disable previous rewrite (fix write with tangnano4k)
2023-12-14 11:38:34 +01:00
ed547ed893
boards: adding AMD Virtex UltraScale+ FPGA VCU1525 Acceleration Development Kit
2023-12-11 12:23:37 +01:00
d8186c5e8a
gowin: GW5AST work around
2023-12-11 07:20:37 +01:00
1c7a4afd01
ftdipp_mpsse: display/typo
2023-12-11 07:18:02 +01:00
bd917d51ef
gowin: try second eraseSRAM before writeSRAM. Not always working but better...
2023-12-10 08:14:06 +01:00
163d83787a
Merge pull request #409 from dau-dev/tkp/pz1
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Add pynq-z1 board
2023-12-09 06:13:43 +01:00
b70a3991cc
Add pynq-z1 board
2023-12-08 14:51:38 -05:00
2a2435ecbe
board: Xilinx KCU105 (Kintex Ultrascale xcku040)
2023-12-08 16:00:59 +01:00
807d794703
latticeBitParser: add ECP3 VERIFY ID support (avoid to fail with bitstream)
2023-12-08 07:07:35 +01:00
fb587e73d8
gowin: Fix clk cycle after sending a command, don't read status register programSRAM sequence
2023-12-04 07:25:43 +01:00
0dcd851187
gowin: avoid multiple status register access
2023-12-04 07:05:40 +01:00
01d6244a0f
gowin: Fix status register parse for GW5AST
2023-12-04 07:01:56 +01:00
8007ffe263
xilinx: lint more happy
2023-11-25 15:14:32 +01:00
234f7f5a35
XADC and DNA for Xilinx FPGA ( #407 )
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* xilinx: add XADC and DNA args, see https://github.com/cfib/openFPGALoaderXADC/tree/XADC_3
parts: add xcku060
* doc: add xcku060
2023-11-25 08:47:24 +01:00
b119a955a6
gowin: GW5A SPI flash support
2023-11-19 13:29:15 +01:00
a5f2aa56c8
gowin: displayReadReg update. Now GW5A field are correctly displayed
2023-11-19 10:25:06 +01:00
31c89e21a3
gowin: detectFamily new function
2023-11-19 10:18:45 +01:00
1cbdee362d
jtag,main: fix warnings
2023-11-19 10:17:54 +01:00
1306c79bdc
Merge pull request #406 from markfeathers/add-user-device-list
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Add user device list for non-fpga JTAG devices
2023-11-13 07:07:16 +01:00
7059c15960
Add user device list for non-fpga JTAG devices
2023-11-10 14:00:24 -07:00
34f20ca686
Merge pull request #404 from hansfbaier/master
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Add xc7k70t and small fixes for xc7k160t
2023-11-09 06:04:46 +01:00
63c1950f2f
Add xc7k70t and small fixes for xc7k160t
2023-11-09 07:45:46 +07:00
1a86fa21ae
Merge pull request #399 from bg-gsl/fix_lattice_bscan_nexus
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Fix lattice bscan nexus in clearSRAM()
2023-11-08 12:47:34 +01:00
fa5ff873e4
lattice.cpp: restore bypass instruction in clearSRAM()
2023-11-08 09:49:14 +01:00
f71858f96a
Rewrite GOWIN algorithms
2023-10-29 08:07:48 +01:00
790d2bccab
fsParser: adding GW5A-25 IDCODE
2023-10-29 07:02:12 +01:00
59b56bcc95
all jtag cable: no more hardcoding tdi bit with writeTMS
2023-10-29 06:41:39 +01:00
43ae0d8fdd
ftdiJtagMPSSE,jtagInterface: {set|get}{Read|Write}Edge signature
2023-10-29 06:12:09 +01:00
b54205fc15
Merge pull request #401 from inkdot7/ax7101
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ALINX AX7101 board.
2023-10-28 18:14:39 +02:00
46ce2e61a7
ALINX AX7101 board.
2023-10-28 17:22:42 +02:00
d58a1c3fc7
lattice: correct mask for sram erase for NEXUS_FAMILY, as it is 0x00
2023-10-26 11:30:24 +02:00
917e42127b
lattice: fix bscan register initialization inside clearSRAM()
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For NEXUS family fpgas, the Bscan register is 362 bits long
or 45.25 bytes => 46 bytes.
This error was already correct when programming the sram.
clearSRAM() is instead used when programming the spi flash memory.
2023-10-25 17:43:49 +02:00
ba6dd3c82e
Merge pull request #397 from inkdot7/ax7102
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ALINX AX7102 board.
2023-10-25 10:52:38 +02:00
a87d689d83
ALINX AX7102 board.
2023-10-24 14:03:18 +02:00
fd8497026a
ftdiJtagMPSSE,jtag,jtagInterface: allows to force read/write edge configuration (useful to mimic SPI through JTAG)
2023-10-24 07:26:19 +02:00
b76a67963e
board: SiPEED tang Mega 138K
2023-10-24 06:11:53 +02:00
9a2fe6e157
board: SiPEED tang Primer 25K
2023-10-24 06:07:42 +02:00
4a3db2b519
doc: adding FT4232HP cable/interface.
2023-10-23 07:16:19 +02:00
988bedefb6
lattice: fix typo / warning
2023-10-23 07:12:45 +02:00
fc35045c95
Merge pull request #395 from bg-gsl/add_ft4232hp
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Add ft4232hp, gr740-mini, mappings of spi flash for Lattice boards, small fixes for Lattice programming procedure
2023-10-23 07:08:09 +02:00
590611a8d5
lattice: fix the warning "left shift count >= width of type" shown in win32/64 builds
2023-10-20 08:44:20 +02:00
bab386911a
spi flash: add mapping for Micron MT25/N25Q128_1_8V (Lattice Certus Versa and CertusPro eval boards) and distinguish between N25Q128 1.8V and 3V memories
2023-10-20 07:57:56 +02:00
940da5fb2b
spi flash: add mapping for Macronix MX25L51245G (CertusPro Versa board and gr740-mini)
2023-10-20 07:55:53 +02:00
5f6074a7fc
lattice: fix bscan width and other minor things for NEXUS family
2023-10-20 07:55:53 +02:00
dce0c050a7
board: add gr740-mini
2023-10-20 07:55:53 +02:00
2754e99215
cable: add FTDI FT4232HP mapping
2023-10-20 07:55:53 +02:00
0bbf817c92
part: fix typo
2023-10-19 17:46:50 +02:00
32ef0bd29c
Adding xcku115 to parts list ( #394 )
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* Adding xcku115 to parts list
* Adding xcku115 to list of supported FPGAs
---------
Co-authored-by: Stephen Goadhouse <stephen.david.goadhouse@cern.ch>
2023-10-19 17:45:42 +02:00
f964c3364f
doc/FPGAs,boards: adding certus boards/parts entries
2023-10-13 17:12:13 +02:00
Gwenhael Goavec-Merou
Tim Paine
bma
Mark Featherston
Hans Baier
Giovanni Bruni
Alexey Starikovskiy
Haakan T Johansson
sgoadhouse