Merge pull request #395 from bg-gsl/add_ft4232hp
Add ft4232hp, gr740-mini, mappings of spi flash for Lattice boards, small fixes for Lattice programming procedure
This commit is contained in:
Gwenhael Goavec-Merou
GitHub
commit
fc35045c95
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@ -324,6 +324,13 @@
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Flash: OK
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Constraints: Fomu-PVT
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- ID: gr740-mini
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Description: GR740-MINI
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URL: https://gaisler.com/index.php/products/boards/gr740-mini
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FPGA: CertusPro-NX LFCPNX-100
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Memory: OK
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Flash: NA
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- ID: honeycomb
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Description: honeycomb
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URL: https://github.com/Disasm/honeycomb-pcb
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@ -155,6 +155,7 @@ static std::map <std::string, target_board_t> board_list = {
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SPI_BOARD("gatemate_evb_spi", "colognechip", "gatemate_evb_spi",
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DBUS4, DBUS5, CBUS0, DBUS3, DBUS0, DBUS1, DBUS2, 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("genesys2", "xc7k325tffg900", "digilent_b", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("gr740-mini", "", "ft4232hp_b", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("hseda-xc6slx16", "xc6slx16ftg256", "", 0, 0, CABLE_DEFAULT),
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/* most ice40 boards uses the same pinout */
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SPI_BOARD("ice40_generic", "lattice", "ft2232",
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@ -108,6 +108,8 @@ static std::map <std::string, cable_t> cable_list = {
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{"ft232", FTDI_SER(0x0403, 0x6014, FTDI_INTF_A, 0x08, 0x0B, 0x08, 0x0B)},
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{"ft232RL", FTDI_BB( 0x0403, 0x6001, FTDI_INTF_A, 0x08, 0x0B, 0x08, 0x0B)},
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{"ft4232", FTDI_SER(0x0403, 0x6011, FTDI_INTF_A, 0x08, 0x0B, 0x08, 0x0B)},
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{"ft4232hp", FTDI_SER(0x0403, 0x6043, FTDI_INTF_A, 0x08, 0x0B, 0x00, 0x00)},
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{"ft4232hp_b", FTDI_SER(0x0403, 0x6043, FTDI_INTF_B, 0x08, 0x0B, 0x00, 0x00)},
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{"ecpix5-debug", FTDI_SER(0x0403, 0x6010, FTDI_INTF_A, 0xF8, 0xFB, 0xFF, 0xFF)},
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{"jlink", CABLE_DEF(MODE_JLINK, 0x1366, 0x0105 )},
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{"jlink_base", CABLE_DEF(MODE_JLINK, 0x1366, 0x0101 )},
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@ -103,7 +103,7 @@ using namespace std;
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# define REG_STATUS_AUTH_DONE (1 << 18) /* Authentication done */
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# define REG_STATUS_PRI_BOOT_FAIL (1 << 21) /* Primary boot failure (1= Fail) even though secondary boot successful */
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# define REG_STATUS_CNF_CHK_MASK (0x0f << 23) /* Configuration Status Check */
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#define REG_STATUS_PRV_CNF_CHK_MASK (0x0fUL << 33) /* NEXUS_FAMILY: Configuration Status Check of previous bitstrem */
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#define REG_STATUS_PRV_CNF_CHK_MASK (UINT64_C(0x0f) << 34) /* NEXUS_FAMILY: Configuration Status Check of previous bitstrem */
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# define REG_STATUS_MACHXO3D_CNF_CHK_MASK (0x0f << 22) /* Configuration Status Check */
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# define REG_STATUS_EXEC_ERR (1 << 26) /*** NOT specified for MachXO3D ***/
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# define REG_STATUS_DEV_VERIFIED (1 << 27) /* I=0 Device verified correct, I=1 Device failed to verify */
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@ -301,11 +301,20 @@ bool Lattice::program_mem()
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displayReadReg(readStatusReg());
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}
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/* The command code 0x1C is not listed in the manual? */
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/* preload 0x1C */
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uint8_t tx_buf[26];
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memset(tx_buf, 0xff, 26);
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wr_rd(0x1C, tx_buf, 26, NULL, 0);
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/* The command code 0x1C is not listed in the manual?
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* PRELOAD/SAMPLE 0x1C
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* For NEXUS family fpgas, the Bscan register is 362 bits long or
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* 45.25 bytes => 46 bytes
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*/
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uint8_t tx_buf[46];
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memset(tx_buf, 0xff, 46);
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int tx_len;
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if(_fpga_family == NEXUS_FAMILY){
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tx_len = 46;
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} else {
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tx_len = 26;
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}
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wr_rd(0x1C, tx_buf, tx_len, NULL, 0);
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/* LSC_REFRESH 0x79 -- "Equivalent to toggle PROGRAMN pin"
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* We REFRESH only if the fpga is in a status of error due to
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@ -375,9 +384,15 @@ bool Lattice::program_mem()
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printSuccess("DONE");
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}
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/* ISC ERASE */
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/* ISC ERASE
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* For Nexus family (from svf file): 1 byte to tx 0x00
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*/
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printInfo("SRAM erase: ", false);
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if (flashErase(FLASH_ERASE_SRAM) == false) {
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uint32_t mask_erase[1] = {FLASH_ERASE_SRAM};
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if (_fpga_family == NEXUS_FAMILY){
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mask_erase[0] = 0x00;
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}
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if (flashErase(mask_erase[0]) == false) {
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printError("FAIL");
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displayReadReg(readStatusReg());
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return false;
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@ -74,6 +74,8 @@ bool libusb_ll::scan()
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snprintf(probe_type, 256, "ft232H");
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else if (desc.idProduct == 0x6015)
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snprintf(probe_type, 256, "ft231X");
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else if (desc.idProduct == 0x6043)
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snprintf(probe_type, 256, "FT4232HP");
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else
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snprintf(probe_type, 256, "unknown FTDI");
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found = true;
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@ -139,9 +139,26 @@ static std::map <uint32_t, flash_t> flash_list = {
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.bp_len = 4,
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.bp_offset = {(1 << 2), (1 << 3), (1 << 4), (1 << 6)}}
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},
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{0x0020ba18, {
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{0x0020bb18, {
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/* https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_128mb_1_8v_65nm.pdf */
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/* MT25QU128ABA has the same JEDEC-standard signature: https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qlhs_u_128_aba_0.pdf */
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/* Differences: https://media-www.micron.com/-/media/client/global/documents/products/technical-note/nor-flash/tn2501_migrating_n25q_to_mt25ql.pdf */
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.manufacturer = "micron",
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.model = "N25Q128",
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.model = "MT25/N25Q128_1_8V",
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.nr_sector = 256,
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.sector_erase = true,
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.subsector_erase = true,
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.has_extended = true,
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.tb_otp = false,
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.tb_offset = (1 << 5),
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.tb_register = STATR,
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.bp_len = 4,
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.bp_offset = {(1 << 2), (1 << 3), (1 << 4), (1 << 6)}}
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},
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{0x0020ba18, {
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/* https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_128mb_3v_65nm.pdf */
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.manufacturer = "micron",
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.model = "N25Q128_3V",
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.nr_sector = 256,
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.sector_erase = true,
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.subsector_erase = true,
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@ -283,6 +300,20 @@ static std::map <uint32_t, flash_t> flash_list = {
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.bp_len = 5,
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.bp_offset = {(1 << 2), (1 << 3), (1 << 4), (1 << 5)}}
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},
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{0xc2201a, {
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/* https://www.macronix.com/Lists/Datasheet/Attachments/8745/MX25L51245G,%203V,%20512Mb,%20v1.7.pdf */
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.manufacturer = "Macronix",
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.model = "MX25L51245G",
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.nr_sector = 1024,
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.sector_erase = true,
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.subsector_erase = true,
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.has_extended = false,
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.tb_otp = true,
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.tb_offset = (1 << 3),
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.tb_register = CONFR,
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.bp_len = 5,
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.bp_offset = {(1 << 2), (1 << 3), (1 << 4), (1 << 5)}}
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},
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{0xef4014, {
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/* https://cdn-shop.adafruit.com/datasheets/W25Q80BV.pdf */
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.manufacturer = "Winbond",
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