ad5ada90db
board: trion_t20_bga256_jtag support
2023-10-03 06:51:38 +02:00
e9b31425d6
cable: efinix jtag ft2232 variant
2023-10-03 06:48:47 +02:00
48caa612a3
Merge pull request #381 from openhardwarefan/xczu17eg_support
...
Add support for Xilinx xczu17eg. It's tested on xczu17eg board with Digilent HS3 at 30Mbps.
2023-09-23 06:42:00 +02:00
c0ad3225cc
Add support for Xilinx xczu17eg. It's tested on xczu17eg board with Digilent HS3 at 30Mbps.
2023-09-22 19:33:01 -07:00
c82a8e6207
Make CH347 driver faster
...
Speed up toggleClk
Defer write-only USB transactions to better utilize bus
2023-09-22 07:08:48 +02:00
67159e8297
Move JTAG chain bit init to device_select()
2023-09-22 07:05:20 +02:00
4c39abf51c
Add missing pieces to JTAG
2023-09-22 07:01:48 +02:00
85f9791600
drop div_by_5 to allow 2.5MHz clock
2023-09-22 06:55:21 +02:00
01ac90a172
[xilinx] add jtag->flush before sleep
2023-09-21 07:38:25 +02:00
b10be9ae8a
properly fill dummy arrays
2023-09-21 07:36:41 +02:00
d3410e0e30
Update JTAG chain detect
2023-09-21 07:33:54 +02:00
fc6f3fb8e1
doc/data: adding an (unused for now) SPIFlash entry
2023-09-21 07:03:41 +02:00
5bbc02f56b
doc/boards: fix wrong constraints link
2023-09-21 07:03:07 +02:00
afbf0c4ff8
board: adding @lambdaconcept ecpix5_r03 (ft4232)
2023-09-21 06:24:30 +02:00
6c16417ee9
Merge UPDATE_DR and UPDATE_IR handling in JTAG state machines
2023-09-20 07:59:34 +02:00
6a0de15bff
Parse LoadingRate field
2023-09-20 07:58:06 +02:00
0c89ac9a44
Add GD32VF103 to misc devices
2023-09-20 07:48:21 +02:00
94b62460c5
jtag: shiftDR: (fix daisy chain) when more than one FPGA, a sequence of '0' before and/or after must be sent instead of '1' ( fix #189 and #133
2023-09-17 08:59:26 +02:00
9810735e32
jtag: rework detectChain: try unmasked idcode first
2023-09-14 21:53:27 +02:00
57fc9bcb6f
part: machXO3: re-add partially revision
2023-09-14 21:52:53 +02:00
2c23e8a3b6
Merge pull request #376 from rarengifoArthrex/master
...
pass along reset parameters to provide control to the caller
2023-09-11 06:14:08 +02:00
5e9cc7c440
pass along reset paramaters to provide control to the caller
...
Upsteam-Status: Submitted [https://github.com/traucucayre/openFPGALoader ]
- Submitted to upstream, waiting approval
2023-09-10 20:46:08 -07:00
c417ce6746
lattice: spi_put: avoid loop when tx == NULL
2023-09-06 15:50:28 +02:00
61b59ce827
jtag: fix state machine (issue introduce by commit 9e91c3)
2023-09-06 15:47:32 +02:00
8989ac9768
Merge pull request #372 from aystarik/fixes
...
Fixes
2023-09-02 07:18:44 +02:00
9e91c31e31
Fixes for PVS errors
2023-09-01 22:30:24 +03:00
fbb8341323
Merge pull request #370 from aystarik/master
...
Generic refactoring of the code
2023-08-31 09:46:44 +02:00
0f3afbcaea
Make IDCODE unsigned
2023-08-29 20:01:21 +03:00
8976404b78
Use JTAG state
2023-08-29 20:00:28 +03:00
1908ccd83b
make output buffer const
2023-08-29 19:51:41 +03:00
d5c72dcc58
doc/FPGAs: adding Gowin GW5A serie
2023-08-12 07:41:18 +02:00
e634b479b0
Merge pull request #364 from Icenowy/gw5ast-138k
...
Add GW5AST-138 support
2023-08-12 07:33:53 +02:00
0de2ea6b39
gowin: add preliminary support for GW5AST-138
...
Arora V series is a new series of Gowin FPGA, in which the flashing
process has changed.
Add preliminary support by adding FS file line count and deal with the
SRAM writing process. Flash writing is not yet done.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2023-08-12 12:36:06 +08:00
6a4e107e42
part: add known ID codes for GW5 series
...
Codes are from Gowin UG704.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2023-08-09 22:11:41 +08:00
11141d7876
doc/boards: adding Avnet Mini-ITX Base Kit
2023-08-08 06:52:59 +02:00
666d9bb456
Merge pull request #362 from shareefj/feature/avnet_mini_itx
...
part/board: adding Avnet Mini-ITX
2023-08-08 06:48:41 +02:00
9d22d62a54
part/board: adding Avnet Mini-ITX
...
Adding the Avnet Mini-ITX dev board that uses the XC7Z100 Zynq-7000
device.
2023-08-07 17:06:02 +01:00
e3c8d6be1d
board: added QMTECH cyclone10 LP starter kit (10CL016YU484C8G)
2023-08-05 11:49:53 +02:00
5ac611c124
spiOverJtag: intel/altera cyclone10 LP 10CL016YU484C8G
2023-08-05 11:48:06 +02:00
7424ea2af9
part: update altera/intel idcode (same idcode for III/IV/10 LP)
2023-08-05 06:47:51 +02:00
fab58d7357
Merge pull request #360 from enjoy-digital/id_codes_cleanup_and_xcku3p_addition
...
ID-Codes cleanup and add XCKU3P ID-Code.
2023-08-04 05:01:31 +02:00
baff0cad1e
src/part: Fix Xilinx XC2 ident.
2023-08-03 16:12:51 +02:00
502f38fb00
src/part.hpp: Add Kintex Ultrascale+ KU3P ID-Code.
2023-08-03 16:07:55 +02:00
4042646434
src/part.hpp: Add separator for each vendor.
2023-08-03 16:07:43 +02:00
c3e0707f6b
src/part.hpp: Reorder families (older first, smaller first) and minor alignment cleanups.
2023-08-03 16:07:33 +02:00
a1dea79230
src/part.hpp: Add separator for each chip family.
2023-08-03 16:07:24 +02:00
4c5f6f361b
svf_jtag: fix -Wmismatched-new-delete delete -> delete[]
2023-08-03 07:53:59 +02:00
6ef87c5466
ftdipp_mpsse: fix format-zero-length snprintf -> memset
2023-08-03 07:43:56 +02:00
0e1e07262c
ftdispi: add missing status_pin
2023-08-03 07:42:06 +02:00
baa9ab86a5
prepare release v0.11.0
2023-08-02 11:21:35 +02:00
Gwenhael Goavec-Merou
Zhongyi Chen
Alexey Starikovskiy
Rodrigo Rengifo
Icenowy Zheng
Shareef Jalloq
Florent Kermarrec