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Merge pull request #362 from shareefj/feature/avnet_mini_itx

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part/board: adding Avnet Mini-ITX
This commit is contained in:
Gwenhael Goavec-Merou
2023-08-08 06:48:41 +02:00
committed by GitHub
parent e3c8d6be1d 9d22d62a54
commit 666d9bb456
2 changed files with 3 additions and 1 deletions
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src/board.hpp
+2 -1
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@@ -222,7 +222,8 @@ static std::map <std::string, target_board_t> board_list = {
JTAG_BOARD("kcu116", "xcku5p-ffvb676", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("zedboard", "xc7z020clg484", "digilent_hs2", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("zybo_z7_10", "xc7z010clg400", "digilent", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("zybo_z7_20", "xc7z020clg400", "digilent", 0, 0, CABLE_DEFAULT)
JTAG_BOARD("zybo_z7_20", "xc7z020clg400", "digilent", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("mini_itx", "xc7z100ffg900", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT)
};
#endif
src/part.hpp
+1
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@@ -82,6 +82,7 @@ static std::map <uint32_t, fpga_model> fpga_list = {
{0x03722093, {"xilinx", "zynq", "xc7z010", 6}},
{0x03727093, {"xilinx", "zynq", "xc7z020", 6}},
{0x23731093, {"xilinx", "zynq", "xc7z045", 6}},
{0x03736093, {"xilinx", "zynq", "xc7z100", 6}},
/* Xilinx Ultrascale / Kintex */
{0x13822093, {"xilinx", "kintexus", "xcku040", 6}},