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486 Commits

Author SHA1 Message Date
Holger Vogt 1ad6253eb4 tiny update 2026-02-14 12:32:50 +01:00
Holger Vogt dc7d61591a Single NMOS degradation 2026-02-13 17:03:21 +01:00
Holger Vogt 2b21666a4d Code model: 
Put the monitored degradation data onto the heap and into the hash table.
prepare_degsim():
Re-read the netlist, remove the monitors, get the device instance name.
Retrieve the degradation data from the result hash table.
 2026-02-09 17:01:19 +01:00
Holger Vogt 44fd33ea7d Add a command 'degsim' to reset the circuit, remove the monitors, 
and add the degradation model to each degraded device.
Use function preparedegsim() to add the model with parameters from
degdatahash.
 2026-02-08 15:47:04 +01:00
Holger Vogt 8755dd4493 Add non-nqs PSP model 2026-02-08 13:53:27 +01:00
Holger Vogt d832290b8c artificially set A_d_idsat from 0 to 0.001 2026-02-08 13:53:26 +01:00
Holger Vogt f6fd763c8c example netlist: 3 inverters in series 2026-02-08 13:53:26 +01:00
Holger Vogt a20da11d4c New title 2026-02-08 13:53:26 +01:00
Holger Vogt 3a24708350 simple netlist example with agemodel data. 2026-02-08 13:53:24 +01:00
Holger Vogt ab03cc94c0 Using mtimeavg 2026-02-03 14:23:41 +01:00
Holger Vogt 86ca3948eb Better graphics 2026-02-03 14:23:07 +01:00
Holger Vogt 4fd68ba901 enable simulation with 'option newtrunc' 2026-02-03 14:22:12 +01:00
dwarning d3b0dc1b31 Adapt VDMOS Vth temperature coefficient to usual notation with - for nch and + for pch. 2026-02-03 14:21:50 +01:00
Holger Vogt 343319a1ed F5 example removed, obsolete or needs to be improved. 2026-02-03 14:21:38 +01:00
Holger Vogt c12ad7ba27 Update the reference to the manual 2026-02-03 14:20:19 +01:00
Holger Vogt f6fc256569 Measure transient analysis time. 2026-02-03 14:19:06 +01:00
Holger Vogt ac9ac548d6 Update test description 2026-02-03 14:16:23 +01:00
Holger Vogt 59a64f57d6 Update: add frequency measurement and temperature dependency. 2026-02-03 14:14:18 +01:00
Holger Vogt 65fc0ad8a6 Add analog code model astate. 
It reports the previous state (delayed by 1 to 3 time steps)
of the input node. Single or differential voltage or current.
 2026-02-03 13:57:57 +01:00
Brian Taylor 7af862af3d Enable CIDER with KLU for DC, OP, and TRAN analyses. Small signal AC analysis is not yet supported for CIDER complex valued device KLU matrices. The examples/cider testcases produce printed simulation result values which have slight differences between Sparse and KLU. Differences are probably expected and in a few cases are ~1-2%, sometimes a little more. This should be good enough for most CIDER analyses. Francesco did a good piece of work. Runtimes are significantly shorter with KLU. 2026-02-03 13:55:12 +01:00
Brian Taylor 0e50efc1fa Add missing value in the last line. 
FIXME: we need to check the input for having adequate columns
 2025-08-28 12:14:50 +02:00
Holger Vogt 481e3e567b Update to filesource 
Move tprev out of the loop to enable storing the previous time value.
Add some general warning message that an error might have occurred during
reading the time or data values from the data input file.
Allow empty lines in the data input file.
Guard early data values (TIME < time offset) against false reading.
Add some simple examples.
 2025-08-11 18:45:21 +02:00
Brian Taylor cc101495a5 Fix the xspice transmission_line examples. 
Also, cherry pick:
commit 87d09def9c (origin/bt_dev)
Author: Brian Taylor <lbwnet@comcast.net>
Date:   Sun May 18 14:01:47 2025 -0700

    Fix memory leak in xspice oneshot.
 2025-07-29 10:57:55 +02:00
Vadim Kuznetsov 70ee0f8ef5 Add examples 2025-07-29 10:54:37 +02:00
Holger Vogt d2ded9fa2c Tiny modifications of SEE examples 2025-07-29 10:47:32 +02:00
Holger Vogt 3fb1ea1c39 Unix line endings 
rusage added
 2025-07-29 10:46:39 +02:00
Holger Vogt 9d7db2166a New example for seegen: CMOS comparator 2025-07-29 10:46:18 +02:00
Holger Vogt 07f8c3558b Add a monitoring output the the seegen instance 2025-07-29 10:45:30 +02:00
Holger Vogt b628032d7d Add a generator for SEE (single event effects) pulses as a code model. 
To be used like
aseegen1 NULL [%id(xcell.n1 m1) %id(xcell.n2 m2) %id(xcell.n1 m1) %id(xcell.n2 m2)] seemod1
.model seemod1 seegen (tdelay = 11n tperiod=25n tfall='tfall' trise='trise' let='let' cdepth='d')
see README.SEEgenerator for details
 2025-07-29 10:39:58 +02:00
Holger Vogt f73873c495 Enable expressions in a meas statement within a .control section, like 
meas tran yeval2 FIND v(2) WHEN v(1)= 0.9*v(2)
 2025-07-29 10:37:59 +02:00
Giles Atkinson bba4046d55 Re-make pll-xspice.cir as a wrapper around shared-pll-xspice.cir, 
behaviour as before.  Add similar pll-digital-iplot.cir as a
demonstration of iplot with analogue and digital nodes.
 2025-05-24 11:28:42 +02:00
Giles Atkinson 592b99d0ef Rename pll-xspice.cir to shared-pll-xspice.cir to prepare for split. 2025-05-24 11:28:34 +02:00
Giles Atkinson a649514e87 Add an extended shared library test program with additional 
local commands to exercise the API.
 2025-05-24 11:28:07 +02:00
Holger Vogt 2862d243d7 Add two simple Skywater PDK examples, inverter and ISCAS85 C7552 2025-05-24 11:13:43 +02:00
Giles Atkinson c7c85ecadc Add co-simulation with VHDL, using the GHDL compiler and d_cosim. 2025-05-24 11:05:33 +02:00
Brian Taylor 4149edd146 Fix circuits so that gtkwave tests run on MacOS. Add encoder/decoder example. 2025-05-24 11:04:13 +02:00
Brian Taylor 00ad25fbc9 Fix d_process named pipes example. Use the correct gtkwave command for MacOS. 
The following is also required:
commit 527b8378e8
Author: Brian Taylor <lbwnet@comcast.net>
Date:   Wed Apr 10 13:24:48 2024 -0700

    Fix circuits so that gtkwave tests run on MacOS. Add encoder/decoder example.
 2025-05-24 11:03:52 +02:00
Giles Atkinson fd3827af40 Fix ordering of parameter definition and use. 
Icarus Verilog no longer accepts use-before-definition.
Also slightly expand the README for Icarus Verilog examples.
 2025-05-24 11:00:18 +02:00
Holger Vogt edecf91437 options are not required 2025-05-24 10:58:45 +02:00
dwarning cef9d5b11c iscas_stdcell.lib need geometry parameters, but is not used anyway, so commented out 2024-12-15 10:25:07 +01:00
Holger Vogt fdbb62844c Example for sending a text string over the subcircuit boundary. 2024-12-06 22:48:31 +01:00
Holger Vogt c79b3501ef Add note on compatibility mode psa 2024-12-06 22:41:31 +01:00
Giles Atkinson cf812da363 Try to clarify the mechanism of parameter substitution and add 
an example of substituting an XSPICE vector parameter.
 2024-11-02 22:41:59 +01:00
Holger Vogt d425d38c44 Old deprecated ADMS examples removed. 2024-11-02 22:38:17 +01:00
Giles Atkinson 35968d1da6 Add additional examples of Verilog co-simulation and share the Verilog 
source and large parts of the example circuits between Verilator and
Icarus Verilog.  Verilog source file adc.v has improved style:
all assignments in the always block are now non-blocking.
 2024-11-02 22:30:32 +01:00
Holger Vogt cab4f8d3d6 File encoding is now UTF-8 
change to letter µ
 2024-11-02 22:22:22 +01:00
dwarning 2c7f1e471b vbic: rm obsolete regression test 2024-05-01 10:34:01 +02:00
Holger Vogt bfb7798f97 measure example with expression evaluation 2024-03-29 17:12:40 +01:00
Holger Vogt 03a1010a65 Repeat loop requires plain number, transformed vector, or transformed variable 2024-03-19 17:05:10 +01:00
Holger Vogt 92b3a901c7 The values used in the foreach loop my be given by a vector 
(in addition to plain numbers or a list variable).
 2024-03-19 16:41:27 +01:00