tiny update
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@ -1,6 +1,6 @@
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test of integrated degradation monitor
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*Inverter sequence
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* NMOS transistor with const drain voltage
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.lib "$PDK_ROOT/$PDK/libs.tech/ngspice/models/cornerMOSlv.lib" mos_tt
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@ -9,7 +9,7 @@ test of integrated degradation monitor
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* the voltage sources:
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Vdd vdd gnd DC 1.8
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Vss vss 0 0
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V1 in gnd pulse(0 1.8 0p 100p 100p 0.5n 2n)
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V1 in gnd dc 0 pulse(0 1.8 0p 100p 100p 0.5n 2n)
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xm02 vdd in vss vss sg13_lv_nmos l=0.15u w=0.495u as=0.131175p ad=0.131175p ps=1.52u pd=1.52u
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*adegmon1 %v([z a vss vss]) mon degmon1
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