Fix ordering of parameter definition and use.

Icarus Verilog no longer accepts use-before-definition.
Also slightly expand the README for Icarus Verilog examples.

examples/xspice/icarus_verilog/README.txt

@@ -5,6 +5,10 @@ so that its simulation engine is available as a dynamic library.
 The Verilog source code and included parts of the circuit definitions
 can be found in the adjacent "verilator" directory.
 
+The circuits and steps below are intended to be used from the directory
+containing this file, certainly ouput files from iverilog should be in
+the current directory when simulating.
+
 The example circuits are:
 
 555.cir: The probably familiar NE555 oscillator provides a minimal example

examples/xspice/verilator/adc.v

@@ -3,12 +3,12 @@
 `timescale 100ns/100ns
 
 module adc(Clk, Comp, Start, Sample, Done, Result);
+   parameter		     Bits=6;
+
    input wire                Clk, Comp, Start;
    output reg		     Sample, Done;
    output reg [Bits - 1 : 0] Result;
 
-   parameter		     Bits=6;
-
    reg [Bits - 1 : 0]	     SR;
    reg			     Running;