Since ctx->getArchArgs() no longer returns architecture-specific
arguments, we read the args field directly.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gatemate: Use GATEMATE_DIE attribute to select placement die
* add DIE parameter in CCF
* add penalty delay when crossing between dies
* Add predictDelay
* Use QtPropertyBrowser for Qt5/6
* Fix cmake for python-console for consistency
* Make GUI compile for both Qt5 and Qt6
* Fix crash on init with Wayland on Qt6
* Cleanup
* disable deprecation warnings for now
* Relaxed cmake check for initial Qt6 test
In the GW5A series, the primitive SemiDual Port BSRAM cannot function
when the width of any of the ports is 32/36 bits - it is necessary to
divide one block into two identical ones, each of which will be
responsible for 16 bits.
Here, we perform such a division and, in addition, ensure that the new
cells resulting from the division undergo the same packing procedure as
the original ones.
Naturally, with some reservations (the AUX attribute is responsible for
this) - in the case of SP, when service elements are added, it makes
sense to do this immediately for 32-bit SP and only then divide.
Also, SDPs are currently being corrected for cases where both ports are
‘problematic’, but it may happen that one port is 32 and the other is,
say, 1/2/4/8/16. This has been left for the future.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
If the chipdb is not found, the Setup() call throws, but GTest still calls
TearDown, which then stumbles over the uninitialized pointer.
This makes the tests fail without valgrind errors or segfaults at least.
In the new series of chips, the SemiDual Port primitive has one RESET
pin instead of two in previous versions - RESETA and RESETB.
Physically, the two pins are still there and both must be connected,
with RESETA being constant.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Over time, it became clear that the special status of corner tiles is
handled in other parts of the toolchain, and in the GW5A chip series, it
began to interfere—in this series, IO can be located in the corners.
So we move the only function (creating VCC and GND) to the extra
function itself, and at the same time create a mechanism for explicitly
specifying the location of these sources in Apicula when necessary.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Check SER_CLK more
* Use connectPorts
* move rewire code
* Move data structures
* move placement decision for later
* cleanups
* find working layout
* clangformat
* Inverted input on ODDR
* Fix some tests
* Copy clocks for multi die
* cleanup
* reporting
* bugfix
* handle PLL special inputs
* Fix user globals
* Proper DDR per bank and cleanup
* Add extra data for die regions and create them
* Better forced_die implementation
* Copy region to newly generated cells, and update when constrained
* Update PLL error messages
* Add TODO comment
* convert nodes to pips
* add plane info for node pips
* a few multiplier router fixes
* do not need node delay
* add pip delays
* cleanup
* tried fixing clock router
* add PLL delays
* fix clock routing
* Do not use actual pip delay, determine best by number of passed pips
* optimize
* proper parameter check
* more multiplier fixes
* another mult fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* log number of clock net users
* Revert "Do not use actual pip delay, determine best by number of passed pips"
This reverts commit c66e422dd0.
We want to guarantee minimum clock skew, so we need pip delay.
* route clocks from source to sink
* add time spent to route_clock
* weakly-bind non-global clocks
* clangformat
* remove dead code
* Require version 1.8
* change to assert
* add revisits in clock router
---------
Co-authored-by: Lofty <dan.ravensloft@gmail.com>
The GW5A series is interesting—in this particular primitive, the inputs
have been renamed from CLKx to CLKINx. Everything else remains the same,
including functionality.
As an output, we will store in the chip database which prefix the DCS
inputs have.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
PLLA-type PLLs are implemented, which are used in GW5A-25A chips.
These are six powerful PLLs, each of which can generate seven
independent frequencies.
Since these devices have an unusual configuration—their fuse bits are
located outside the main grid and therefore their Bels do not have
specific “correct” coordinates—the extra bel functions mechanism is used
to describe them. But all the complexity falls on the apicula part.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
By replacing the operation of adding the input to itself with a
specially formed LUT, we free up two PIPs.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Add bridge support
* Use bridge only if CPE is unused
* do not use CPE_MULT for MUX routing
* Fixed and documented
* delay for CPE_BRIDGE
* Convert bridge pips into bels
Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
* recursively reassign bridges
* reconnect cell ports to new nets
* handle inversion bits
* sort data in output for easier compare
* one to be removed after testing
* debug message
* Remove need for notifyPipChange
* use same logic for detecting bridge pips
* make sure that the pip used is the one assigned
* one wire may feed multiple ports
* remove #if
* clean up wire binding
* add debugging
* fix
* clangformat
* put back to error
* use tile instead of getting name out of bel/pip
* bump chipdb
* adressing review comments
* Addressed last one
---------
Co-authored-by: Lofty <dan.ravensloft@gmail.com>
Very rarely (about once a year), the dedicated clock router would
malfunction, issuing an incorrect route.
The reason turned out to be the so-called gate wires to the global clock
wire system from the logic. Among the PIPs for which these wires are
sinks, there are PIPs where the sources are also clock wires.
This leads to the possibility of feeding the clock signal back into the
gate and again into the global clock MUX.
If handled carelessly, this can lead to a complete loop.
But the loop option itself is particularly useful in the case of DCS
(dynamic clock selection) - the fact is that because these primitives
have four clock inputs and each of them could theoretically address all
56 clock sources, but in practice there are not enough wires and the DCS
inputs cannot serve as sinks for all clock sources.
The simplest solution (and the one that currently works) is to use the
gate to re-enter the clock system, but this time changing the clock
source.
This commit explicitly marks wires as gates and removes the possibility
of looping (however unlikely it may be) where a loop is not needed.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
A programmable on-chip crystal oscillator has been implemented for the
GW5A series.
A critical innovation in this series was the change in the nature of the
OSC output pin—it now belongs to the clock wires, and therefore the
routes must be made with a special global router, as there is no
possibility of using routing through general-purpose PIPs.
At the same time, we are transferring the outputs of all previous
generations of OSC to potential clock wires. At the moment, this will
not affect the way they are routed - they will still end up as segments
as before, but in the future we may optimize the mechanism.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Optimize ALU wiring
Interestingly, although VCC and GND sources are present in each cell,
they cannot be connected directly to all LUT inputs. Instead, additional
PIPs are used.
A very simple ALU optimization: once we detect that one of the inputs is
a constant, we modify the main LUT that describes the ALU function so
that this primitive input is ignored, and then disconnect it from the
network, freeing up the PIP.
For example (unrealistic, since a real ALU LUT has a larger size and
service bits in the middle, etc.), the addition function of A and B when
A = 1 is converted from the general case (A isn't a constant and B isn't a
constant) to a special case:
0110 -> 0011
The renaming of ALU ports for ADD and SUB modes has also been
removed—this has already been done in the chip database as a fixed
change to the ALU LUT.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Fix the style.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Miodrag Milanović
YRabbit
myrtle
egorxe
Lofty
Gwenhael Goavec-Merou
Simon Richter
Patrick Urban