ripup_arc walks from the sink wire back to the net source, unbinding
pips as it goes. For nets with constant_value set, the walk condition
required every wire on the path to itself carry that constant value
(getWireConstantValue(cursor) == net->constant_value). This is false
for all general-purpose routing wires, so the walk terminated at the
sink immediately and ripup never unbound anything.
Consequences on congested designs with const routing (observed on
himbaechel/xilinx, where GND/VCC use const-net mode):
- re-routing the arc rebound the same path on top of itself, leaking
one wire refcount per ripup/re-route cycle
- congestion on contested constant tap wires could never resolve; the
router livelocked with a handful of wires stuck overused for
thousands of iterations
Constant-net arc trees root at a tap wire bound with a null pip (the
const_mode midpoint bind in route_arc), so terminate the walk there
instead: walk to the net source as usual, and stop at the first
null-pip binding.
Hardware-verified on xc7a100t: a MEGA65 core port (~34k LCs) that
previously livelocked (>3000 iterations, 6 wires pinned overused) now
routes to 0 overused wires in ~30 iterations.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Define open_(o|i)fstream_and_log_error in log.h to:
- quote 'filename'
- add error cause to easier troubleshoot
- use existing consistent string style
- easily allows OS specific message
Introduce it when file are opened and add it where error message
was missing.
* gatemate: add alternate clock routes
* use additional pins
* Fix clock router and timings
* Fix DDR nets
* Test passtrough concept
* remove not used variable
* wip
* handle pip masks
* Cleanup
* create CPE_CPLINES cells and set properties on them
* Fix pip masking
* rough code to break cplines into subnets
* add ports to cell
* mux bridges need cell bel pins too
* fix multiplier output register packing
* remove empty if
* Fix ODDR
* Add options to disable some pips
* Use resources info
* mask field to resource field
* produce valid netlist with propagation netlist at least
* adapt reassign_cplines for internal resource pips
* Handle block and resources
* fix formatting
* It is required to set all mandatory properties now
* arch API for resources
* current progress
* Add option to skip bridges
* perform per-wire resource congestion costing
* Added no-cpe-cp option
* resource bugfix
* comment out spammy debug message
* Fix routing conflicts issues
* allow only some pass trough for clock router
* handle inversion bits for pass signals
* verify inversion before/after assigning bridges
* we care only if there is net
* Revert "we care only if there is net"
This reverts commit 3da2769e31.
* Revert "verify inversion before/after assigning bridges"
This reverts commit 8613ee17c8.
* chipdb version bump
* clangformat
* cleanup
* cleanup
* Initial conversion to GroupId
* Keep group info in pip extra
* Cleanup headers
* Initialize resource efficiently
* Addressing review comments
* improve resource docs
* Make CP lines not use as clocks as default
---------
Co-authored-by: Lofty <dan.ravensloft@gmail.com>
The two main changes, done together in this commit, are:
* Eliminating most instances of `aux_source_directory()`, replacing
them with explicit file listings; and
* Moving these file listings into respective subdirectories by
representing respective nextpnr components as interface libraries.
In addition, the GUI CMake script tree was simplified since it had
a lot of unused/redundant code.
The `aux_source_directory()` command is not recommended for use by
CMake itself because it misses dependency changes when adding/removing
files, and consequently causes build failures requiring a clean rebuild.
This commit does not touch anything related to architectures/families,
which are very complex and redundant all on their own.
When implementing concepts such as partition pins or deliberately split
nets, there's a need for something that looks like a cell (starts/ends
routing with pins on nets, has timing data) but isn't mapped to a fixed
bel in the architecture, but instead can have pin mappings defined at
runtime.
The PseudoCell allows this by providing an alternate, virtual-function
based API for such cells. When a cell has `pseudo_cell` used, instead of
calling functions such as getBelPinWire, getBelLocation or getCellDelay
in the Arch API; such data is provided by the cell itself, fully
flexible at runtime regardless of arch, via methods on the PseudoCell
implementation.
Joris van Zwieten
gatecat
mrcmry
Lunaphied
Miodrag Milanović
Lofty
Catherine
Rowan Goemans