Merge branch 'master' into netgen-1.5

copy if the property record does not have a model.class record
(should it always?).

VERSION

@@ -1 +1 @@
-1.5.152
+1.5.162

base/netcmp.c

@@ -158,6 +158,9 @@ int right_col_end = 87;
 /* if TRUE, always partition ALL classes */
 int ExhaustiveSubdivision = 0;
 
+/* if TRUE, use fast symmetry breaking to resolve automorphisms */
+int FastSymmetryBreaking = 1;
+
 #ifdef TEST
 static void PrintElement_List(struct Element *E)
 {
@@ -5246,6 +5249,12 @@ void DumpNetworkAll(char *model, int file)
 /* NOTE:  ob1 must belong to Circuit1, and ob2 must belong to	*/
 /* Circuit2.  The calling procedure is responsble for ensuring	*/
 /* that this is true.						*/
+/*								*/
+/* NOTE:  This routine assumes that if file1 == file2 or if	*/
+/* file2 != Circuit1->graph, then "do_print" is FALSE.  It 	*/
+/* hard-codes "Circuit 1" and "Circuit 2" in most print		*/
+/* statements.  file1 == file2 only when checking properties	*/
+/* for symmetry breaking, where nothing is printed.		*/
 /*--------------------------------------------------------------*/
 
 #ifdef TCL_NETGEN
@@ -5253,8 +5262,9 @@ Tcl_Obj *
 #else
 void
 #endif
-PropertyMatch(struct objlist *ob1, struct objlist *ob2, int do_print,
-		int do_list, int *retval)
+PropertyMatch(struct objlist *ob1, int file1,
+		struct objlist *ob2, int file2,
+		int do_print, int do_list, int *retval)
 {
    struct nlist *tc1, *tc2;
    struct objlist *tp1, *tp2, *obn1, *obn2;
@@ -5268,8 +5278,22 @@ PropertyMatch(struct objlist *ob1, struct objlist *ob2, int do_print,
    Tcl_Obj *proplist = NULL, *mpair, *mlist;
 #endif
 
-   tc1 = LookupCellFile(ob1->model.class, Circuit1->file);
-   tc2 = LookupCellFile(ob2->model.class, Circuit2->file);
+   tc1 = LookupCellFile(ob1->model.class, file1);
+   tc2 = LookupCellFile(ob2->model.class, file2);
+
+   if (tc1 == NULL || tc2 == NULL) {
+      if (tc1 == NULL)
+	 Fprintf(stdout, "Error:  Circuit %d device \"%s\" not found!\n",
+		    file1, ob1->model.class);
+      else
+	 Fprintf(stdout, "Error:  Circuit %d device \"%s\" not found!\n",
+		    file2, ob2->model.class);
+#ifdef TCL_NETGEN
+      return NULL;
+#else
+      return;
+#endif
+   }
 
    if (tc1->classhash != tc2->classhash) {
       *retval = -1;
@@ -5550,9 +5574,11 @@ PropertyCheck(struct ElementClass *EC, int do_print, int do_list, int *rval)
       E2 = Etmp;
    }
 #ifdef TCL_NETGEN
-   return PropertyMatch(E1->object, E2->object, do_print, do_list, rval);
+   return PropertyMatch(E1->object, E1->graph, E2->object, E2->graph,
+		do_print, do_list, rval);
 #else
-   PropertyMatch(E1->object, E2->object, do_print, do_list, rval);
+   PropertyMatch(E1->object, E1->graph, E2->object, E2->graph,
+		do_print, do_list, rval);
 #endif
 }
 
@@ -5791,10 +5817,8 @@ int ResolveAutomorphsByProperty()
 		badmatch = FALSE;
 		for (E2 = E1->next; E2 != NULL; E2 = E2->next) {
 		    if (E2->hashval != orighash) continue;
-		    if (E1->graph == Circuit1->file) 
-			PropertyMatch(E1->object, E2->object, FALSE, FALSE, &result);
-		    else
-			PropertyMatch(E2->object, E1->object, FALSE, FALSE, &result);
+		    PropertyMatch(E1->object, E1->graph, E2->object, E2->graph,
+			    FALSE, FALSE, &result);
 		    if (result == 0) {
 			E2->hashval = newhash;
 			if (E2->graph == E1->graph)
@@ -5841,7 +5865,81 @@ int ResolveAutomorphsByProperty()
 /*
  *-------------------------------------------------------------------------
  *
- * ResolveElementAutomorphisms --
+ * ResolveAutormorphismsFull --
+ *
+ * Arbitrarily equivalence one pair of elements within an automorphic class
+ *
+ * Return value is the same as VerifyMatching()
+ *
+ *-------------------------------------------------------------------------
+ */
+
+int ResolveAutomorphismsFull()
+{
+  struct ElementClass *EC;
+  struct Element *E;
+  struct NodeClass *NC;
+  struct Node *N;
+  int C1, C2;
+
+  for (EC = ElementClasses; EC != NULL; EC = EC->next) {
+    struct Element *E1, *E2;
+    C1 = C2 = 0;
+    E1 = E2 = NULL;
+    for (E = EC->elements; E != NULL; E = E->next) {
+      if (E->graph == Circuit1->file) {
+	C1++;
+	E1 = E;
+      }
+      else {
+	C2++;
+	E2 = E;
+      }
+    }
+    if (C1 == C2 && C1 != 1) {
+      unsigned long newhash;
+      Magic(newhash);
+      E1->hashval = newhash;
+      E2->hashval = newhash;
+      goto converge;
+    }
+  }
+
+  for (NC = NodeClasses; NC != NULL; NC = NC->next) {
+    struct Node *N1, *N2;
+    C1 = C2 = 0;
+    N1 = N2 = NULL;
+    for (N = NC->nodes; N != NULL; N = N->next) {
+      if (N->graph == Circuit1->file) {
+	C1++;
+	N1 = N;
+      }
+      else {
+	C2++;
+	N2 = N;
+      }
+    }
+    if (C1 == C2 && C1 != 1) {
+      unsigned long newhash;
+      Magic(newhash);
+      N1->hashval = newhash;
+      N2->hashval = newhash;
+      goto converge;
+    }
+  }
+
+ converge:
+  FractureElementClass(&ElementClasses);
+  FractureNodeClass(&NodeClasses);
+  ExhaustiveSubdivision = 1;
+  while (!Iterate() && VerifyMatching() != -1);
+  return(VerifyMatching());
+}
+
+/*
+ *-------------------------------------------------------------------------
+ *
+ * ResolveElementAutomorphismsFast --
  *
  * Apply arbitrary symmetry breaking to symmetric element lists, then
  * iterate exhaustively to resolve all automorphisms.
@@ -5851,7 +5949,7 @@ int ResolveAutomorphsByProperty()
  *-------------------------------------------------------------------------
  */
 
-int ResolveElementAutomorphisms()
+int ResolveElementAutomorphismsFast()
 {
   struct ElementClass *EC;
   struct Element *E;
@@ -5903,7 +6001,7 @@ int ResolveElementAutomorphisms()
 /*
  *-------------------------------------------------------------------------
  *
- * ResolveNodeAutomorphisms --
+ * ResolveNodeAutomorphismsFast --
  *
  * Apply arbitrary symmetry breaking to symmetric node lists, then iterate
  * exhaustively to resolve all automorphisms.  Normally, all automorphisms
@@ -5916,7 +6014,7 @@ int ResolveElementAutomorphisms()
  *
  */
 
-int ResolveNodeAutomorphisms()
+int ResolveNodeAutomorphismsFast()
 {
   struct Node *N;
   struct NodeClass *NC;
@@ -5970,7 +6068,20 @@ int ResolveNodeAutomorphisms()
  *
  * ResolveAutormorphisms --
  *
- * Arbitrarily equivalence one pair of elements within an automorphic class
+ * Do symmetry breaking of automorphisms.  If FastSymmetryBreaking is
+ * False (not the default), then run ResolveAutomorphismsFull() (q.v.).
+ * Otherwise, run the fast symmetry breaking method:
+ *
+ * Arbitrarily equivalence all pairs of elements and nodes within all
+ * automorphic classes, and run to completion.  Note that this is a
+ * fast version of ResolveAutomorphismsFull(), and can run many orders
+ * of magnitude faster.  However, it can also produce an incorrect
+ * result, declaring a global mismatch where none exists.  In that
+ * case, the matching should be re-run with ResolveAutomorphismsFull().
+ *
+ * Some investigation needs to be done to determine if there is a way
+ * to execute faster symmetry breaking without the possibility of
+ * producing an incorrect result.
  *
  * Return value is the same as VerifyMatching()
  *
@@ -5981,9 +6092,12 @@ int ResolveAutomorphisms()
 {
     int result;
 
-    result = ResolveElementAutomorphisms();
+    if (FastSymmetryBreaking == 0)
+	return ResolveAutomorphismsFull();
+
+    result = ResolveElementAutomorphismsFast();
     if (result != 0)
-	result = ResolveNodeAutomorphisms();
+	result = ResolveNodeAutomorphismsFast();
 
     return result;
 }
@@ -6918,6 +7032,8 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
       if (*(cover + i) == (char)0) {
 	 j = 0;
          for (ob2 = tc2->cell; ob2 != NULL; ob2 = ob2->next) {
+	    char *name1, *name2;
+
 	    if (!IsPort(ob2)) break;
 
 	    bangptr2 = strrchr(ob2->name, '!');
@@ -6925,7 +7041,14 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
 	       *bangptr2 = '\0';
 	    else bangptr2 = NULL;
 
-	    if ((*matchfunc)(ob1->name, ob2->name)) {
+	    name1 = ob1->name;
+	    name2 = ob2->name;
+
+	    /* Recognize proxy pins as matching */
+	    if (!strncmp(name1, "proxy", 5)) name1 +=5;
+	    if (!strncmp(name2, "proxy", 5)) name2 +=5;
+
+	    if ((*matchfunc)(name1, name2)) {
 	       ob2->model.port = i;		/* save order */
 	       *(cover + i) = (char)1;
 
@@ -7032,7 +7155,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
          obn->name = (char *)MALLOC(6 + strlen(ob2->name));
          sprintf(obn->name, "proxy%s", ob2->name);
          obn->type = UNKNOWN;
-         obn->model.port = -1;
+         // obn->model.port = -1;
          obn->instance.name = NULL;
          obn->node = -1;
 	 if (ob1 == tc1->cell) {
@@ -7102,6 +7225,25 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
          obn->instance.name = NULL;
          obn->node = -1;
 
+#if 0
+	 /* Note:  This pin has already been accounted for */
+	 if (Debug == 0) {
+	    if (strcmp(ob1->name, "(no pins)")) {
+	       for (m = 0; m < left_col_end; m++) *(ostr + m) = ' ';
+	       for (m = left_col_end + 1; m < right_col_end; m++) *(ostr + m) = ' ';
+	       snprintf(ostr, left_col_end, "%s", ob1->name);
+	       snprintf(ostr + left_col_end + 1, left_col_end, "(no matching pin)");
+	       for (m = 0; m < right_col_end + 1; m++)
+		  if (*(ostr + m) == '\0') *(ostr + m) = ' ';
+	       Fprintf(stdout, ostr);
+	    }
+	 }
+	 else {
+	    Fprintf(stderr, "No netlist match for cell %s pin %s\n",
+				tc1->name, ob1->name);
+	 }
+#endif
+
 	 if (ob2 == tc2->cell) {
 	    obn->next = ob2;
 	    tc2->cell = obn;
@@ -7405,7 +7547,8 @@ static void handler(int sig)
 /*----------------------------------------------------------------------*/
 /* Note that this cover-all routine is not called from the Tcl/Tk	*/
 /* version, which replaces it with the script "lvs".			*/
-/* return 1 if the two are identical.  Try to resolve automorphisms.	*/
+/* return 1 if the two are identical.  Try to resolve automorphisms	*/
+/* using the original "full" symmetry breaking algorithm.		*/
 /*----------------------------------------------------------------------*/
 
 int Compare(char *cell1, char *cell2)

base/netcmp.h

@@ -7,6 +7,7 @@ extern struct nlist *Circuit1;
 extern struct nlist *Circuit2;
 
 extern int ExhaustiveSubdivision;
+extern int FastSymmetryBreaking;
 
 extern int left_col_end;
 extern int right_col_end;

base/netgen.c

@@ -2470,7 +2470,8 @@ void CopyProperties(struct objlist *obj_to, struct objlist *obj_from)
       kvcur->value.ival = 0;
 
       obj_to->instance.props = kvcopy;
-      obj_to->model.class = strsave(obj_from->model.class);
+      if (obj_from->model.class)
+         obj_to->model.class = strsave(obj_from->model.class);
    }
 }
 
@@ -3583,8 +3584,8 @@ int CombineSeries(char *model, int file)
 
 	    /* Excise the 2nd instance.  instlist[i][1] remains as the	*/
 	    /* only pointer to it.					*/
-            for (obp = instlist[i][0]; obp->next->type > FIRSTPIN ||
-			obp->next->type == PROPERTY; obp = obp->next);
+            for (obp = instlist[i][0]; obp->next && (obp->next->type > FIRSTPIN ||
+			obp->next->type == PROPERTY); obp = obp->next);
             for (ob2 = obp; ob2 && ob2->next != instlist[i][1]; ob2 = ob2->next);
 
 	    /* Device may have been moved by the above code.  If so, look for	*/

base/objlist.c

@@ -1112,13 +1112,17 @@ void FreeObjectAndHash(struct objlist *ob, struct nlist *ptr)
 
 /***************  GENERAL UTILITIES ****************************/
 
-int NumberOfPorts(char *cellname)
+int NumberOfPorts(char *cellname, int file)
 {
   struct nlist *tp;
   struct objlist *ob;
   int ports;
 
-  tp = LookupCell(cellname);
+  if (file == -1)
+    tp = LookupCell(cellname);
+  else
+    tp = LookupCellFile(cellname, file);
+
   if (tp == NULL) return(0);
   ports = 0;
   for (ob = tp->cell; ob != NULL; ob = ob->next)

base/objlist.h

@@ -242,7 +242,7 @@ extern void FreeObjectAndHash(struct objlist *ob, struct nlist *ptr);
 extern void FreePorts(char *cellname);
 extern struct IgnoreList *ClassIgnore;
 
-extern int NumberOfPorts(char *cellname);
+extern int NumberOfPorts(char *cellname, int file);
 extern struct objlist *InstanceNumber(struct nlist *tp, int inst);
 
 extern struct objlist *List(char *list_template);

base/place.c

@@ -929,7 +929,7 @@ void ToggleDebug(void)
 void DescribeCell(char *name, int detail)
 {
   Printf("Cell: %s contains %d instances, %d nodes and %d ports\n", name, 
-	 NumberOfInstances(name),  RenumberNodes(name), NumberOfPorts(name));
+	 NumberOfInstances(name),  RenumberNodes(name), NumberOfPorts(name, -1));
   PrintEmbeddingTree(stdout,name,detail);
 }
 

base/query.c

@@ -801,7 +801,11 @@ void DescribeInstance(char *name, int file)
   {
     if (ob->node > nodemax) nodemax = ob->node;
     else if ((ob->node == -1) && (ob->model.port != PROXY)) {
-      if (!(tp->flags & CELL_PLACEHOLDER))
+
+      /* All black-box modules and placeholders by definition have all	*/
+      /* disconnected pins, so don't report those.			*/
+
+      if (!(tp->flags & CELL_PLACEHOLDER) && (tp->class != CLASS_MODULE))
       {
 	if (disconnectednodes == 0) Fprintf(stderr, "\n");
         disconnectednodes++;
@@ -903,7 +907,7 @@ void PrintLeavesInCell(char *cellname, int filenum)
   np->dumped = 1;
 
   if (np->class != CLASS_SUBCKT) {
-    Printf("%s; %d ports; Primitive.\n", cellname, NumberOfPorts(cellname));
+    Printf("%s; %d ports; Primitive.\n", cellname, NumberOfPorts(cellname, filenum));
     return;
   }
 
@@ -916,7 +920,7 @@ void PrintLeavesInCell(char *cellname, int filenum)
       am_a_leaf = 0;
     }
 
-  if (am_a_leaf) Printf("%s; %d ports\n", cellname, NumberOfPorts(cellname));
+  if (am_a_leaf) Printf("%s; %d ports\n", cellname, NumberOfPorts(cellname, filenum));
   return;
 }
 

base/verilog.c

@@ -553,9 +553,43 @@ void CleanupModule() {
    int maxnode = 0;
    int has_submodules = FALSE;
    struct objlist *sobj, *nobj, *lobj, *pobj;
+   struct objlist *myLastPort, *object_it, *myNextObject;
 
    if (CurrentCell == NULL) return;
 
+   myLastPort = NULL;
+
+   /* Reorder objects so that all ports come first, before nodes, because
+    * parts of the code depend on it.
+    */
+
+   for (object_it = CurrentCell->cell; object_it && object_it->type <= 0;
+		object_it = myNextObject ) {
+
+       myNextObject = object_it->next;
+       if (!myNextObject)	// end of list
+           continue;
+
+       if (myLastPort == NULL) {
+           if (object_it->type == PORT) {
+               myLastPort = object_it;	    // port at begining of list
+               myNextObject = object_it;    // otherwise skips one
+           }
+           else if (myNextObject->type == PORT) {
+               object_it->next = myNextObject->next;
+               myNextObject->next = CurrentCell->cell;
+               CurrentCell->cell = myNextObject;
+               myLastPort = myNextObject;
+           }
+       }
+       else if (myNextObject->type == PORT) {
+	   object_it->next = myNextObject->next;
+	   myNextObject->next = myLastPort->next;
+	   myLastPort->next = myNextObject;
+	   myLastPort = myNextObject;
+       }
+   }
+
    for (sobj = CurrentCell->cell; sobj; sobj = sobj->next)
       if (sobj->node > maxnode)
 	 maxnode = sobj->node + 1;
@@ -1225,7 +1259,12 @@ skip_endmodule:
 		    lhs = LookupObject(nodename, CurrentCell);
 		    *aptr = '[';
 		}
-		else strcpy(noderoot, nexttok);
+		else {
+		    strcpy(noderoot, nexttok);
+		    /* Set LHS to the start of the vector */
+		    sprintf(nodename, "%s[%d]", nexttok, wb.start);
+		    lhs = LookupObject(nodename, CurrentCell);
+		}
 	    }
 	    else {
 		lhs = LookupObject(nexttok, CurrentCell);
@@ -1290,13 +1329,21 @@ skip_endmodule:
 			if (rhs != NULL) {
 			    Printf("Improper assignment;  left-hand side cannot "
 					"be parsed.\n");
-			    Printf("Right-hand side is \"%s\".\n", rhs->name);
+			    if (j != -1)
+			    	Printf("Right-hand side is \"%s\".\n", assignroot);
+			    else
+			    	Printf("Right-hand side is \"%s\".\n", rhs->name);
+			    Printf("Improper expression is \"%s\".\n", nexttok);
 			    break;
 			}
 			if (lhs != NULL) {
 			    Printf("Improper assignment;  right-hand side cannot "
 					"be parsed.\n");
-			    Printf("Left-hand side is \"%s\".\n", lhs->name);
+			    if (i != -1)
+			    	Printf("Left-hand side is \"%s\".\n", noderoot);
+			    else
+			    	Printf("Left-hand side is \"%s\".\n", lhs->name);
+			    Printf("Improper expression is \"%s\".\n", nexttok);
 			    /* Not parsable, probably behavioral verilog? */
 			    Printf("Module '%s' is not structural verilog, "
 				    "making black-box.\n", model);
@@ -1854,7 +1901,7 @@ nextinst:
 		     if (is_bundle &&
 			    ((i == -1) ||
 			    ((wbb.start > wbb.end) && (i < wbb.end)) ||
-			    ((wbb.start < wbb.end) && (i > wbb.end)))) {
+			    ((wbb.start <= wbb.end) && (i > wbb.end)))) {
 		         if (bptr) *bptr = '[';
 
 			 netname = cptr + 1;
@@ -1933,7 +1980,9 @@ nextinst:
 		  sprintf(localnet, "_noconnect_%d_", localcount++);
 		  Node(localnet);
 		  join(localnet, obptr->name);
-		  Fprintf(stderr, "Note:  Implicit pin %s\n", obpinname);
+		  Fprintf(stderr,
+			 "Note:  Implicit pin %s in instance %s of %s in cell %s\n",
+			 obpinname, locinst, modulename, CurrentCell->name);
 	       }
 	       else if (GetBus(scan->net, &wb) == 0) {
 		   char *bptr2;

configure

@@ -4,4 +4,6 @@
 # all of its config scripts in a different directory than the configure
 # script itself.
 
-( CFLAGS="-g" ; export CFLAGS ; cd scripts ; ./configure "$@" )
+export CFLAGS="$CFLAGS -g"
+cd scripts
+exec ./configure "$@"

tcltk/netgen.tcl.in

@@ -382,6 +382,9 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
       } elseif {$arg == "-blackbox"} {
 	 puts stdout "Treating empty subcircuits as black-box cells"
 	 netgen::model blackbox on
+      } elseif {$arg == "-full"} {
+	 puts stdout "Using full symmetry breaking method"
+	 netgen::symmetry full
       }
    }
 
@@ -501,6 +504,7 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
       return
    }
    set properr {}
+   set pinsgood 0
    while {$endval != {}} {
       if {$dolist == 1} {
          netgen::run -list converge
@@ -546,6 +550,7 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
 		equate classes "$fnum1 [lindex $endval 0]" \
 			 "$fnum2 [lindex $endval 1]"
 	    }
+	    set pinsgood $result
             netgen::log echo on
 	 }
 	 if {$uresult == 2} {lappend properr [lindex $endval 0]}
@@ -569,7 +574,11 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
    netgen::log echo off
    puts stdout "Result: " nonewline
    netgen::log echo on
-   verify only
+   if {$pinsgood == 0} {
+      netgen::log put "The top level cell failed pin matching.\n"
+   } else {
+      verify only
+   }
    if {$properr != {}} {
       netgen::log put "The following cells had property errors: $properr\n"
    }

tcltk/tclnetgen.c

@@ -94,6 +94,7 @@ int _netcmp_ignore(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_permute(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_property(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_exhaustive(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
+int _netcmp_symmetry(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_restart(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_global(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_convert(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
@@ -244,6 +245,9 @@ Command netcmp_cmds[] = {
 	{"exhaustive",		_netcmp_exhaustive,
 		"\n   "
 		"toggle exhaustive subdivision"},
+	{"symmetry",		_netcmp_symmetry,
+		"[fast|full]\n   "
+		"apply method for symmetry breaking"},
 	{"restart",		_netcmp_restart,
 		"\n   "
 		"start over (reset data structures)"},
@@ -1532,23 +1536,24 @@ int
 _netgen_model(ClientData clientData,
     Tcl_Interp *interp, int objc, Tcl_Obj *CONST objv[])
 {
-   struct nlist *tp;
+   struct nlist *tp, *tp2;
    char *model, *retclass;
    unsigned char class;
    int fnum = -1;
-   int result, index, nports;
+   int result, index, nports, nports2;
 
    char *modelclasses[] = {
       "undefined", "nmos", "pmos", "pnp", "npn",
       "resistor", "capacitor", "diode",
       "inductor", "module", "blackbox", "xline",
-      "moscap", "mosfet", "bjt", "subcircuit", NULL
+      "moscap", "mosfet", "bjt", "subcircuit", "copy",
+      NULL
    };
    enum OptionIdx {
       UNDEF_IDX,  NMOS_IDX, PMOS_IDX, PNP_IDX, NPN_IDX,
       RES_IDX, CAP_IDX, DIODE_IDX, INDUCT_IDX,
       MODULE_IDX, BLACKBOX_IDX, XLINE_IDX, MOSCAP_IDX,
-      MOSFET_IDX, BJT_IDX, SUBCKT_IDX
+      MOSFET_IDX, BJT_IDX, SUBCKT_IDX, COPY_IDX
    };
 
    if (objc != 3 && objc != 2) {
@@ -1580,7 +1585,7 @@ _netgen_model(ClientData clientData,
 
    if (objc == 3) {
       model = Tcl_GetString(objv[2]);
-      nports = NumberOfPorts(model);
+      nports = NumberOfPorts(model, fnum);
 
       if (Tcl_GetIndexFromObj(interp, objv[2], (CONST84 char **)modelclasses,
 		"class", 0, &index) != TCL_OK) {
@@ -1644,6 +1649,40 @@ _netgen_model(ClientData clientData,
 	    break;
 	 case SUBCKT_IDX:
 	    class = CLASS_SUBCKT;
+	    break;
+	 case COPY_IDX:
+	    /* "copy" is not a class, but indicates that the cell,  */
+	    /* if undefined or a module, should have its class	    */
+	    /* taken from the other circuit, if that circuit has a  */
+	    /* cell of the same name.				    */
+	    if (Circuit1 == NULL || Circuit2 == NULL) {
+		Tcl_SetResult(interp, "Circuits have not been queued for comparison.",
+			NULL);
+		return TCL_ERROR;
+	    }
+	    if (tp == Circuit1) {
+		tp2 = LookupCellFile(tp->name, Circuit2->file);
+		nports2 = NumberOfPorts(tp2->name, Circuit2->file);
+	    }
+	    else if (tp == Circuit2) {
+		tp2 = LookupCellFile(tp->name, Circuit1->file);
+		nports2 = NumberOfPorts(tp2->name, Circuit1->file);
+	    }
+	    else {
+		Tcl_SetResult(interp, "The referenced netlist is not being compared.",
+			NULL);
+		return TCL_ERROR;
+	    }
+	    /* Should a non-matching number of ports be considered a fatal error? */
+	    // if (nports2 != nports) {
+	    //	Tcl_SetResult(interp, "The number of ports for this cell does not "
+	    //		"match between netlists.", NULL);
+	    //	return TCL_ERROR;
+	    // }
+
+	    class = tp2->class;
+	    /* To do (maybe): Rename tp ports to match tp2? */
+
 	    break;
       }
       tp->class = class;
@@ -3937,6 +3976,48 @@ _netcmp_permute(ClientData clientData,
    return TCL_OK;
 }
 
+/*------------------------------------------------------*/
+/* Function name: _netcmp_symmetry			*/
+/* Syntax: netgen::symmetry [fast|full]			*/
+/* Formerly: x						*/
+/* Results:						*/
+/* Side Effects:					*/
+/*------------------------------------------------------*/
+
+int
+_netcmp_symmetry(ClientData clientData,
+    Tcl_Interp *interp, int objc, Tcl_Obj *CONST objv[])
+{
+   char *fastfull[] = {
+      "fast", "full", NULL
+   };
+   enum OptionIdx {
+      FAST_IDX, FULL_IDX
+   };
+   int result, index;
+
+   if (objc == 1)
+      index = -1;
+   else {
+      if (Tcl_GetIndexFromObj(interp, objv[1], (CONST84 char **)fastfull,
+		"option", 0, &index) != TCL_OK)
+         return TCL_ERROR;
+   }
+
+   switch(index) {
+      case FAST_IDX:
+	 FastSymmetryBreaking = TRUE;
+	 break;
+      case FULL_IDX:
+	 FastSymmetryBreaking = FALSE;
+	 break;
+   }
+   Printf("Symmetry breaking method: %s.\n", 
+	     FastSymmetryBreaking ? "FAST" : "FULL");
+
+   return TCL_OK;
+}
+
 /*------------------------------------------------------*/
 /* Function name: _netcmp_exhaustive			*/
 /* Syntax: netgen::exhaustive [on|off]			*/
@@ -3958,7 +4039,7 @@ _netcmp_exhaustive(ClientData clientData,
    int result, index;
 
    if (objc == 1)
-      index = YES_IDX;
+      index = -1;
    else {
       if (Tcl_GetIndexFromObj(interp, objv[1], (CONST84 char **)yesno,
 		"option", 0, &index) != TCL_OK)