<col2_width>" to set the output format width, to avoid the fixed column
widths of 41 characters which can truncate long strings in the output
such as deep cell hierarchies. This command can be placed in the setup
script to widen the output columns to accomodate the result (to-do:
provide an "auto" mode to automatically determine the best width).
with increment/decrement syntax at the end. Also the parser now
handles additional keywords associated with behavioral verilog
(initial, specify) and flags modules with them as black-box entries.
that affects vectors sliced across instance arrays. Can cause vector
numbers to be out-of-bounds if an instance is arrayed but each
instance is listed separately.
inline-I/O syntax with "wire" (e.g., "input wire [3:0] test")
and addressed the failure to add buses declared in inline I/O
to the list of known buses.
verilog parser. The parser should now be able to handle any
conditionals anywhere in the verilog code. Also a bug was found
in the code that handles "a = b" assignments, and corrected.
code using the backtick expression. Also expanded the parsing of
"ifdef", "ifndef", and "endif" to include "elsif" and "else". All
forms of "if" statements should now be handled, since verilog does
not define boolean expressions in ifdef operators like most languages
do.
SPICE and verilog, in spite of the syntactical differences, to
account for the trick that qflow uses to replace the trailing space
in a verilog backslash-escaped name with a second backslash to get
a SPICE-compatible name that can be easily converted back to its
original verilog name without loss of information. What this means
is that verilog can read SPICE files containing verilog names (which
is illegal SPICE) and verilog files containing hacked-backslash
names (which is illegal verilog). This should be mostly harmless
although the wisdom of it is surely questionable.
assignment statements in verilog netlists, including assignment of
signal bundles. Also corrected handling of signal bundles in pin
connections, which had been corrected in qflow's verilog parser but
not copied back to netgen. Note that the syntax for signals multiplied
N times is still not handled.
a "critical property". This lets a device define multiple critical
properties, all of which must match before additive properties can
be combined in the same device.
re-worked property command, "critical" properties must match
across devices so that all other properties can be combined as
specified (addition, parallel combination, or none). The code was
still based on the older notion of the "critical" property being
the one to add (and thus preventing multiple properties from being
added in different ways). This has now been fixed.
handle verilog syntax. Also: Added SPICE voltage and current
sources as separate classes (as opposed to being converted to
subcircuits, which was how they were previously handled). That
allowed voltage sources to be checked for zero value and removed
by shorting the ends together, as was being done for zero value
resistors (note that like zero-value resistors, removal is only
done if removing the component makes a better match than leaving
it in). In particular, yosys has SPICE netlist output that
converts equality assignments ("assign a = b") into zero-value
voltage sources, so these components need to be treated as
non-physical elements.
the possibility that a device (e.g., resistor or capacitor) may
not be a semiconductor device (in other words, a parasitic or
ideal device), and therefore uses "value" but not width and
length, and therefore "value" is a critical property to merge
both in series and parallel. Corrected the series/parallel
network optimization to prevent it from setting both M and S
records > 1 on the same device (which is ambiguous). To try
to get number of devices to match, where there are both series
and parallel devices, they will be merged across the critical
property early (before property matching).
accidentally erasing array delimiters from node names, a move that
surprisingly has no effect at all on LVS until the cell containing
the truncated nodes is flattened, at which point it causes odd and
confusing behavior that seems to have nothing to do with node names
at all.
type double before sorting (previously, property promotion was
being done after parallel sorting). Also, modified the verilog
file reading so that parameters and definitions that are numeric
are stored as numeric (not string) properties.
perfect). Given the complexities of the verilog language, the simple
strtok() tokenizer used by the SPICE parser is not sufficient. Wrote
a better tokenizer that can distinguish between whitespace and
functional tokens like parentheses, semicolons, etc., which are tokens
themselves but also token separators.
determine if a parameter is a floating-point number, integer, or
string, and set the parameter accordingly. Found an error in the
parameter comparison if the subcircuit definitions don't agree
on the type of parameter. Now all values are promoted to a single
type based on preference order (double, integer, string). Tested
on a verilog file with a primitive device type defined as a module
with its properties encoded as parameters. This successfully
matched against the SPICE primitive device.
CDL syntax) parameters that have values which are multi-word and
space separated (who the hell comes up with these things?). One
can presumably safely assume that additional pin names are not
intermixed with parameters, so now if a multi-token parameter
value is encountered, the first word is taken as the value and
the remaining words are ignored, generating a warning message.
Since I have no idea what these values are used for, I cannot say
with certainty whether or not this would break LVS, but in the
test case given to me, the parameter had no impact on LVS, but
was apparently an annotation for the layout editor.
ifndef, endif conditional statements. Pre-define the key "LVS"
for use with netgen. Also corrected some problems stemming from
the way delimiters are handled and the flexible use of whitespace
in verilog.
be in any specific order since all ports are named. Also corrected
problem with pin names not using the same string matching function
as used for nets in general (which affects the ability to match
against different bus delimiters).
some problems stemming from comparing a case-sensitive netlist
against a case-insensitive one. Verilog netlist reading does
not yet have support for macros other than "`include", and it
does not yet have support for bit vectors constructed with
braces ({}).
calls "equate pins". This could fail because the routine that forces
uniqueness of pins was being called by the "compare" command but
outside of PinMatch. Fixed by duplicating the call to force uniqueness
of pins inside the "equate" function. Redundant calls should not
matter as uniqueness is resolved on the first call and subsequent calls
will need no further action.
time warnings and errors. Removed the "-lazy" option from the
Tcl load command, which is not needed when the stubs libraries
are compiled in correctly, and which causes issues on some
systems (e.g., Mac OS). Thanks to Matt Guthaus for the patch.
from a ".include" line by trying alternate extensions. This
should be discouraged, as it happened that a file included
"name.defparams", a file that didn't exist, and instead of calling
out the missing file, it recast it to "name.spice" and caused it
to drop into an infinite loop. Oops.
the default before comparing instances against each other for
serial/parallel combination. In particular, this avoids a
failure to serially combine a device with M = 1 vs. a device with
no M declared.
Netgen was incorrectly treating mismatched networks as a missing
set of parameters on whichever device had more property records,
resulting in misleading output.
attempt to resolve values by combining over serial chains was
attempting to access a property "S" in the component's master
record, which generally won't exist unless it has been explicitly
set in the netlist (which is unlikely since "S" is not a standard
SPICE/CDL parameter like "M").
misses a device if it has been already moved due to earlier
merging in the serial combine routine, and runs off the end of
the list; the other if the pin check routine falls on the last
device in the list, leading to an incorrect check for a record
where there is only a NULL.
unordered at the time of reaching reorderpins(). Pins will be
ordered arbitrarily (in the order of appearance in the linked
list), but netgen will not crash.
for subcircuits (.subckt ... .ends pair with cellname and pin names
and pin order, but no contents) are automatically treated as black-
box circuits if found and if the "-blackbox" option is passed to the
"lvs" (scripted) command. The "equate pins" command can be used
outside of a comparison to force two circuits (black-box or
otherwise) to be matched by pin name (if not a black-box circuit,
then this is a provisional name match, as a circuit comparison will
order based on connectivity first, not pin names). So two sets of
black-box circuit libraries can be used as long as their pin names
match. One hack added to ignore the "!" at the end of global names
when comparing pin names for matching. Otherwise, pin names must
compare by case-insensitive string match.
Tim Edwards