f0cf6b52d3
Merge branch 'master' into work
2018-11-14 13:46:14 -05:00
9432bfc182
Update at Wed Nov 14 13:46:12 EST 2018 by tim
2018-11-14 13:46:12 -05:00
4fb892a64f
Fixed configure script error that reports python3 as being
...
configured even when it is not found on the system. This was only
a reporting error, and had no other repercussions.
2018-11-14 13:45:02 -05:00
faadb78870
Merge branch 'master' into work
2018-11-12 16:33:17 -05:00
7fc668c2d4
Update at Mon Nov 12 16:33:14 EST 2018 by tim
2018-11-12 16:33:14 -05:00
13c45c6d0c
Encountered a problem with parsing non-inlined ports of a module and
...
tracked it down to a "to be completed" comment in the source code.
So it is now completed.
2018-11-12 16:32:33 -05:00
5efe2151ed
Merge branch 'master' into work
2018-10-31 14:05:11 -04:00
642de57418
Update at Wed Oct 31 14:05:09 EDT 2018 by tim
2018-10-31 14:05:09 -04:00
397444acd3
Modified the JSON generation script to backslash-escape backslashes
...
in verilog net names, which are apparently legal in verilog but not
in python strings (if not escaped). This is somewhat critical for
running the LVS GUI as yosys can generate backslashes in generated
net names in the synthesized netlist.
2018-10-31 14:03:15 -04:00
5e5720e7be
Merge branch 'master' into work
2018-10-29 15:19:57 -04:00
65c0f6b840
Update at Mon Oct 29 15:19:54 EDT 2018 by tim
2018-10-29 15:19:54 -04:00
09b2bb3316
Extended the verilog parser to account for the fact that there can
...
be whitespace between a wire/register name and its array delimiter.
2018-10-29 15:19:13 -04:00
41665036e9
Merge branch 'master' into work
2018-10-02 14:41:40 -04:00
b4c189a114
Update at Tue Oct 2 14:41:38 EDT 2018 by tim
2018-10-02 14:41:38 -04:00
85af816ab8
Removed references to /usr/local/man/man1 and netgen.1, as the netgen.1
...
man page does not exist. Running mkdirs on the empty directory causes
problems with "git rm".
2018-10-02 14:40:17 -04:00
4ba5425b6a
Merge branch 'master' into work
2018-09-26 10:49:06 -04:00
83b2084a10
Update at Wed Sep 26 10:49:04 EDT 2018 by tim
2018-09-26 10:49:04 -04:00
0de1c232e4
Corrected property matching so that properties are promoted to
...
type double before sorting (previously, property promotion was
being done after parallel sorting). Also, modified the verilog
file reading so that parameters and definitions that are numeric
are stored as numeric (not string) properties.
2018-09-26 10:46:55 -04:00
b8e6f6c030
Merge branch 'master' into work
2018-09-24 15:13:32 -04:00
a6742bca2e
Update at Mon Sep 24 15:13:30 EDT 2018 by tim
2018-09-24 15:13:30 -04:00
3a03e769af
Substantially improved verilog parsing (although almost certainly not
...
perfect). Given the complexities of the verilog language, the simple
strtok() tokenizer used by the SPICE parser is not sufficient. Wrote
a better tokenizer that can distinguish between whitespace and
functional tokens like parentheses, semicolons, etc., which are tokens
themselves but also token separators.
2018-09-24 15:09:29 -04:00
445f732f8b
Merge branch 'master' into work
2018-08-08 11:28:45 -04:00
b911aa7b2e
Update at Wed Aug 8 11:28:43 EDT 2018 by tim
2018-08-08 11:28:43 -04:00
b979d0ad97
Changed the netgen shell script from "sh" to "bash" due to the
...
presence of one or more bash-isms in the code. Thanks to Sean
Cross for the patch.
2018-08-08 11:28:04 -04:00
86ab771964
Merge branch 'master' into work
2018-08-01 15:44:34 -04:00
2d74b3d94b
Update at Wed Aug 1 15:44:32 EDT 2018 by tim
2018-08-01 15:44:32 -04:00
036e1f0947
Modified the verilog reading code so that it will automatically
...
determine if a parameter is a floating-point number, integer, or
string, and set the parameter accordingly. Found an error in the
parameter comparison if the subcircuit definitions don't agree
on the type of parameter. Now all values are promoted to a single
type based on preference order (double, integer, string). Tested
on a verilog file with a primitive device type defined as a module
with its properties encoded as parameters. This successfully
matched against the SPICE primitive device.
2018-08-01 15:40:23 -04:00
5223011330
Merge branch 'master' into work
2018-06-25 21:26:47 -04:00
7bde5125fd
Update at Mon Jun 25 21:26:47 EDT 2018 by tim
2018-06-25 21:26:47 -04:00
dd6145463e
Modified the SPICE parser to at least sanely deal with (possibly
...
CDL syntax) parameters that have values which are multi-word and
space separated (who the hell comes up with these things?). One
can presumably safely assume that additional pin names are not
intermixed with parameters, so now if a multi-token parameter
value is encountered, the first word is taken as the value and
the remaining words are ignored, generating a warning message.
Since I have no idea what these values are used for, I cannot say
with certainty whether or not this would break LVS, but in the
test case given to me, the parameter had no impact on LVS, but
was apparently an annotation for the layout editor.
2018-06-25 21:21:45 -04:00
f4ff74783c
Merge branch 'master' into work
2018-06-17 15:06:17 -04:00
f3d850e68e
Update at Sun Jun 17 15:06:17 EDT 2018 by tim
2018-06-17 15:06:17 -04:00
1c08e5a48d
Corrected missing tcl.h includes, which are needed in files that
...
call FREE(), since the Tcl/Tk version makes that a macro for the
subroutine Tcl_Free(). Thanks to Laurent Charrier for the bug
fix.
2018-06-17 15:05:15 -04:00
821145f9c1
Merge branch 'master' into work
2018-06-01 08:47:34 -04:00
6eb1efd55a
Update at Fri Jun 1 08:47:33 EDT 2018 by tim
2018-06-01 08:47:33 -04:00
6d569ca396
Added a missing top-level clean to the Makefile, which is mainly
...
responsible for removing the log files. Otherwise the log files
just keep accumulating output forever.
2018-06-01 08:46:52 -04:00
7a0bff846f
Merge branch 'master' into work
2018-05-28 21:39:13 -04:00
ced1299351
Update at Mon May 28 21:39:11 EDT 2018 by tim
2018-05-28 21:39:11 -04:00
f213376bfd
Removed "Depend" from the .gitignore file, as compilation depends
...
on it and fails the first time if it does not exist, requiring
running "make" twice (which is not advertised in the build
instructions).
2018-05-28 21:37:35 -04:00
223b197b71
Merge branch 'master' into work
2018-05-23 13:05:17 -04:00
f0eb14be5e
Update at Wed May 23 13:05:15 EDT 2018 by tim
2018-05-23 13:05:15 -04:00
534ea839c0
Revised the verilog parser to correctly identify and parse
...
parameters passed to instances, so that these can match critical
parameters in the SPICE netlist being compared against.
2018-05-23 13:04:31 -04:00
b721cacb40
Merge branch 'master' into work
2018-05-01 14:08:18 -04:00
84f984e7f0
Update at Tue May 1 14:08:16 EDT 2018 by tim
2018-05-01 14:08:16 -04:00
25ac57d103
First pass at incorporating the efabless LVS manager GUI into the
...
netgen distribution. It sort of works, but not quite there yet.
2018-05-01 14:07:16 -04:00
02a77b61f9
Merge branch 'master' into work
2018-04-26 08:01:20 -04:00
dfd1e59432
Update at Thu Apr 26 08:01:18 EDT 2018 by tim
2018-04-26 08:01:18 -04:00
f14ebf323f
Fixed a script error that caused pins not to be reported in the
...
Tcl list and JSON formatted outputs.
2018-04-26 08:00:47 -04:00
62648c5672
Merge branch 'master' into work
2018-04-25 15:03:18 -04:00
7d113beada
Update at Wed Apr 25 15:03:16 EDT 2018 by tim
2018-04-25 15:03:16 -04:00
Tim Edwards
Tim Edwards